STK5Q4U362J-E [ONSEMI]

智能功率模块 (IPM),600V,10A;
STK5Q4U362J-E
型号: STK5Q4U362J-E
厂家: ONSEMI    ONSEMI
描述:

智能功率模块 (IPM),600V,10A

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STK5Q4U362J-E  
Advance Information  
Intelligent Power Module (IPM)  
600 V, 10 A  
The STK5Q4U362J-E is a fully-integrated inverter power stage  
consisting of a high-voltage driver, six IGBT’s and a thermistor, suitable  
for driving permanent magnet synchronous (PMSM) motors, brushless-  
DC (BLDC) motors and AC asynchronous motors. The IGBT’s are  
configured in a 3-phase bridge with separate emitter connections for the  
lower legs for maximum flexibility in the choice of control algorithm.  
The power stage has a full range of protection functions including cross-  
conduction protection, external shutdown and under-voltage lockout  
functions. An internal comparator and reference connected to the over-  
current protection circuit allows the designer to set the over-current  
protection level.  
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PACKAGE PICTURE  
Features  
Three-phase 10 A / 600 V IGBT module with integrated drivers  
Typical values : V (sat) = 1.8 V, V = 1.5 V, ESW = 390 J at 10 A  
CE  
F
Compact 29.6 mm 18.2 mm dual in-line package  
Cross-conduction protection  
Adjustable over-current protection level  
Integrated bootstrap diodes and resistors  
Enable pin  
MODULE SPCM24 29.6x18.2 DIP S3  
MARKING DIAGRAM  
Thermistor  
Typical Applications  
Industrial Pumps  
Industrial Fans  
Industrial Automation  
Home Appliances  
STK5Q4U362J = Specific Device Code  
A = Year  
B = Month  
C = Production Site  
DD = Factory Lot Code  
Device marking is on package underside  
ORDERING INFORMATION  
Shipping  
(Qty / Packing)  
Device  
Package  
MODULE SPCM24  
29.6x18.2 DIP S3  
(Pb-Free)  
STK5Q4U362J-E  
16 / Tube  
Figure 1. Functional Diagram  
This document contains information on a new product. Specifications and information  
herein are subject to change without notice.  
© Semiconductor Components Industries, LLC, 2016  
October 2016 - Rev. P3  
1
Publication Order Number :  
STK5Q4U362J-E/D  
STK5Q4U362J-E  
STK5Q4U362J-E  
Figure 2. Application Schematic  
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2
STK5Q4U362J-E  
Figure 3. Simplified Block Diagram  
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3
STK5Q4U362J-E  
PIN FUNCTION DESCRIPTION  
Pin  
Name  
Description  
1
2
3
4
5
6
7
8
9
GND  
VDD  
HINU  
HINV  
HINW  
LINU  
LINV  
LINW  
FAULT  
ITRIP  
ENABLE  
RCIN  
TH1  
TH2  
NU  
Negative Main Supply  
+15 V Main Supply  
Logic Input High Side Gate Driver - Phase U  
Logic Input High Side Gate Driver - Phase V  
Logic Input High Side Gate Driver - Phase W  
Logic Input Low Side Gate Driver - Phase U  
Logic Input Low Side Gate Driver - Phase V  
Logic Input Low Side Gate Driver - Phase W  
Fault output  
10  
11  
12  
13  
14  
17  
18  
19  
20  
22  
26  
28  
32  
34  
38  
Current protection pin  
Enable input  
R, C connection terminal for setting FAULT clear time  
Thermistor output 1  
Thermistor output 2  
Low Side Emitter Connection - Phase U  
Low Side Emitter Connection - Phase V  
Low Side Emitter Connection - Phase W  
W phase output. Internally connected to W phase high side driver ground  
High Side Floating Supply Voltage for W phase  
V phase output. Internally connected to V phase high side driver ground  
High Side Floating Supply voltage for V phase  
U phase output. Internally connected to U phase high side driver ground  
High Side Floating Supply voltage for U phase  
Positive Bus Input Voltage  
NV  
NW  
W
VBW  
V
VBV  
U
VBU  
VP  
Note : Pins 15, 16, 21, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36, 37 are not present  
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4
STK5Q4U362J-E  
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)  
Rating  
Symbol  
Conditions  
VP to NU, NV, NW, surge < 500 V  
Value  
450  
Unit  
V
V
V
Supply voltage  
Collector-emitter voltage  
(Note 3)  
CC  
max  
VP to U, V, W ; U to NU ; V to NV ; W to NW  
VP, U, V, W, NU, NV, NW terminal current  
600  
V
CE  
±10  
A
Output current  
Io  
VP, U, V, W, NU, NV, NW terminal current,  
Tc = 100C  
VP, U, V, W, NU, NV, NW terminal current,  
pulse width 1ms  
±5  
±20  
A
A
V
Output peak current  
Iop  
V
VBU to U, VBV to V, VBW to W, V  
(Note 4)  
to GND  
DD  
,V  
Gate driver supply voltages  
0.3 to +20.0  
DD BS  
V
0.3 to V  
Input signal voltage  
HINU, HINV, HINW, LINU, LINV, LINW  
FAULT terminal  
V
V
IN  
DD  
0.3 to V  
FAULT terminal voltage  
RCIN terminal voltage  
ITRIP terminal voltage  
ENABLE terminal voltage  
Maximum power dissipation  
Junction temperature  
Storage temperature  
VFAULT  
VRCIN  
VITRIP  
VENABLE  
Pd  
DD  
0.3 to V  
RCIN terminal  
V
DD  
ITRIP terminal  
V
0.3 to +10.0  
0.3 to V  
ENABLE terminal  
V
DD  
IGBT per 1 channel  
IGBT, Gate driver IC  
31  
150  
W
Tj  
C  
Tstg  
C  
40 to +125  
20 to +100  
0.6  
Operating case temperature  
Package mounting torque  
Isolation voltage  
Tc  
IPM case temperature  
Case mounting screw  
C  
Nm  
Vrms  
Vis  
50 Hz sine wave AC 1 minute  
(Note 5)  
2000  
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device  
functionality should not be assumed, damage may occur and reliability may be affected.  
2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for  
Safe Operating parameters.  
3. This surge voltage developed by the switching operation due to the wiring inductance between VP and NU,NV,NW terminals.  
4.  
V
= VBU to U, VBV to V, VBW to W.  
BS  
5. Test conditions : AC 2500 V, 1 s  
RECOMMENDED OPERATING RANGES (Note 6)  
Rating  
Symbol  
Min  
0
Typ  
280  
15  
Max  
400  
17.5  
16.5  
5.0  
Unit  
V
V
V
V
V
Supply voltage  
VP to NU, NV, NW  
V
CC  
VBU to U, VBV to V, VBW to W  
12.5  
13.5  
3.0  
0
BS  
Gate driver supply voltage  
V
V
V
to GND (Note 4)  
DD  
15  
DD  
(ON)  
IN  
ON-state input voltage  
OFF-state input voltage  
PWM frequency  
HINU, HINV, HINW, LINU, LINV, LINW  
(OFF)  
IN  
0.3  
fPWM  
DT  
1
20  
kHz  
μs  
Dead time  
Turn-off to turn-on (external)  
ON and OFF  
1
Allowable input pulse width  
Package mounting torque  
PWIN  
1
μs  
‘M3’ type screw  
0.4  
0.6  
Nm  
6. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to  
stresses beyond the Recommended Operating Ranges limits may affect device reliability.  
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5
STK5Q4U362J-E  
ELECTRICAL CHARACTERISTICS at Tc = 25C, V  
= 15 V, V  
= 15 V (Note 7)  
DD  
BS  
Parameter  
Test Conditions  
Symbol  
Min  
Typ  
Max  
Unit  
Power output section  
V
= 600 V  
I
CE  
Collector-emitter leakage current  
-
-
100  
μA  
V
CE  
V
(sat)  
1.9  
1.6  
1.5  
1.2  
-
2.7  
Ic = 10 A, Tj = 25C  
Ic = 5 A, Tj = 100C  
IF = 10 A, Tj = 25C  
IF = 5 A, Tj = 100C  
IGBT  
CE  
Collector to emitter saturation voltage  
-
V
V
2.2  
V
F
Diode forward voltage  
Junction to case thermal resistance  
Switching time  
-
V
θj-c(T)  
θj-c(T)  
tON  
-
-
-
-
-
-
-
-
-
-
-
-
4
C/W  
C/W  
μs  
Freewheeling Diode  
-
5.5  
0.6  
1.0  
300  
90  
1.3  
Ic = 10 A, V  
Ic = 10 A, V  
= 300 V, Tj = 25C  
CC  
CC  
tOFF  
1.6  
Turn-on switching loss  
Turn-off switching loss  
Total switching loss  
EON  
-
-
-
-
-
-
-
-
μJ  
μJ  
μJ  
μJ  
μJ  
μJ  
μJ  
ns  
= 300 V, Tj = 25C  
EOFF  
ETOT  
EON  
390  
360  
110  
470  
60  
Turn-on switching loss  
Turn-off switching loss  
Total switching loss  
Ic = 10 A, V  
Ic = 10 A, V  
= 300 V, Tj = 25C  
= 300 V, Tj = 25C  
EOFF  
ETOT  
EREC  
trr  
CC  
CC  
Diode reverse recovery energy  
Diode reverse recovery time  
(di/dt set by internal driver)  
160  
Full  
Square  
Ic = 20 A, V  
= 450 V  
Reverse bias safe operating area  
RBSOA  
-
CE  
V
= 400 V  
Short circuit safe operating area  
Allowable offset voltage slew rate  
Driver Section  
SCSOA  
dv/dt  
4
-
-
-
μs  
CE  
U to NU, V to NV, W to NW  
50  
V/ns  
50  
V
V
= 15 V (Note 4), per driver  
= 15 V, total  
ID  
-
0.07  
0.95  
-
0.4  
mA  
mA  
V
BS  
DD  
Gate driver consumption current  
ID  
-
3
High level Input voltage  
Low level Input voltage  
Logic 1 input current  
Vin H  
Vin L  
IIN+  
2.5  
-
0.8  
900  
3
HINU, HINV, HINW, LINU, LINV, LINW  
to GND  
-
-
V
V
V
= +3.3 V  
= 0 V  
-
660  
-
μA  
μA  
IN  
IN  
Logic 0 input current  
IIN-  
-
-
Bootstrap ON Resistance  
FAULT terminal sink current  
FAULT clearance delay time  
IB = 1 mA  
RB  
110  
2
-
FAULT : ON / VFAULT = 0.1 V  
RCLR = 2 M, CCLR = 1 nF  
VEN ON-state voltage  
VEN OFF-state voltage  
ITRIP to GND  
IoSD  
FLTCLR  
VEN(ON)  
VEN(OFF)  
VITRIP  
tITRIP  
-
-
mA  
ms  
V
1.1  
2.5  
-
1.65  
-
2.2  
-
ENABLE ON/OFF voltage  
-
0.8  
0.54  
-
V
ITRIP threshold voltage  
0.44  
-
0.49  
1.1  
350  
V
ITRIP to shutdown propagation delay  
ITRIP blanking time  
μs  
ns  
tITRIPBL  
250  
-
V
and V  
supply undervoltage  
BS  
VDDUV+  
VBSUV+  
DD  
positive going input threshold  
and V supply undervoltage  
10.2  
10.0  
-
11.1  
10.9  
0.2  
11.8  
11.6  
-
V
V
V
V
VDDUV-  
VBSUV-  
DD  
negative going input threshold  
and V supply undervoltage Ilockout  
BS  
V
VDDUVH  
VBSUVH  
DD  
hysteresis  
BS  
7. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.  
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
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6
STK5Q4U362J-E  
TYPICAL CHARACTERISTICS  
TJ = 25C  
TJ = 100C  
TJ = 100C  
TJ = 25C  
Figure 4. V  
versus ID for different temperatures  
Figure 5. V versus ID for different temperatures  
F
CE  
(V  
DD  
= 15 V)  
TJ = 100C  
TJ = 100C  
TJ = 25C  
TJ = 25C  
Figure 7. EOFF versus ID for different temperatures  
Figure 6. EON versus ID for different temperatures  
Figure 8. Thermal impedance plot (IGBT)  
Figure 9. Thermal impedance plot (FRD)  
X:100ns/div  
X:100ns/div  
Vce: 100V/div  
Io:5A/div  
Io:5A/div  
Vce: 100V/div  
Figure 10. Turn-on waveform Tj = 100C, V  
= 400 V  
Figure 11. Turn-off waveform Tj = 100C, V  
= 400 V  
CC  
CC  
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7
STK5Q4U362J-E  
APPLICATIONS INFORMATION  
Input / Output Timing Chart  
Figure 12. Input/Output Timing Chart  
Notes  
1. This section of the timing diagram shows the effect of cross-conduction prevention.  
2. This section of the timing diagram shows that when the voltage on V decreases sufficiently all gate output signals will go low,  
DD  
rises sufficiently, normal operation will resume.  
switching off all six IGBTs. When the voltage on V  
DD  
3. This section shows that when the bootstrap voltage V  
drops, the corresponding high side output (U or V or W) is switched off.  
BS  
rises sufficiently, normal operation will resume.  
When V  
BS  
4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes  
later after the over-current condition is removed.  
5. After V  
has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input  
DD  
before enabling the driver for the HIN signal.  
Input / Output Logic Table  
INPUT  
OUTPUT  
U, V, W  
High side  
IGBT  
Low side  
IGBT  
HIN  
LIN  
Itrip  
Enable  
FAULT  
H
L
L
H
L
L
L
H
H
H
H
H
L
ON (Note 5)  
OFF  
OFF  
ON  
VP  
OFF  
OFF  
OFF  
OFF  
ON  
NU, NV, NW  
L
L
OFF  
OFF  
OFF  
OFF  
OFF  
High Impedance  
High Impedance  
High Impedance  
High Impedance  
H
X
X
H
X
X
L
OFF  
H
X
OFF  
OFF  
OFF  
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STK5Q4U362J-E  
Thermistor characteristics  
Parameter  
Symbol  
Condition  
Min  
99  
Typ  
100  
Max  
101  
Unit  
k  
kΩ  
K
R
25  
Tc = 25  
Resistance  
R
100  
5.18  
4208  
40  
5.38  
4250  
5.60  
4293  
+125  
Tc = 100℃  
B
B-Constant (25 to 50)  
Temperature Range  
Figure 13. Thermistor Resistance versus Case Temperature  
Case Temperature (Tc) TH to GND voltage characteristic  
Figure 14. Thermistor Voltage versus Case Temperature  
Conditions : RTH = 39 k, pull-up voltage 5.0 V (see Figure 2)  
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STK5Q4U362J-E  
Fault output  
Calculation of bootstrap capacitor value  
The FAULT output is an open drain output requiring a  
pull-up resistor. If the pull-up voltage is 5 V, use a  
pull-up resistor with a value of 6.8 kor higher. If the  
pull-up voltage is 15 V, use a pull-up resistor with a  
value of 20 kor higher. The FAULT output is  
The bootstrap capacitor value CB is calculated using  
the following approach. The following parameters  
influence the choice of bootstrap capacitor:  
VBS : Bootstrap power supply.  
triggered if there is a V  
undervoltage or an  
15 V is recommended.  
DD  
QG : Total gate charge of IGBT at V = 15 V.  
overcurrent condition.  
BS  
45 nC  
Undervoltage lockout protection  
UVLO : Falling threshold for UVLO.  
Specified as 12 V.  
If V  
goes below the V  
supply undervoltage  
DD  
DD  
lockout falling threshold, the FAULT output is  
switched on. The FAULT output stays on until V  
IDMAX : High side drive consumption current.  
Specified as 0.4 mA  
tONMAX : Maximum ON pulse width of high side  
IGBT.  
DD  
supply undervoltage lockout  
rises above the V  
DD  
rising threshold. After V  
has risen above the  
DD  
threshold to enable normal operation, the driver waits  
to receive an input signal on the LIN input before  
enabling the driver for the HIN signal.  
Capacitance calculation formula:  
CB = (QG + IDMAX * tONMAX)/(VBS - UVLO)  
Overcurrent protection  
CB is recommended to be approximately 3 times the  
value calculated above. The recommended value of CB  
is in the range of 1 to 47 μF, however, the value needs  
to be verified prior to production. When not using the  
bootstrap circuit, each high side driver power supply  
requires an external independent power supply.  
An over-current condition is detected if the voltage on  
the ITRIP pin is larger than the reference voltage.  
There is a blanking time of typically 350 ns to improve  
noise immunity. After a shutdown propagation delay of  
typically 1.1 s, the FAULT output is switched on. The  
FAULT output is held on for a time determined by the  
resistor and capacitor connected to the RCIN pin. If  
RCLR = 2 Mand CCLR = 1 nF, the FAULT output  
is switched on for 1.65 ms (typical).  
The internal bootstrap circuit uses a MOSFET. The  
turn on time of this MOSFET is synchronized with the  
turn on of the low side IGBT. The bootstrap capacitor  
is charged by turning on the low side IGBT.  
The over-current protection threshold should be set to  
be equal or lower to 2 times the module rated current  
(IO).  
If the low side IGBT is held on for a long period of  
time (more than one second for example), the bootstrap  
voltage on the high side MOSFET will slowly  
discharge.  
An additional fuse is recommended to protect against  
system level or abnormal over-current fault conditions.  
Capacitors on High Voltage and V  
DD  
supplies  
100  
10  
Both the high voltage and V  
supplies require an  
DD  
electrolytic capacitor and an additional high frequency  
capacitor.  
1
Enable pin  
The ENABLE terminal pin is used to enable or shut  
down the built-in driver. If the voltage on the ENABLE  
pin rises above the ENABLE ON-state voltage the  
output drivers are enabled. If the voltage on the  
ENABLE pin falls below the ENABLE OFF-state  
voltage, the drivers are disabled.  
0.1  
0.01  
0.1  
1
10  
100  
1000  
tONMAX [ms]  
Figure 15. Bootstrap capacitance versus tONMAX  
Minimum input pulse width  
When input pulse width is less than 1 μs, an output  
may not react to the pulse. (Both ON signal and OFF  
signal)  
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10  
STK5Q4U362J-E  
Mounting Instructions  
Item  
Recommended Condition  
Pitch  
26.0 ±0.1 mm (Please refer to Package Outline Diagram)  
Diameter : M3  
Screw head types: pan head, truss head, binding head  
Screw  
Plane washer dimensions (Figure 16)  
D = 7 mm, d = 3.2 mm and t = 0.5 mm JIS B 1256  
Washer  
Material : Aluminum or Copper  
Warpage (the surface that contacts IPM ) : 50 to 50 μm  
Screw holes must be countersunk.  
No contamination on the heat sink surface that contacts IPM.  
Heat sink  
Torque  
Grease  
Temporary tightening : 50 to 60% of final tightening on first screw  
Temporary tightening : 50 to 60% of final tightening on second screw  
Final tightening : 0.4 to 0.6 Nm on first screw  
Final tightening : 0.4 to 0.6 Nm on second screw  
Silicone grease.  
Thickness : 50 to 100 μm  
Uniformly apply silicone grease to whole back.  
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and  
compressibility parameters have a strong influence on performance.  
Recommended  
Not recommended  
Silicone grease  
Figure 16. Module Mounting details: components; washer drawing; need for even spreading of thermal grease  
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11  
STK5Q4U362J-E  
TEST CIRCUITS  
I  
CE  
ICE  
A
34  
32  
M
VBS=15V  
VBS=15V  
U+  
V+  
W+  
U-  
V-  
W-  
M
N
38  
32  
38  
26  
38  
20  
32  
17  
26  
18  
20  
19  
28  
26  
U+,V+,W+ : High side phase  
U-,V-,W- : Low side phase  
VCE  
22  
20  
VBS=15V  
VDD=15V  
2
1
N
Figure 17. Test Circuit for I  
CE  
34  
32  
M
VBS=15V  
VBS=15V  
VBS=15V  
V (sat) (Test by pulse)  
CE  
U+  
V+  
W+  
U-  
V-  
W-  
26  
M
N
38  
32  
3
38  
26  
4
38  
20  
5
32  
17  
6
26  
18  
7
20  
19  
8
V
Ic  
22  
20  
VCE(sat)  
m
2
VDD=15V  
5V  
N
m
1,10,N  
Figure 18. Test circuit for V (sat)  
CE  
VF (Test by pulse)  
U+  
V+  
W+  
U-  
V-  
W-  
M
N
38  
32  
38  
26  
38  
20  
32  
17  
26  
18  
20  
19  
Figure 19. Test circuit for VF  
www.onsemi.com  
12  
STK5Q4U362J-E  
M
RB (Test by pulse)  
6
U+  
V+  
W+  
5V  
7
8
M
N
2
2
2
V
IB  
34  
28  
22  
VB  
(RB)  
2
VDD=15V  
N
1,3,4,5,10  
Figure 20. Test circuit for RB  
ID  
ID  
A
M
VBS U+  
34  
VBS V+  
VBS W+  
VDD  
VD  
M
N
28  
26  
22  
20  
2
1
32  
N
Figure 21. Test circuit for ID  
Switching time (The circuit is a representative example of the low side U phase.)  
34  
32  
38  
32  
Input signal  
(0 to5V)  
VBS=15V  
28  
26  
VBS=15V  
Vcc  
90%  
22  
20  
CS  
VBS=15V  
Io  
Ic  
10%  
2
VDD=15V  
17  
6
Input signal  
tOFF  
tON  
1,10  
Figure 22. Switching time test circuit  
www.onsemi.com  
13  
STK5Q4U362J-E  
PACKAGE DIMENSIONS  
unit : mm  
www.onsemi.com  
14  
STK5Q4U362J-E  
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15  

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