STK6031 [ETC]
•80C51 Central Processing Unit (CPU).–Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1 / 3.–Industrial standard 80C51 instruction set.–Normal mode, idle mode, and stop mode.•Program Memory : 64 kbytes on-chip flash memory.–with hardware ISP (In-System Programming).–Program code protection.•Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.•Aux Memory (AUX RAM): 768 bytes of SRAM.•SFRs (Special Function Register): 46 SFRs.•Timers: Timer 0, Timer 1, and Timer 2.•On-chip Watchdog Timer.•Full-duplex UART•Five I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4 (P4.0 ~•On-chip power-on-reset with low-voltage detection and reset.•Interrupts: 6 sources, 2 priority level, 6 vectored addresses.•Software enable/disable of ALE output pulse to reduce EMI.•4-channel, 6-bit ADC.•5-channel, 8-bit PWM.•CPU operating freque;
| 型号： | STK6031 |
| 厂家： | 
ETC |
| 描述： | •80C51 Central Processing Unit (CPU).–Option for multiple CPU clock (XTAL1, XTAL1 x 2, or XTAL1 / 3.–Industrial standard 80C51 instruction set.–Normal mode, idle mode, and stop mode.•Program Memory : 64 kbytes on-chip flash memory.–with hardware ISP (In-System Programming).–Program code protection.•Main Data RAM: 256 bytes (upper 128 + lower 128 bytes) of on-chip SRAM.•Aux Memory (AUX RAM): 768 bytes of SRAM.•SFRs (Special Function Register): 46 SFRs.•Timers: Timer 0, Timer 1, and Timer 2.•On-chip Watchdog Timer.•Full-duplex UART•Five I/O ports: Port 0, Port 1, Port 2, Port 3, and Port 4 (P4.0 ~•On-chip power-on-reset with low-voltage detection and reset.•Interrupts: 6 sources, 2 priority level, 6 vectored addresses.•Software enable/disable of ALE output pulse to reduce EMI.•4-channel, 6-bit ADC.•5-channel, 8-bit PWM.•CPU operating freque 静态存储器 |
| 文件： | 总69页 (文件大小：1528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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