SZNUP3112UPMUTAG [ONSEMI]
Quad Transient Voltage Suppressor Array;
| 型号： | SZNUP3112UPMUTAG |
| 厂家： | 
ONSEMI |
| 描述： | Quad Transient Voltage Suppressor Array 二极管 |
| 文件： | 总4页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUP3112UPMU,
SZNUP3112UPMU
Quad Transient Voltage
Suppressor Array
ESD Protection Diodes with Ultra−Low
(0.7 pF) Capacitance
http://onsemi.com
The three−line voltage transient suppressor array is designed to protect
voltage−sensitive components that require ultra−low capacitance from
ESD and transient voltage events. This device features a common anode
D
D
D
V
CC
1
2
3
design which protects three independent high speed data lines and a V
power line in a single six−lead UDFN low profile package.
CC
Excellent clamping capability, low capacitance, low leakage, and fast
response time make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, it is
suited for use in high frequency designs such as a USB 2.0 high speed.
Features
MARKING
DIAGRAM
• Low Capacitance Data Lines (0.7 pF Typical)
• Protects up to Three Data Lines Plus a V Pin
1
CC
UDFN6 1.6x1.6
MU SUFFIX
CASE 517AP
6
P5 MG
• UDFN Package, 1.6 x 1.6 mm
G
1
• Low Profile of 0.50 mm for Ultra Slim Design
• ESD Rating: IEC61000−4−2: Level 4
P5
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
− Contact (14 kV)
• V Pin = 15 V Protection
CC
(Note: Microdot may be in either location)
• D , D , and D Pins = 5.2 V Minimum Protection
1
2
3
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
PIN CONNECTIONS
• This is a Pb−Free Device
6
5
4
V
D
D
D
1
2
3
CC
1
2
3
Typical Applications
• USB 2.0 High−Speed Interface
• Cell Phones
• MP3 Players
• SIM Card Protection
GND
NC
NC
MAXIMUM RATINGS (T = 25°C, unless otherwise specified)
J
ORDERING INFORMATION
Symbol
Rating
Value
−40 to 125
−55 to 150
260
Unit
°C
†
Device
Package
Shipping
T
J
Operating Junction Temperature Range
Storage Temperature Range
NUP3112UPMUTAG
UDFN6
(Pb−Free)
3000 / Tape &
Reel
T
STG
°C
T
L
Lead Solder Temperature – Maximum
(10 seconds)
°C
SZNUP3112UPMUTAG UDFN6
(Pb−Free)
3000 / Tape &
Reel
ESD
IEC 61000−4−2 Contact
14000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
April, 2014− Rev. 1
NUP3112UPMU/D
NUP3112UPMU, SZNUP3112UPMU
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
F
I
PP
V
C
PP
V
RWM
Working Peak Reverse Voltage
V
C
V
V
I
Maximum Reverse Leakage Current @ V
BR RWM
R
RWM
V
I
V
F
R
T
V
BR
Breakdown Voltage @ I
I
T
I
T
Test Current
I
F
Forward Current
V
F
Forward Voltage @ I
F
I
PP
P
Peak Power Dissipation
Max. Capacitance @ V = 0 and f = 1.0 MHz
pk
C
Uni−Directional TVS
R
ELECTRICAL CHARACTERISTICS (T = 25°C, unless otherwise specified)
J
Parameter
Reverse Working Voltage (D , D , and D )
Conditions
Symbol
Min
−
Typ
−
Max Unit
(Note 1)
(Note 1)
V
4.0
12
V
V
1
2
3
RWM1
RWM2
Reverse Working Voltage (V )
V
−
−
1
Breakdown Voltage (D , D , and D )
I = 1 mA, (Note 2)
V
BR
5.2
13.5
−
5.5
15
−
−
V
1
2
3
T
Breakdown Voltage (V
)
I = 5 mA, (Note 2)
T
V
BR2
15.8
1.0
1.0
0.9
V
CC
Reverse Leakage Current (D , D , and D )
@ V
@ V
I
R
I
R
mA
mA
pF
1
2
3
RWM
Reverse Leakage Current (V
)
−
−
CC
RWM2
Capacitance (D , D , and D )
V
R
= 0 V, f = 1 MHz (Line to GND)
C
J
−
0.7
1
2
3
1. TVS devices are normally selected according to the working peak reverse voltage (V
or continuous peak operating voltage level.
), which should be equal or greater than the DC
RWM
2. V is measured at pulse test current I .
BR
T
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
http://onsemi.com
2
NUP3112UPMU, SZNUP3112UPMU
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
http://onsemi.com
3
NUP3112UPMU, SZNUP3112UPMU
PACKAGE DIMENSIONS
UDFN6, 1.6x1.6, 0.5P
CASE 517AP
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
B
2X
L
0.10
C
L1
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
E
DETAIL A
REFERENCE
OPTIONAL
MILLIMETERS
CONSTRUCTION
DIM MIN
0.45
A1 0.00
MAX
0.55
0.05
2X
A
0.10
C
MOLD CMPD
EXPOSED Cu
A3
b
0.13 REF
TOP VIEW
0.20
0.30
D
E
e
1.60 BSC
1.60 BSC
0.50 BSC
A3
A
(A3)
DETAIL B
D2 1.10
E2 0.45
1.30
0.65
−−−
0.40
0.15
0.05
0.05
C
C
A1
K
L
0.20
0.20
DETAIL B
OPTIONAL
CONSTRUCTION
6X
L1 0.00
SIDE VIEW
SEATING
PLANE
C
A1
SOLDERMASK DEFINED
MOUNTING FOOTPRINT*
DETAIL A
6X L
D2
1.26
3
1
E2
6X
6
5
0.52
0.61 1.90
6X K
6X b
0.10 C A B
e
NOTE 3
C
0.05
1
BOTTOM VIEW
0.50 PITCH
6X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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NUP3112UPMU/D
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