UC2844DR2 [ONSEMI]
High Performance Current Mode Controllers; 高性能电流模式控制器
| 型号： | UC2844DR2 |
| 厂家： | 
ONSEMI |
| 描述： | High Performance Current Mode Controllers |
| 文件： | 总16页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC3844, UC3845, UC2844,
UC2845
High Performance
Current Mode Controllers
The UC3844, UC3845 series are high performance fixed frequency
current mode controllers. They are specifically designed for Off−Line
and DC−to−DC converter applications offering the designer a cost
effective solution with minimal external components. These integrated
circuits feature an oscillator, a temperature compensated reference, high
gain error amplifier, current sensing comparator, and a high current
totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, a latch for single pulse metering, and a flip−flop which
blanks the output off every other oscillator cycle, allowing output dead
times to be programmed for 50% to 70%.
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PDIP−8
N SUFFIX
CASE 626
8
1
SOIC−14
D SUFFIX
CASE 751A
14
1
These devices are available in an 8−pin dual−in−line plastic package
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
package has separate power and ground pins for the totem pole output
stage.
SOIC−8
D1 SUFFIX
CASE 751A
8
1
The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX845 is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
PIN CONNECTIONS
Compensation
1
2
8
7
V
ref
Voltage Feedback
V
CC
Features
3
4
6
5
Current Sense
R /C
Output
GND
• Current Mode Operation to 500 kHz Output Switching Frequency
• Output Deadtime Adjustable from 50% to 70%
• Automatic Feed Forward Compensation
T
T
(Top View)
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Input Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with ON Semiconductor SENSEFETt Products
• Pb−Free Packages are Available
1
14
13
Compensation
NC
V
ref
2
NC
V
3
4
12
11
Voltage Feedback
NC
CC
V
C
5
6
10
9
Current Sense
NC
Output
V
CC
7(12)
GND
R /C
T
7
8
Power Ground
T
V
ref
8(14)
V
CC
Undervoltage
Lockout
5.0V
Reference
(Top View)
R
R
V
ref
V
C
Undervoltage
Lockout
7(11)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
R C
T
Output
6(10)
T
Flip
Flop
&
Oscillator
4(7)
Voltage
Feedback
PWR GND
5(8)
Latching
PWM
+
−
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page page 14 of this data sheet.
2(3)
Current
Sense
3(5)
Error
Amplifier
1(1)
Output
Comp.
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 7
UC3844/D
UC3844, UC3845, UC2844, UC2845
MAXIMUM RATINGS
Rating
Symbol
Value
30
Unit
mA
A
Total Power Supply and Zener Current
Output Current, Source or Sink (Note 1)
Output Energy (Capacitive Load per Cycle)
Current Sense and Voltage Feedback Inputs
Error Amp Output Sink Current
(I + I )
CC Z
I
O
1.0
W
5.0
− 0.3 to + 5.5
10
mJ
V
V
in
I
O
mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, Case 751A
Maximum Power Dissipation @ T = 25°C
P
q
862
145
mW
A
D
JA
Thermal Resistance Junction−to−Air
R
°C/W
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ T = 25°C
P
D
1.25
100
W
°C/W
A
Thermal Resistance Junction−to−Air
R
q
JA
Operating Junction Temperature
T
+ 150
°C
°C
J
Operating Ambient Temperature
UC3844, UC3845
T
A
0 to + 70
− 25 to + 85
UC2844, UC2845
Storage Temperature Range
T
stg
− 65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum Package power dissipation limits must be observed.
ELECTRICAL CHARACTERISTICS (V = 15 V, (Note 2), R = 10 k, C = 3.3 nF, T = T to T
(Note 3), unless otherwise noted.)
CC
T
T
A
low
high
UC284X
UC384X
Characteristics
REFERENCE SECTION
Reference Output Voltage (I = 1.0 mA, T = 25°C)
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
V
ref
4.95
−
5.0
2.0
3.0
0.2
−
5.05
20
4.9
−
5.0
2.0
3.0
0.2
−
5.1
20
V
mV
mV
mV/°C
V
O
J
Line Regulation (V = 12 V to 25 V)
Reg
CC
line
load
S
Load Regulation (I = 1.0 mA to 20 mA)
Reg
−
25
−
25
O
Temperature Stability
T
−
−
−
−
Total Output Variation over Line, Load, Temperature
Output Noise Voltage (f = 10 Hz to kHz, T = 25°C)
V
ref
4.9
−
5.1
−
4.82
−
5.18
−
V
n
50
50
mV
J
Long Term Stability (T = 125°C for 1000 Hours)
S
−
5.0
− 85
−
−
5.0
− 85
−
mV
mA
A
Output Short Circuit Current
I
− 30
− 180
− 30
− 180
SC
OSCILLATOR SECTION
Frequency
f
kHz
osc
47
46
52
−
57
60
47
46
52
−
57
60
T = 25°C
J
T = T
to T
high
A
low
Frequency Change with Voltage (V = 12 V to 25 V)
Df
Df
D
D
−
−
0.2
5.0
1.0
−
−
0.2
5.0
1.0
%
%
CC
osc/
V
Frequency Change with Temperature
−
−
osc/
T
T = T
to T
A
low
high
Oscillator Voltage Swing (Peak−to−Peak)
Discharge Current (V = 2.0 V, T = 25°C)
V
−
−
1.6
−
−
−
−
1.6
−
−
V
osc
I
dischg
10.8
10.8
mA
osc
J
ERROR AMPLIFIER SECTION
Voltage Feedback Input (V = 2.5 V)
V
2.45
−
2.5
−0.1
90
2.55
−1.0
−
2.42
−
2.5
−0.1
90
2.58
−2.0
−
V
O
FB
Input Bias Current (V = 2.7 V)
I
IB
mA
dB
FB
Open Loop Voltage Gain (V = 2.0 V to 4.0 V)
A
VOL
65
65
O
2. Adjust V above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
low
= 0°C for UC3844, UC3845
−25°C for UC2844, UC2845
T
high
= +70°C for UC3844, UC3845
+85°C for UC2844, UC2845
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UC3844, UC3845, UC2844, UC2845
ELECTRICAL CHARACTERISTICS (V = 15 V, (Note 4), R = 10 k, C = 3.3 nF, T = T to T
(Note 5), unless otherwise noted.)
CC
T
T
A
low
high
UC284X
Typ
UC384X
Characteristics
ERROR AMPLIFIER SECTION (continued)
Unity Gain Bandwidth (T = 25°C)
Symbol
Min
Max
Min
Typ
Max
Unit
BW
0.7
60
1.0
70
−
−
0.7
60
1.0
70
−
−
MHz
dB
J
Power Supply Rejection Ratio (V = 12 V to 25 V)
PSRR
CC
Output Current
mA
Sink (V = 1.1 V, V = 2.7 V)
2.0
−0.5
12
−1.0
−
−
2.0
−0.5
12
−1.0
−
−
I
O
FB
Sink
Source (V = 5.0 V, V = 2.3 V)
O
FB
I
Source
Output Voltage Swing
V
High State (R = 15 k to ground, V = 2.3 V)
5.0
−
6.2
0.8
−
1.1
5.0
−
6.2
0.8
−
1.1
V
V
L
FB
OH
Low State (R = 15 k to V , V = 2.7 V)
L
ref
FB
OL
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6 & 7)
Maximum Current Sense Input Threshold (Note 6)
Power Supply Rejection Ratio
A
2.85
0.9
3.0
1.0
3.15
1.1
2.85
0.9
3.0
1.0
3.15
1.1
V/V
V
V
V
th
PSRR
dB
V
= 12 V to 25 V (Note 6)
−
−
−
70
−
−
−
−
70
−
CC
Input Bias Current
I
−2.0
150
−10
300
−2.0
150
−10
300
mA
IB
Propagation Delay (Current Sense Input to Output)
t
ns
PLH(IN/OUT)
OUTPUT SECTION
Output Voltage
V
Low State (I
= 20 mA)
= 200 mA)
= 20 mA)
= 200 mA)
−
−
12
12
0.1
1.6
13.5
13.4
0.4
2.2
−
−
−
13
12
0.1
1.6
13.5
13.4
0.4
2.2
−
V
Sink
Sink
Sink
Sink
OL
(I
High State (I
(I
V
OH
−
−
Output Voltage with UVLO Activated
= 6.0 V, I = 1.0 mA
V
OL(UVLO)
V
V
CC
−
−
−
0.1
50
50
1.1
150
150
−
−
−
0.1
50
50
1.1
150
150
Sink
Output Voltage Rise Time (C = 1.0 nF, T = 25°C)
t
r
ns
ns
L
J
Output Voltage Fall Time (C = 1.0 nF, T = 25°C)
t
f
L
J
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX844
UCX845
V
V
V
th
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
Minimum Operating Voltage After Turn−On
V
CC(min)
UCX844
UCX845
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
PWM SECTION
Duty Cycle
Maximum
Minimum
%
46
−
48
−
50
0
47
−
48
−
50
0
DC
DC
max
min
TOTAL DEVICE
Power Supply Current (Note 4)
Startup:
I
mA
V
CC
(V = 6.5 V for UCX845A,
−
−
0.5
12
1.0
17
−
−
0.5
12
1.0
17
CC
(V 14 V for UCX844) Operating
CC
Power Supply Zener Voltage (I = 25 mA)
V
30
36
−
30
36
−
CC
Z
4. Adjust V above the Startup threshold before setting to 15 V.
CC
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
= 0°C for UC3844, UC3845
−25°C for UC2844, UC2845
T
= +70°C for UC3844, UC3845
+85°C for UC2844, UC2845
low
high
6. This parameter is measured at the latch trip point with V = 0 V.
FB
DV Output Compensation
7. Comparator gain is defined as: A
V
DV Current Sense Input
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UC3844, UC3845, UC2844, UC2845
10
0
75
V
T
= 15 V
= 25°C
CC
A
1.0 nF
50
70
65
60
55
50
2.0 nF
20
5.0 nF
C
T
= 10 nF
10
5.0
2.0
100
pF
NOTE: Output switches
at one−half the oscillator
frequency.
200
pF
500
pF
1.0
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
f
, OSCILLATOR FREQUENCY (Hz)
f
osc
, OSCILLATOR FREQUENCY (Hz)
osc
Figure 2. Timing Resistor versus
Oscillator Frequency
Figure 3. Output Deadtime versus
Oscillator Frequency
V
CC
A = −1.0
T = 25°C
A
= 15 V
V
CC
A = −1.0
T = 25°C
A
= 15 V
V
V
2.55 V
3.0 V
2.5 V
2.5 V
2.0 V
2.45 V
0.5 ms/DIV
1.0 ms/DIV
Figure 4. Error Amp Small Signal
Transient Response
Figure 5. Error Amp Large Signal
Transient Response
100
80
60
40
20
1.2
0
V
= 15 V
V = 2.0 V to 4.0 V
CC
V
CC
= 15 V
O
R = 100 K
T = 25°C
A
1.0
0.8
0.6
0.4
0.2
0
30
60
90
L
Gain
T = 25°C
A
T = 125°C
A
Phase
T = −55°C
120
A
0
150
180
−ꢀ20
10
100
1.0 k
10 k
100 k
1.0 M
10 M
0
2.0
4.0
6.0
8.0
f, FREQUENCY (Hz)
V , ERROR AMP OUTPUT VOLTAGE (V)
O
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Current Sense Input Threshold
versus Error Amp Output Voltage
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UC3844, UC3845, UC2844, UC2845
0
−4.0
−8.0
−12
−16
−20
−24
110
V
= 15 V
CC
V
= 15 V
CC
R ≤ 0.1 W
L
90
70
50
T = 125°C
A
T = −55°C
A
T = 25°C
A
0
20
I
40
60
80
100
120
−55
−25
0
25
50
75
100
125
, REFERENCE SOURCE CURRENT (mA)
T , AMBIENT TEMPERATURE (°C)
A
ref
Figure 8. Reference Voltage Change
versus Source Current
Figure 9. Reference Short Circuit Current
versus Temperature
V
= 15 V
I = 1.0 mA to 20 mA
V
= 12 V to 25 V
CC
CC
T = 25°C
A
O
T = 25°C
A
2.0 ms/DIV
2.0 ms/DIV
Figure 10. Reference Load Regulation
Figure 11. Reference Line Regulation
0
−1.0
−2.0
Source Saturation
(Load to Ground)
V
= 15 V
80 ms Pulsed Load
CC
V
CC
V
= 15 V
C = 1.0 nF
CC
120 Hz Rate
T
= 25°C
A
L
90%
T = 25°C
A
T
= −55°C
A
3.0
2.0
1.0
0
T
A
= −55°C
T
A
= 25°C
10%
Sink Saturation
)
GN
D
(Load to V
CC
50 ns/DIV
0
200
400
600
800
I , OUTPUT LOAD CURRENT (mA)
O
Figure 12. Output Saturation Voltage
versus Load Current
Figure 13. Output Waveform
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UC3844, UC3845, UC2844, UC2845
25
V
= 30 V
C = 15 pF
CC
L
T = 255C
20
15
10
5
A
R = 10 k
T
C = 3.3 nF
T
V
FB
= 0 V
I
Sense
T = 255C
= 0 V
A
0
0
10
20
30
40
100 ns/DIV
V
CC
, SUPPLY VOLTAGE (V)
Figure 14. Output Cross Conduction
Figure 15. Supply Current versus
Supply Voltage
PIN FUNCTION DESCRIPTION
Pin
8−Pin
14−Pin
Function
Description
1
2
1
3
Compensation
This pin is Error Amplifier output and is made available for loop compensation.
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
3
4
5
7
Current Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
R /C
The Oscillator frequency and maximum Output duty cycle are programmed by connecting
T
T
resistor R to V and capacitor C to ground. Operation to 1.0 MHz is possible.
T
ref
T
5
6
−
GND
This pin is combined control circuitry and power ground (8−pin package only).
10
Output
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin. The output switches at one−half the oscillator frequency.
7
8
−
12
14
8
V
This pin is the positive supply of the control IC.
CC
V
This is the reference output. It provides charging current for capacitor C through resistor R .
ref
T
T
Power Ground
This pin is a separate power ground return (14−pin package only) that is connected back to
the power source. It is used to reduce the effects of switching transient noise on the control
circuitry.
−
11
V
C
The Output high state (V ) is set by the voltage applied to this pin (14−pin package only).
With a separate power source connection, it can reduce the effects of switching transient
noise on the control circuitry.
OH
−
−
9
GND
NC
This pin is the control circuitry ground return (14−pin package only) and is connected to back
to the power source ground.
2,4,6,13
No connection (14−pin package only). These pins are not internally connected.
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UC3844, UC3845, UC2844, UC2845
OPERATING DESCRIPTION
The UC3844, UC3845 series are high performance, fixed
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft−start interval
(Figures 21, 22). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
frequency, current mode controllers. They are specifically
designed for Off−Line and DC−to−DC converter
applications offering the designer a cost effective solution
with minimal external components. A representative block
diagram is shown in Figure 16.
(0.5 mA) and the required output voltage (V ) to reach the
OH
comparator’s 1.0 V clamp level:
3.0 (1.0 V) + 1.4 V
Rf(min)
≈
= 8800 W
Oscillator
0.5 mA
The oscillator frequency is programmed by the values
selected for the timing components R and C . Capacitor C
Current Sense Comparator and PWM Latch
T
T
T
is charged from the 5.0 V reference through resistor R to
approximately 2.8 V and discharged to 1.2 V by an internal
The UC3844, UC3845 operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the inductor current on a cycle−by−cycle
basis. The current Sense Comparator PWM Latch
configuration used ensures that only a single pulse appears
at the Output during any given oscillator cycle. The inductor
current is converted to a voltage by inserting the ground
T
current sink. During the discharge of C , the oscillator
T
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. An internal flip−flop has been incorporated in the
UCX844/5 which blanks the output off every other clock
cycle by holding one of the inputs of the NOR gate high. This
in combination with the C discharge period yields output
T
deadtimes programmable from 50% to 70%. Figure 2 shows
referenced sense resistor R in series with the source of
S
R
T
versus Oscillator Frequency and Figure 3, Output
output switch Q1. This voltage is monitored by the Current
Sense Input (Pin 3) and compared a level derived from the
Error Amp Output. The peak inductor current under normal
operating conditions is controlled by the voltage at pin 1
where:
Deadtime versus Frequency, both for given values of C .
T
Note that many values of R and C will give the same
T
T
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency.
In many noise sensitive applications it may be desirable to
frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 18. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 19. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved to realize output deadtimes of greater than 70%.
V(Pin 1) − 1.4 V
Ipk
=
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
1.0 V
RS
Ipk(max)
=
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 6). The
noninverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 29). The output voltage is offset by
two diode drops (≈ 1.4 V) and divided by three before it
connects to the inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
order to keep the power dissipation of R to a reasonable
S
level. A simple method to adjust this voltage is shown in
Figure 20. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.
clamp
pk(max)
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 24.
the Output (Pin 6) when Pin 1 is at its lowest state (V ).
OL
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UC3844, UC3845, UC2844, UC2845
V
in
V
CC
V
CC
7(12)
36V
V
+
−
ref
Reference
Regulator
8(14)
V
CC
UVLO
+
R
R
Internal
Bias
−
2.5V
+
V
C
−
+
R
T
7(11)
V
ref
UVLO
3.6V
−
Q1
Output
6(10)
Oscillator
4(7)
2(3)
T Q
+
C
T
1.0mA
Power Ground
5(8)
S
R
+
−
Q
−
+
Voltage Feedback
Input
PWM
Latch
2R
Error
Amplifier
R
Current Sense Input
3(5)
1.0V
Output
Compensation
1(1)
Current Sense
Comparator
R
S
GND 5(9)
+
−
Sink Only
Positive True Logic
=
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 16. Representative Block Diagram
Capacitor C
T
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
Large R /Small C
T
Small R /Large C
T T
T
Figure 17. Timing Diagram
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8
UC3844, UC3845, UC2844, UC2845
Undervoltage Lockout
designer added flexibility in tailoring the drive voltage
independent of V A zener clamp is typically connected
to this input when driving power MOSFETs in systems
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (V and the reference output (V ) are
CC.
where V is greater the 20 V. Figure 23 shows proper
CC
power and control ground connections in a current sensing
power MOSFET application.
CC
ref
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
upper and lower thresholds are 16 V/10 V for the UCX844,
comparator
CC
Reference
The 5.0 V bandgap reference is trimmed to ± 1.0%
tolerance at T = 25°C on the UC284X, and ± 2.0% on the
and 8.4 V/7.6 V for the UCX845. The V comparator upper
ref
J
and lower thresholds are 3.6 V/3/4 V. The large hysteresis
and low startup current of the UCX844 makes it ideally
suited in off−line converter applications where efficient
bootstrap startup techniques later required (Figure 30). The
UCX845 is intended for lower voltage DC−to−DC converter
applications. A 36 V zener is connected as a shunt regulator
UC384X. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Design Considerations
from V to ground. Its purpose is to protect the IC from
CC
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulsewidth jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX844 is 11 V and
8.2 V for the UCX845.
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ± 1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever and undervoltage
lockout is active. This characteristic eliminates the need for
an external pull−down resistor.
bypass capacitors (0.1 mF) connected directly to V , V ,
CC
C
and V may be required depending upon circuit layout.
ref
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise generating components.
The SOIC−14 surface mount package provides separate
pins for V (output supply) and Power Ground. Proper
C
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the I
pk(max)
clamp level. The separate V supply input allows the
C
V
ref
8(14)
R
R
8(14)
4(7)
R
R
Bias
R
A
R
T
Bias
4
8
R
B
5.0k
6
OSC
+
−
External
Sync
Input
OSC
+
4(7)
R
S
C
T
3
0.01
+
5
2
Q
+
+
−
−
+
2R
7
EA
47
−
2(3)
1(1)
2R
R
5.0k
1
EA
2(3)
1(1)
C
MC1455
R
5(9)
5(9)
To
Additional
UCX84XA’s
R
B
1.44
(R + 2R )C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
f =
D
max
=
R
A
+ 2R
B
A
B
Figure 18. External Clock Synchronization
Figure 19. External Duty Cycle Clamp and
Multi−Unit Synchronization
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9
UC3844, UC3845, UC2844, UC2845
V
CC
V
in
7(12)
+
5.0V
ref
−
+
8(14)
4(7)
R
R
−
Bias
+
−
+
5.0V
ref
7(11)
6(10)
5(8)
8(14)
R
R
−
Q1
OSC
Bias
+
−
T
+
V
+
Clamp
1.0mA
2R
S
+
−
Q
−
−
R2
R
OSC
+
EA
T
2(3)
1(1)
+
Comp/Latch
4(7)
2(3)
R
S
1.0V
1.0mA
2R
3(5)
+
Q
−
+
−
R
S
R
R1
EA
5(9)
R
1.0V
1.67
2
R
R
2
V
1
Clamp
R
S
−3
1(1)
t
V
Clamp
+ 0.33 x 10
I
≈
C
pk(max)
R
1
+ R
2
R
R
5(9)
+ 1
ꢀ 3600C in mF
Where: 0 ≤ V
≤ 1.0 V
Soft−Start
Clamp
1
Figure 20. Adjustable Reduction of Clamp Level
Figure 21. Soft−Start Circuit
V
CC
V
in
7(12)
V
CC
+
R
I r
S pk DS(on)
5.0V
ref
−
V
in
+
V
Pin
5 ≈
(12)
8(14)
R
R
r
+ R
S
DM(on)
−
Bias
+
If: SENSEFET = MTP10N10M
= 200
−
+
+
−
7(11)
6(10)
5(8)
R
S
5.0V
ref
+
−
Q1
Then: V 5 = 0.075 I
pin
pk
OSC
−
T
+
D
SENSEFET
+
4(7)
V
Clamp
−
+
S
(11)
(10)
(8)
1.0mA
2R
+
S
Q
−
−
−
R
+
EA
2(3)
1(1)
Comp/Latch
G
T
R
K
M
R2
1.0V
3(5)
S
Q
R
S
−
R
+
5(9)
Power Ground
To Input Source
Return
MPSA63
Comp/Latch
C
1.67
2
R1
R
R
2
(5)
1
V
Clamp
−3
R
+ 0.33 x 10
S
R
1
+ R
2
R
R
1/4 W
+ 1
Control CIrcuitry
Ground:
To Pin (9)
1
V
Clamp
R
I
≈
Where: 0 ≤ V
≤ 1.0 V
pk(max)
Clamp
S
Virtually lossless current sensing can be achieved with the implement of a SENSEFET
power switch. For proper operation during over current conditions, a reduction of the
V
R R
1 2
C
t
= − In
1 −
C
Softstart
3V
Clamp
R + R
1 2
I
clamp level must be implemented. Refer to Figures 20 and 22.
pk(max)
Figure 22. Adjustable Buffered Reduction of
Figure 23. Current Sensing Power MOSFET
Clamp Level with Soft−Start
V
CC
V
in
7(12)
+
5.0V
ref
−
+
−
+
−
+
7(11)
−
Q1
T
6(10)
5(8)
S
Q
−
R
+
R
Comp/Latch
3(5)
The addition of the RC filter will eliminate
instability caused by the leading edge spike on
the current waveform.
C
R
S
Figure 24. Current Waveform Spike Suppression
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10
UC3844, UC3845, UC2844, UC2845
V
CC
I
B
V
in
V
in
7(12)
+
0
−
+
5.0V
Base
Charge
Removal
ref
−
+
−
+
C
1
−
+
7(11)
6(10)
5(8)
R
g
−
Q1
Q1
T
6(1)
5(8)
S
Q
−
R
+
Comp/Latch
3(5)
3(5)
R
S
R
S
The totem−pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C .
1
Series gate resistor R will damp any high frequency parasitic oscillations
g
caused by the MOSFET input capacitance and any series wiring inductance
in the gate−source circuit.
Figure 25. MOSFET Parasitic Oscillations
Figure 26. Bipolar Transistor Drive
8(14)
4(7)
R
R
Bias
V
CC
V
in
OSC
7(12)
+
1.0mA
2R
+
+
Isolation
Boundary
−
5.0V
ref
−
+
EA
2(3)
1(1)
R
−
+
V
Waveforms
GS
−
Q1
+
7(11)
6(10)
5(8)
+
0
−
+
0
−
−
2N
3905
MCR
101
5(9)
T
50% DC
V
25% DC
2N
3903
S
− 1.4
N
N
(pin 1)
P
Q
−
I
=
pk
R
+
S
3 R
S
R
Comp/Latch
3(5)
C
N
S
R
S
N
p
The MCR101 SCR must be selected for a holding of less than 0.5 mA at T
.
A(min)
The simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
Figure 27. Isolated MOSFET Drive
Figure 28. Latched Shutdown
From V
O
From V
2.5V
O
+
2.5V
+
R
1.0mA
2R
i
2(3)
1.0mA
2R
+
R
p
2(3)
R
−
i
+
−
EA
R
d
C
I
R
f
EA
R
C
I
R
R
f
d
R
C
p
1(1)
1(1)
5(9)
R ≥ 8.8 k
f
5(9)
Error Amp compensation circuit for stabilizing any current−mode topology except
for boost and flyback converters operating with continuous inductor current.
Error Amp compensation circuit for stabilizing current−mode boost and flyback
topologies operating with continuous inductor current.
Figure 29. Error Amplifier Compensation
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11
UC3844, UC3845, UC2844, UC2845
L1
MBR1635
2200
+
4.7W
3300pF
MDA
202
4.7k
250
5.0V/4.0A
T1
+
+
+
+
1000
56k
115VA
C
5.0V RTN
12V/0.3A
MUR110
1000
1N4935
68
1N4935
L2
10
7(12)
+
+
±12V RTN
47
100
1000
10
L3
8(14)
+
−
+
+
5.0V
ref
−12V/0.3A
+
0.01
MUR110
680pF
1N4937
Bias
+
+
−
33k
7(11)
1N4937
2.7k
4(7)
2(3)
22W
OSC
T
S
6(10)
+
MTP
4N50
1.0nF
1N5819
18k
+
−
Q
−
+
5(8)
3(5)
R
EA
Comp/Latch
4.7k
1.0k
470pF
1(1)
0.5W
5(9)
T1 − Primary: 45 Turns # 26 AWG
T1 − Secondary ± 12 V: 9 Turns # 30 AWG
ꢁT1 − (2 strands) Bifiliar Wound
Figure 30. 27 Watt Off−Line Flyback Regulator
T1 − Secondary 5.0 V: 4 Turns (six strands)
ꢁT1 − #26 Hexfiliar Wound
T1 − Secondary Feedback: 10 Turns #30 AWG
ꢁT1 − (2 strands) Bifiliar Wound
T1 − Core: Ferroxcube EC35−3C8
Test
Conditions
Results
T1 − Bobbin: Ferroxcube EC35PCB1
T1 − Gap ≈ 0.01" for a primary inductance of 1.0 mH
Line Regulation:
5.0 V
± 12 V
V
in
= 95 VAC to 130 VAC
D = 50 mV or ± 0.5%
D = 24 mV or ± 0.1%
L1 − 15 mH at 5.0 A, Coilcraft Z7156.
L2, L3 − 25 mH at 1.0 A, Coilcraft Z7157.
Load Regulation: 5.0 V
V
V
= 115 VAC, I = 1.0 A to 4.0 A
D = 300 mV or ± 3.0%
D = 60 mV or ± 0.25%
in
out
± 12 V
= 115 VAC, I = 100 mA to 300
in
mA
out
Output Ripple:
Efficiency
5.0 V
± 12 V
V
= 115 VAC
40 mV
80 mV
in
pp
pp
V
in
= 115 VAC
70%
All outputs are at nominal load currents, unless otherwise noted.
http://onsemi.com
12
UC3844, UC3845, UC2844, UC2845
V = 15V
in
+
UC3845
Output Load Regulation
(open loop configuration)
7(12)
47
I
O
(mA)
V (V)
O
34V
8(14)
+
Reference
Regulator
ꢂ0
ꢂ2
ꢂ9
18
36
29.9
28.8
28.3
27.4
24.4
−
V
CC
UVLO
+
1N5819
R
R
Internal
Bias
−
2.5V
+
7(11)
6(10)
5(8)
−
+
10k
V
ref
UVLO
3.6V
−
15 10
1N5819
4(7)
Oscillator
V
O
ꢀ 2 (V )
in
+
+
T
47
+
1.0nF
Connect to
Pin 2 for
closed loop
operation.
0.5mA
S
R2
2R
+
−
Q
2(3)
1(1)
−
+
R
PWM
Latch
Error
Amplifier
R
1.0V
3(5)
R2
R2
V
R1
O = 2.5
+ 1
Current Sense
Comparator
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series
resistor may be required when using tantalum or other low ESR capacitors. The converter’s output can provide
excellent line and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 31. Step−Up Charge Pump Converter
V = 15V
in
+
UC3845
7(12)
47
34V
8(14)
+
Reference
Regulator
−
V
CC
UVLO
+
R
R
Internal
Bias
−
2.5V
+
7(11)
−
+
10k
V
ref
UVLO
3.6V
−
15 10
1N5819
+
4(7)
6(10)
+
Oscillator
V
ꢀ − (V )
O
in
T
1N5819
47
+
1.0nF
0.5mA
5(8)
S
2R
+
−
Q
2(3)
1(1)
−
+
R
PWM
Latch
Output Load Regulation
Error
Amplifier
R
1.0V
3(5)
I
O
(mA)
V (V)
O
ꢂ0
ꢂ2
ꢂ9
18
32
−14.4
−13.2
−12.5
−11.7
−10.6
Current Sense
Comparator
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.
Figure 32. Voltage−Inverting Charge Pump Converter
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13
UC3844, UC3845, UC2844, UC2845
ORDERING INFORMATION
†
Device
UC3844D
Operating Temperature Range
Package
Shipping
SOIC−14
55 Units/Rail
55 Units/Rail
UC3844DG
SOIC−14
(Pb−Free)
UC3844DR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
UC3844DR2G
SOIC−14
(Pb−Free)
UC3844N
PDIP−8
50 Units/Rail
50 Units/Rail
UC3844NG
PDIP−8
(Pb−Free)
T = 0° to +70°C
A
UC3845D
SOIC−14
55 Units/Rail
55 Units/Rail
UC3845DG
SOIC−14
(Pb−Free)
UC3845DR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
UC3845DR2G
SOIC−14
(Pb−Free)
UC3845N
PDIP−8
50 Units/Rail
50 Units/Rail
UC3845NG
PDIP−8
(Pb−Free)
UC2844D
SOIC−14
55 Units/Rail
55 Units/Rail
UC2844DG
SOIC−14
(Pb−Free)
UC2844DR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
UC2844DR2G
SOIC−14
(Pb−Free)
UC2844N
PDIP−8
50 Units/Rail
50 Units/Rail
UC2844NG
PDIP−8
(Pb−Free)
T = −25° to +85°C
A
UC2845D
SOIC−14
55 Units/Rail
55 Units/Rail
UC2845DG
SOIC−14
(Pb−Free)
UC2845DR2
SOIC−14
2500 Tape & Reel
2500 Tape & Reel
UC2845DR2G
SOIC−14
(Pb−Free)
UC2845N
PDIP−8
50 Units/Rail
50 Units/Rail
UC2845NG
PDIP−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
SOIC−14
D SUFFIX
CASE 751A
SOIC−8
D1 SUFFIX
CASE 751
8
14
8
UC384xN
AWL
YYWWG
384x
ALYW
G
UC384xDG
AWLYWW
1
1
1
8
14
x
= 4 or 5
UC284xN
AWL
YYWWG
A
= Assembly Location
UC284xDG
AWLYWW
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
1
1
http://onsemi.com
14
UC3844, UC3845, UC2844, UC2845
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
1
4
MILLIMETERS
INCHES
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MIN
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
K
L
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
_
1.01
−−−
0.030
10
0.040
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
B
0.13 (0.005)
T A
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
14
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
6.20 0.228 0.244
0.50 0.010 0.019
0.25
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15
UC3844, UC3845, UC2844, UC2845
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
0.10 (0.004)
1.27 BSC
0.050 BSC
M
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
J
H
D
8
0
_
_
_
_
M
S
S
X
0.25 (0.010)
Z
Y
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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UC3844/D
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