MN101D06F [PANASONIC]

RESET; RESET


型号：	MN101D06F
厂家：	PANASONIC
描述：	RESET RESET
文件：	总5页 (文件大小：118K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ROM (×8-bit)

MN101D06F , MN101D06G , MN101D06H

MN101D06F

MN101D06G

MN101D06H

160 K

Type

96 K

128 K

3 K

4 K

5 K

RAM (×8-bit)

*Lead-free

QFP100-P-1818B

Package

Minimum Instruction

Execution Time

With main clock operated

When sub-clock operated

0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)

71.5 µs (at 3.0 V to 5.5 V fixed to 14.32 MHz internal frequency division)

61 µs (at 2.2 V to 5.5 V, 32.768 kHz)

• RESET • Runaway • External 0 • External 1 • External 2 • External 3 • External 4 • key input (P50 to 54)

• Timer 0 • Timer 1 • Timer 2 • Timer 3 • Timer 4 • Timer 6 • Capstan FG • Control • HSW

• Cylinder(Drum) FG • Servo V-sync • Synchronous output • OSD • XDS • Serial 0 • Serial 1 • Serial 2

• A/D (common with PWM 4 reference frequency) • OSD V-sync

Interrupts

Timer counter 0: 16-bit × 1

Timer Counter

(timer function, clock function [max. 2 s or max. 36 h at cascade-connecting with timer 6])

Clock source ····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; overflow of timer counter 6;

1/512 of XI oscillation clock or OSC oscillation clock frequency

Interrupt source ················ overflow of timer counter 0

Timer counter 1: 16-bit × 1 (timer function, linear timer counter function)

Clock source ····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; CTL signal

Interrupt source ················ overflow of timer counter 1

Timer counter 2: 16-bit × 1 (timer function, input capture, duty judgment of CTL signal(VISS/VASS detection function))

Clock source ····················· 1/2, (1/4,) 1/8, (1/16,) 1/12, (1/24) of system clock frequency

Interrupt source ················ overflow of timer counter 2; input of CTL specified edge; underflow of timer 2

shift register 4-bit counter; coincidence of timer 2 shift register with timer 2

shift register compare register

Timer counter 3: 16-bit × 1

(timer function, detection of serial indexing, generation of remote control output carrier frequency)

Clock source ····················· 1/2, (1/4,) 1/8, (1/16) of system clock frequency; XI oscillation clock

Interrupt source ················ overflow of timer counter 3

Timer counter 4: 16-bit × 1 (timer function, event count [P15 input], generation of serial transmission clock)

Clock source ····················· 1/8, (1/16) of system clock frequency; external clock input

Interrupt source ················ overflow of timer counter 4; coincidence of timer counter 4 with OCR4

Timer counter 5: 19-bit × 1 (watchdog, stable oscillation waiting function)

Clock source ····················· system clock

Watchdog interrupt source ·· 1/2¹⁶, 1/2¹⁹of timer counter 5 frequency

Clear by stable oscillation ·· after 256 counts by timer counter 5 (2¹⁸counts of OSC oscillation clock)

Timer counter 6: 16-bit × 1 (clock function [max. 2 s])

Clock source ····················· 1/512 of OSC oscillation clock frequency; XI oscillation clock;

1/4, (1/8,) 1/64, (1/128) of system clock frequency

Interrupt source ················ 1/2¹³, 1/2¹⁴, 1/2¹⁵overflow of timer counter 6

Timer counter 7: 8-bit × 1 or 4-bit × 2 (timer function, event count)

Clock source ····················· 1/4, (1/8,) 1/16, (1/32) of system clock frequency; external clock input

Interrupt source ················ overflow of timer counter 7 (although when 4-bit × 2, there is one interrupt vector. )

Serial 0: 8-bit × 1 (synchronous type/start-stop synchronous type) (transfer direction of MSB/LSB selectable)

Synchronous type clock source 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency;

2-division timer 4 output; NSBT0 pin input

Serial Interface

Clock for UART ·············· 8-division of above clock; 2-division timer 4 output; NSBT0 pin input

MAD00029FEM

MN101D06F,MN101D06G,MN101D06H

Serial 1: 8-bit × 1

Serial Interface (Continue)

(synchronous type/remote control transmission/simple remote control receive) (transfer direction of MSB/LSB

selectable, start condition function)

Clock source ····················· 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency;

2-division timer 4 output; NSBT1 pin input

Remote control clock ······ 2-division timer 4 output

Serial 2: 8-bit × 1 (I²C) (master transmission/reception, slave transmission/reception)

Clock source ····················· 1/144 to 1/252 of system clock; SCK pin input

OSD mode:

Accommodation with menu(internal synchronous) or super impose(external synchronous) display

OSD

Applicable broadcasting system:NTSC, PAL, PAL-M, PAL-N

Screen configuration

Character type

Character size

Enlarged characters

Character interpolation

Line background color

Line background intensity

Screen background color

Character color

: 24 characters × 2n rows (n = 1 to 6)

: max. 512 character types (variable, incude special characters)

: 12 × 18 dots (Vertical direction: 1 dot for 2H at not enlargement)

: each × 2, × 3 or × 4 settings in horizontal and vertical

: none

: 8-hue settable (settable in the row unit at menu display)

: 8 gradations settable in the row unit (at output of composite video signal)

: 8-hue settable (at output of composite video signal)

: white (at output of composite video signal)

Character intensity

Frame function

: 8 gradations settable in the row unit (at output of composite video signal)

: 1-dot frame in 4 or 8 directions

Frame intensity

Box shade function

: 4 gradations settable in the row unit (at output of composite video signal)

: settable in the character unit (at output of composite video signal

with 129 or more characters (character types))

Blinking

: none (covered by software)

Inverted character

Halftone

: settable in the character unit

: settable in the row unit in 2 intensity gradations (at output of

external synchronous composite video signal)

CCD mode:

Supports Closed Caption in the U.S.A.

Screen configuration

Character type

: 32 characters × 16 rows

: max. 128 character types (variable)

Character size

: 12 × 26 dots (Vertical direction: 1 dot for 1H, including 8 dots in the

underlined area)

Enlarged characters

: none

Character interpolation

Line background color

Line background intensity

: none

: 8-hue settable

: 8 gradations settable in the screen unit (at output of composite video

signal)

Screen background color

Character color

: 8-hue settable (at output of composite video signal)

: 8 colors (at RGB output)

: White (at output of composite video signal)

: 8 gradations settable in the screen unit (at output of composite video signal)

: none

: settable in the row unit in 2 intensity gradations

(at output of external synchronous composite video signal)

: Underline, italic, blinking function and scroll

: composite video signal input (output level: 1 V[p-p] / 2 V[p-p])

: sync tip clamp, clamp level in 4 levels

: composite video output

Character intensity

Frame function

Box shade function

Inverted character

Halftone

Others

Input

Clamp method

Output

: digital output (6 pins)

Measure against image fluctuation

Dot clock

: built-in AFC circuit

: 1/2 of OSC oscillation clock (automatic phase adjustment)

See the next page for electrical characteristics, pin assignment and support tool.

MAD00029FEM

Built-in U.S. closed caption data slicer (optional 2 line data can be extracted.)

XDS

Correcting address designation: up to 3 addresses possible

ROM Correction

Correction method: correction program being saved in internal RAM

• Common use: 66

• Common use: 2

I/O Pins

I/O

Input

8-bit × 13-ch. (without S/H)

A/D Inputs

PWM

13-bit × 2-ch. (at repetition cycle 572 µs at 14.32 MHz),

10-bit × 2-ch. (at repetition cycle 71.5 µs at 14.32 MHz),

8-bit × 1-ch. (at repetition cycle 71.5 µs, 0.572 ms, 1.14 ms, 2.29 ms at 14.32 MHz)

18-bit × 6-ch.

ICR

16-bit × 2 (8-bit synchronous output; 4-bit 3-state synchronous output),

16-bit × 1 (weak electric field V-sync backup), 16-bit × 1 (Rec CTL)

OCR

Buzzer output; 3-state output VLP pin; remote control receive;

Special Ports

CTL signal input terminal; Capstan FG inputterminal; Sylinder(Durm) PG/FG input terminals;

HSW output terminal; Head Amp/Rortary control output terminals;

output of 1/2 OSC oscillation clock (2 V[p-p]); output of 1/4 OSC oscillation clock (1 V[p-p])

Electrical Characteristics

Supply current

Limit

Parameter

Symbol

Condition

Unit

min

typ

max

100

IDD1

IDD2

14.32 MHz operation without load, VDD = 5 V

1/1024 of 14.32 MHz operation without load, VDD = 3.0 V

Stop of 14.32 MHz oscillation, VDD = 2.7 V

32 kHz oscillation operation without load

Operating supply current

µA

IDD3

100

Supply current at STOP

Supply current at HALT

IDSP

Stop of oscillation without load, VDD = 5 V, Ta = 55 °C

14.32 MHz oscillation without load, VDD = 5 V

Stop of 14.32 MHz oscillation, VDD = 2.7 V

32 kHz oscillation operation without load

µA

IDHT0

IDHT1

µ A

(Ta = 25 °C ± 2 °C , VSS = 0 V)

A/D Converter Performance

Parameter

Limit

Unit

Symbol

Condition

min

typ

max

Conversion relative error

A/D Conversion Time

Analog Input Voltage

∆NLAD

± 3

LSB

µ s

tAD

fosc = 14.32 MHz

(Ta = 25 °C ± 2 °C , VDD = 5.0 V , VSS = 0 V)

MAD00029FEM

MN101D06F , MN101D06G , MN101D06H

Pin Assignment

CVIN2(PB4↔)

CVIN(PB5↔)

100

TPZ(→P90/AD12)

AD11(↔PC3)

AD10(↔PC2)

AD9(↔PC1)

AD8(↔PC0)

AD7(↔P87)

AD6(↔P86)

AD5(↔P85)

AD4(↔P84)

AD3(↔P83)

AD2(↔P82)

AD1(↔P81)

AD0(↔P80)

P77

SS2

CVOUT(PB6↔)

HSYNC(PB7↔)

VSYN(P20↔)

OSCO2(P21↔)

OSCI2(P22↔)

SXI

XO(P23↔)

XI(P24↔)

MN101D06F

MN101D06G

MN101D06H

OSCI

OSCO

SBUFD0(P25/PWM4↔)

PWM0

PWM1

SBUFD1(P11/PWM2↔)

SBUFD2(P12/PWM3↔)

SBUFD3(P13/FF15↔)

SBUFD4(P14/TC3O↔)

SBUFD5(P15/TC4I↔)

SBUFD6(OSDH/P16/XDSCK↔)

SBUFD7(OSDV/P17/OSCDIV/XDSDAT↔)

P76

P75

P74

P73

P72

P71

P70

ROTA(↔P67)

HAMP(↔P66)

DENV(↔P65)

QFP100-P-1818B ^{* Lead-free}

Support Tool

PX-ICE101C / D + PX-PRB101D06-QFP100-P-1818B-M

In-circuit Emulator

Flash Memory Built-in Type

Type

MN101DF06ZAF

ROM (× 8-bit)

224 K

6 K

RAM (× 8-bit)

Minimum instruction execution time

0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)

71.5 µs (at 3.0 V to 5.5 V, fixed to 14.32 MHz internal division)

61 µs (at 2.5 V to 5.5 V, 32.768 kHz)

Package

QFP100-P-1818B ^*Lead-free

MAD00029FEM

Request for your special attention and precautions in using the technical information

and semiconductors described in this material

(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of

the products or technical information described in this material and controlled under the "Foreign Exchange

and Foreign Trade Law" is to be exported or taken out of Japan.

(2) The technical information described in this material is limited to showing representative characteristics and

applied circuits examples of the products. It neither warrants non-infringement of intellectual property right

or any other rights owned by our company or a third party, nor grants any license.

(3) We are not liable for the infringement of rights owned by a third party arising out of the use of the technical

information as described in this material.

(4) The products described in this material are intended to be used for standard applications or general electronic

equipment (such as office equipment, communications equipment, measuring instruments and household

appliances).

Consult our sales staff in advance for information on the following applications:

• Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion

equipment, life support systems and safety devices) in which exceptional quality and reliability are re-

quired, or if the failure or malfunction of the products may directly jeopardize life or harm the human body.

• Any applications other than the standard applications intended.

(5) The products and product specifications described in this material are subject to change without notice for

modification and/or improvement. At the final stage of your design, purchasing, or use of the products,

therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications

satisfy your requirements.

(6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating,

the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be

liable for any defect which may arise later in your equipment.

Even when the products are used within the guaranteed values, take into the consideration of incidence of

break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as

redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physi-

cal injury, fire, social damages, for example, by using the products.

(7) When using products for which damp-proof packing is required, observe the conditions (including shelf life

and amount of time let standing of unsealed items) agreed upon when specification sheets are individually

exchanged.

(8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written

permission of Matsushita Electric Industrial Co., Ltd.

2003 SEP

MN101D06F [PANASONIC]

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