MN101DF08GAL [PANASONIC]
Microcontroller, 8-Bit, FLASH, 14.32MHz, CMOS, PQFP80, 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80;
| 型号： | MN101DF08GAL |
| 厂家： | 
PANASONIC |
| 描述： | Microcontroller, 8-Bit, FLASH, 14.32MHz, CMOS, PQFP80, 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80 时钟 微控制器 外围集成电路 |
| 文件： | 总4页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ROM (
×8-bit)
MN101D08E
MN101D08E
80 K
Type
RAM (×8-bit)
2 K
LQFP080-P-1414A *Lead-free
Package
Minimum Instruction
Execution Time
With main clock operated
When sub-clock operated
0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)
71.5 µs (at 2.7 V to 5.5 V fixed to 14.32 MHz internal frequency division)
61 µs (at 2.5 V to 5.5 V, 32.768 kHz)
• RESET • Runaway • External 0, 1, 2, 3, 4 • Timer 0 • Timer 1 • Timer 2 • Timer 3 • Timer 6
• Capstan FG • Control • HSW • Cylinder(Drum) FG • Servo V-sync • Synchronous output • OSD
• XDS • Serial 1 • Serial 2 • PWM 4 • OSD V-sync
Interrupts
Timer counter 0: 8-bit × 1 (timer function)
Timer Counter
Clock source ····················· 1/4, 1/16 of system clock frequency
Interrupt source ················ overflow of timer counter 0
Timer counter 1: 8-bit × 1 (timer function, linear timer counter function)
Clock source ····················· 1/4 of system clock frequency; CTL signal
Interrupt source ················ overflow of timer counter 1
Timer counter 2: 16-bit × 1 (timer function, input capture (CTL specified edge), duty judgment of CTL signal)
Clock source ····················· 1/4, 1/16, 1/24 of system clock frequency
Interrupt source ················ overflow of timer counter 2; input of CTL specified edge; underflow of timer 2
shift register 4-bit counter; coincidence of timer 2 shift register with timer 2 shift
register compare register
Timer counter 3: 16-bit ´ 1 (timer function)
Clock source ····················· 1/4, 1/16 of system clock frequency
Interrupt source ················ overflow of timer counter 3
Timer counter 5: 19-bit × 1 (watchdog, stable oscillation waiting function)
Clock source ····················· system clock
Watchdog interrupt source ·· 1/216, 1/219 of timer counter 5 frequency
Clear by stable oscillation ·· after 256 counts by timer counter 5 (218 counts of OSC oscillation clock)
Timer counter 6: 16-bit × 1 (clock function [max. 2 s])
Clock source ····················· 1/512 of OSC oscillation clock frequency; XI oscillation clock;
1/8, 1/128 of system clock frequency
Interrupt source ················ 1/213, 1/214, 1/215 overflow of timer counter 6
Serial 1: 8-bit × 1 (synchronous type)
Serial Interface
(transfer direction of MSB/LSB selectable, start condition function)
Clock source ····················· 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency; NSBT1 pin input
Serial 2: 8-bit × 1 (I2C) (master transmission/reception, slave transmission/reception)
Clock source ····················· 1/144 to 1/252 of system clock; SCK pin input
MAD00032DEM
98
MN101D08E
Display mode
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Menu(Internal synchronized ) display, super impose(external synchronized) display
NTSC, PAL, PAL-M, PAL-N
OSD
Applicable broadcasting system
Screen configuration
Character type
24 characters ´ 2n rows (n = 1 to 6)
max. 128 character types (variable, include special characters)
12 ´ 18 dots (Vertical direction: 1 dot for 2H at not enlargement.)
each ´ 2 settings in horizontal and vertical
none
Character size
Enlarged characters
Character interpolation
Line background color
Line background intensity
Screen background color
Character color
8-hue settable (settable in the row unit at menu display)
8 gradations settable in the row unit
8-hue settable at menu display
white
Character intensity
Frame function
8 gradations settable in the row unit
1-dot frame in 4 directions
Frame intensity
Blinking
4 gradations settable in the row unit
none (covered by software)
Inverted character
Halftone
settable in the character unit
none
Input
composite video signal input (output level: 1 V[p-p] / 2 V[p-p])
sync tip clamp, clamp level in 4 levels
composite video output
Clamp method
Output
Measure against image fluctuation:
Dot clock
built-in AFC circuit
:
1/2 of OSC oscillation clock (automatic phase adjustment)
Built-in U.S. closed caption data slicer (optional 1 line data can be extracted.)
XDS
Correcting address designation: up to 3 addresses possible
ROM Correction
Correction method: correction program being saved in internal RAM
56
1
• Common use: 45
• Common use:
I/O Pins
I/O
1
Input
8-bit × 11-ch. (without S/H)
A/D Inputs
PWM
13-bit × 2-ch. (at repetition cycle 572 µs at 14.32 MHz),
8-bit × 1-ch. (at repetition cycle 71.5 µs, 0.572 ms, 1.14 ms, 2.29 ms at 14.32 MHz)
16-bit × 2-ch.(Speed system),
18-bit × 4-ch.(Phase system)
ICR
16-bit × 3 (Synchronous output × 2, Rec CTL × 1 )
OCR
3-state output (PTO) VLP pin; CTL input; Capstan FG input; Cylinder(Drum) PG/FG inputs; HSW output;
Head amp/ Rotary control outputs; output of 1/4 OSC oscillation clock (1 V[p-p])
Special Ports
Notes
See the next page for electrical characteristics, pin assignment and support tool.
MAD00032DEM
99
Electrical Characteristics
Supply current
Limit
typ
50
Parameter
Symbol
Condition
Unit
min
max
100
5
IDD1
IDD2
14.32 MHz operation without load, VDD = 5 V
1/1024 of 14.32 MHz operation without load, VDD = 2.7 V
Stop of 14.32 MHz oscillation, VDD = 2.7 V
32 kHz oscillation operation without load
mA
mA
2
Operating supply current
µA
IDD3
50
100
Supply current at STOP
Supply current at HALT
IDSP
Stop of oscillation without load, VDD = 5 V
14.32 MHz oscillation without load, VDD = 5 V
Stop of 14.32 MHz oscillation, VDD = 2.7 V
32 kHz oscillation operation without load
10
15
µA
IDHT0
5
5
mA
IDHT1
20
µ A
(Ta = 25°C ± 2°C , VSS = 0 V)
A/D Converter Performance
Parameter
Limit
Unit
Symbol
Condition
min
typ
max
Conversion relative error
A/D Conversion Time
Analog Input Voltage
∆NLAD
± 3
LSB
µ s
tAD
fosc = 14.32 MHz
8
5
V
(Ta = 25°C ± 2°C , VDD = 5.0 V, VSS = 0 V)
MAD00032DEM
100
MN101D08E
Pin Assignment
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
(
↔
PC0
)
)
)
)
)
)
)
)
)
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
P77
P76
P75
P74
P73
P72
P71
P70
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CVIN (PB5↔)
(
↔
↔
↔
↔
↔
↔
↔
↔
P87
P86
P85
P84
P83
P82
P81
P80
VSS2
(
(
(
(
(
(
(
CVOUT (PB6↔)
SXI
X0 (P23↔)
XI (P24↔)
VSS
OSCI
OSC0
VDD
MN101D08E
PWM4(P25↔)
PWM0
PWM1
SBUFD1(P11↔)
SBUFD2(P12↔)
SBUFD3(P13↔)
SBUFD4(TC60/P14↔)
SBUFD5(P15↔)
SBUFD6(P16↔)
SBUFD7(OSCDIV/P17↔)
(
↔
P67)ROTA
(
↔
P66)HAMP
(
↔P65)DENV
*Lead-free
LQFP080-P-1414A
Support Tool
PX-ICE101C / D + PX-PRB101D08-LQFP080-P-1414A
In-circuit Emulator
Flash Memory Built-in Type
Type
MN101DF08G AL
ROM (× 8-bit)
128 K
4 K
RAM (× 8-bit)
Minimum instruction execution time
0.1397 µs (at 4.0 V to 5.5 V, 14.32 MHz)
71.5 µs (at 2.7 V to 5.5 V, fixed to 14.32 MHz internal division)
61 µs (at 2.5 V to 5.5 V, 32.768 kHz)
Package
LQFP080-P-1414A *Lead-free
MAD00032DEM
101
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