PI6C2502A [PERICOM]
Phase-Locked Loop Clock Driver; 锁相环时钟驱动器
| 型号： | PI6C2502A |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Phase-Locked Loop Clock Driver |
| 文件： | 总4页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2502A
Phase-Locked Loop Clock Driver
ProductDescription
ProductFeatures
ThePI6C2502Afeaturesalow-skew,low-jitter,phase-lockedloop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
• High-PerformancePhase-Locked-LoopClockDistribution
forNetworking,
• Synchronous DRAM modules for server/workstation/
PC applications
Application
• Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
• Zero Input-to-Output delay
• Lowjitter:Cycle-to-Cyclejitter±75psmax.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operatesat3.3VVCC
• Wide range of Clock Frequencies 80 to 134 MHz
• Package:Plastic8-pinSOICPackage(W)
LogicBlockDiagram
ProductPinConfiguration
CLK_IN
FB_IN
CLK_OUT
FB_OUT
8-Pin
W
PLL
AV
CC
Figure1.ThisCombinationProvidesZero-DelayBetweenthe
Reference Clocks Signal and 17 Outputs.
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PI6C2502A
Phase-LockedLoopClockDriver
PinFunctions
Pin Name
Pin Number
Type
Description
CLK_IN
FB_IN
8
5
I
I
Reference Clock input. CLK_IN allows spread spectrum clock input.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
Feedback output FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series-damping resistor of the same value
as the clock outputs CLK_OUT.
FB_OUT
CLK_OUT
AVCC
2
3
7
O
O
Clock outputs. These outputs provide low-skew copies of CLK_IN.
Each output has an embedded series-damping resistor.
Analog power supply. AVCC can be also used to bypass the PLL for
test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK_IN is buffered directly to the device outputs.
Power
AGND
VCC
1
4
6
Ground
Power
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply.
Ground.
GND
DC Specifications (Absolute maximum ratings over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
+0.5
Units
V
I
Input voltage range
Output voltage range
DC input voltage
DC output current
V
CC
V
O
0.5
V
V
I_DC
3.8
I
100
1.0
mA
W
O_DC
o
Power
Maximum power dissipation at T = 55 C in still air
A
o
T
STG
Storage temperature
65
150
C
Note:
Stress beyond those listed under absolute maximum ratings may cause permanent damage to the device.
Parameter
Test Conditions
V
Min.
Typ.
Max.
10
Units
CC
(1)
I
CC
V = V or GND; I = 0 Standby Current
3.6V
µA
I
CC
O
C
V = V or GND
4
6
I
I
CC
3.3V
pF
C
V =V or GND
O CC
O
Note:
1. Continuous Output Current
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PI6C2502A
Phase-LockedLoopClockDriver
Recommended Operating Conditions
Symbol
Parameter
Min.
3.0
Max.
Units
V
VCC
VIH
VIL
VI
Supply voltage
3.6
High level input voltage
Low level input voltage
Input voltage
2.0
0.8
VCC
70
0
0
TA
Operating free-air temperature
ºC
ElectricalCharacteristics(OverRecommendedOperatingFree-AirTemperatureRange
PullUp/DownCurrentsofPI6C2502A,VCC =3.0V)
Symbol
Parameter
Condition
Vout = 2.4V
Min.
Max.
Units
Pull-up current
Pull-up current
13.6
22
I
OH
Vout = 2.0V
Vout = 0.8V
mA
Pull-down current
Pull-down current
19
13
I
OL
Vout = 0.55V
AC Specifications
(Timing requirements over recommended ranges of supply voltage and operating free-air temperature)
Symbol
Parameter
Clock frequency PI6C2502A
Input clock duty cycle
Min.
80
Max.
134
60
Units
MHz
%
F
CLK
D
CYI
40
Stabilization Time after power up
1
ms
SwitchingCharacteristics
(Over recommended ranges of supply voltage and operating free-air temperature, CL = 30pF)
V
= 3.3V ±0.3V, 0-70°C
CC
Parameter
From (Input)
To (Output)
Units
Min.
Typ.
Max.
tphase error without jitter
CLK_IN↑ at 100 & 66 MHz
FB_IN↑
150
+150
ps
Jitter, cycle-to-cycle
Duty cycle
At 100 & 66 MHz
75
45
+75
55
%
ns
CLK_OUT
tr, rise-time, 0.4V to 2.0V
tf, fall-time, 2.0V to 0.4V
1.0
1.1
Note:
These switching parameters are guaranteed by design.
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PI6C2502A
Phase-LockedLoopClockDriver
Package Mechanical Information
Plastic 8-pin SOIC Package
8
3.78
3.99
.149
.157
1
4.80
5.00
.189
.196
0.25
0.50
.0099
.0196
x 45˚
1.35
1.75
.053
.068
.016
.026
REF
0.406
0.660
SEATING PLANE
0-8˚
0.19
0.25
.0075
.0098
0.40 .016
0.10
0.25
.0040
.0098
1.27
.050
.050
BSC
.2284
.2440
5.80
.013
.020
0.330
0.508
1.27
6.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
PI6C2502AW
W8
8-pin 150-mil SOIC
Commercial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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