PI6C2972FCE [PERICOM]
Low Voltage PLL Clock Driver; 低电压PLL时钟驱动器
| 型号： | PI6C2972FCE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Low Voltage PLL Clock Driver |
| 文件： | 总7页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C2972
Low Voltage PLL Clock Driver
Description
Features
ThePI6C2972are3.3Vcompatible,PLLbasedclockdriverdevices
targeted for high-performance CISC or RISC processor based sys-
tems.Withoutputfrequenciesofupto125MHzandskewsof550ps
thePI6C2972areideallysuitedformostsynchronoussystems. The
devices offer twelve low skew outputs plus a feedback and sync
output for added flexibility and ease of system implementation.
• FullyIntegratedPLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3VV
CC
• + 100ps Typical Cycle–to–Cycle Jitter
ThePI6C2972featuresanextensiveleveloffrequencyprogramma-
bility between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1,
2:1,3:1,3:2,4:1,4:3,5:1,5:2,5:3,6:1and6:5betweenoutputscanbe
realizedbypulsinglowoneclockedgepriortothecoincidentedges
of the Qa and Qc outputs. The Sync output will indicate when the
coincident rising edges of the above relationships will occur. The
Power–On Reset ensures proper programming if the frequency
select pins are set at power up. If the fselFB2 pin is held high, it may
be necessary to apply a reset after power–up to ensure synchroni-
zation between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with
power–up conditions being dependent, it is difficult to guarantee.
All other conditions of the fsel pins will automatically synchronize
duringPLLlockacquisition.
The PI6C2972 offers a very flexible output enable/disable scheme.
NotethatallofthecontrolinputsonthePI6C2972haveinternalpull–
up resistors.
ThePI6C2972isfully3.3Vcompatibleandrequiresnoexternalloop
filtercomponents.AllinputsacceptLVCMOS/LVTTLcompatible
levelswhiletheoutputsprovideLVCMOSlevelswiththecapability
todrive50-ohmtransmissionlines. Forseriesterminatedlineseach
PI6C2972 output can drive two 50-ohm lines in parallel thus effec-
tively doubling the fanout of the device.
• Packaging(Pb-free&Greenavailable):
-52-pinLQFP(FC)
PinConfiguration
39 38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
fselFB1
QSync
GNDO
Qc0
fselb1
fselb0
fsela1
fsela0
Qa3
40
41
42
43
44
45
46
47
48
49
50
51
52
VCCO
Qc1
VCCO
Qa2
fselc0
fselc1
Qc2
GNDO
Qa1
VCCO
Qc3
VCCO
Qa0
GND0
Inv_Clk
GND0
VCO_Sel
1
2
3
4
5
6
7
8
9 10 11 12 13
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PI6C2972
LowVoltagePLLClockDriver
BlockDiagram
xtal_1
xtal_2
VC0_Sel
PLL_En
REF_Sel
Sync
Frz
Q
D
Qa0
Qa1
Qa2
Qa3
0
1
0
1
TCLK0
PHASE
DETECTOR
VCO
TCLK1
TCLK_Sel
LPF
Ext_FB
Sync
Frz
Q
D
Qb0
Qb1
Qb2
Qb3
fselFB2
MR/OE
Q
D
Qc0
Qc1
POWER-ON
RESET
Sync
Frz
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
Sync
Frz
Q
Q
D
D
Qc2
Qc3
QFB
÷2, ÷4, ÷6, ÷8
2
2
0
1
fsela0:1
fselb0:1
÷4, ÷6, ÷8, ÷10
Sync Pulse
÷2
2
2
fselc0:1
fselFBO:1
Data Generator
Sync
Frz
D
QSync
Q
Frz_Clk
Output Disable
Circuitry
12
Frz_Data
Inv_Clk
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PI6C2972
LowVoltagePLLClockDriver
FunctionTable1
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0
0
1
1
0
1
0
1
÷4
÷6
0
0
1
1
0
1
0
1
÷4
÷6
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
÷8
÷8
÷12
÷10
FunctionTable2
fselFB2
fselFB1
fselFB0
QFB
0
0
0
0
0
0
1
1
0
1
0
1
÷4
÷6
÷8
÷10
1
1
1
1
0
0
1
1
0
1
0
1
÷8
÷12
÷16
÷20
FunctionTable3
Control Pin
Logic '0'
Logic '1'
VCO_Sel
Ref_Sel
VCO/2
TCLK
VCO
Xtal
TCLK_Sel
PLL_En
TCLK0
TCLK1
Bypass PLL
Master Reset/Output Hi-Z
Non-Inverted Qc2, Qc3
Enable PLL
Enable Outputs
Inverted Qc2, Qc3
MR/OE
Inv_CLK
CrystalRecommendations
Parameters
Value
Crystal Cut
Fundamental AT Cut
Parallel Resonance
±100ppm @ 25°C
±175ppm (0° to 70°C)
0° to 70°C
Resonance
Freq. Tolernace
Freq. Temp. Stability
Operating Range
Shunt Capacitance
ESR
< 7pF
< 40-Ohm
Drive Level
5mW
Aging
5ppm / Year (First 3 years)
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PI6C2972
LowVoltagePLLClockDriver
TimingDiagrams
fVCO
Qa
1:1 Mode
2:1 Mode
Qc
Sync
Qa
Qc
Sync
3:1 Mode
3:2 Mode
Qc( 2)
Qa( 6)
Sync
Qa( 4)
Qc( 6)
Sync
4:1 Mode
4:3 Mode
Qc( 2)
Qa( 8)
Sync
Qa( 6)
Qc( 8)
Sync
1:6 Mode
Qa( 12)
Qc( 2)
Sync
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PI6C2972
LowVoltagePLLClockDriver
AbsoluteMaximumRatings
Symbol
Parameter
Supply Voltage
Input Voltage
Min.
–0.3
–0.3
Max.
Units
V
V
CC
4.6
V
I
V
+0.3
V
DD
I
Input Current
±20
125
mA
°C
IN
T
Storage Temperature
–40
STOR
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute-maximum-rated conditions is not implied.
(4)
DC Characteristics (T = 0°C to 70°C, V = 3.3V ± 5%)
A
CC
Symbol
VIH
Conditions
Characteristic
Min.
Typ.
Max.
3.6
Units
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
2.0
VIL
0.8
V
VOH
VOL
IIN
IOH = 20mA(2)
IOL = 20mA(2)
Note 3
2.4
0.5
±120
215
20
µΑ
ICC
Maximum Quiescent Supply Current
Analog VCC Current
Input Capacitance
190
15
mA
ICCA
CIN
4
pF
Cpd
Per Output
Power Dissipation Capacitance
25
Notes:
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the “High” input is within the VCMR range and the input lies within the VPP specification.
2. The PI6C2972 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to VCC/2) transmission lines on the
incidentedge.
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
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PI6C2972
LowVoltagePLLClockDriver
PLL Input Reference Characteristic (T = 0°C to 70°C)
A
Symbol
Conditions
Characteristics
Min.
Max.
Units
tr, tf
fref
TCLK Input Rise/Falls
Reference Input Frequency
Reference Input Duty Cycle
Crystal Oscillator Frequency
3.0
100, Note 5
75
ns
Note 5
Note 5
25
MHz
%
frefDC
txtal
10
25
MHz
Notes:
5. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100 MHz,
minimum input reference frequency is limited by the VCO lock range and the feedback divider.
AC Characteristics (T = 0°C to 70°C, V = 3.3V ± 5%)
A
CC
Symbol
Characteristics
Conditions
Min.
Typ.
Max.
Units
tr, t
Output Rise/Fall Time (Note7)
Output Duty Cycle (Note7)
0.8 to 2.0V
0.15
1.2
ns
f
t
/2
t
/2
t
/2
CYCLE
–750
CYCLE
CYCLE
+750
t
pw
±500
Propagation Delay
Notes 7, 8, QFB = ÷8
TCLK0
TCLK1
–270
–330
130
70
530
470
ps
t
pd
t
Output-to-Output Skew
VCO Lock Range
Note 7
550
480
os
f
200
VCO
Maximum Output Frequency Q (÷2)
125
120
80
MHz
Q (÷4)
Q (÷6)
Q (÷8)
f
max
60
Note 7
tjitter
, t
Cycle–to–Cycle Jitter (Peak–to–Peak)
Output Disable Time
±100
ps
ns
t
2
2
8
PLZ PHZ
t
,t
Output ENable TIme
10
10
20
PZL PZH
t
Maximum PLL Lock Time
Maximum Frz_Clk Frequency
ms
lock
f
MHz
MAX
Notes:
7. 50OhmtransmissionlineterminatedintoV /2
CC
8. tpd is specified for a 50 MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/
longer input reference periods. The tpd does not include jitter.
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PI6C2972
LowVoltagePLLClockDriver
Start
Bit
D0 D1 D2 D3
D4 D5
D6
D7
D8
D9 D10 D11
D0–D3 are the control bits for Qa0–Qa3, respectively
D4–D7 are the control bits for Qb0–Qb3, respectively
D8–D10 are the control bits for Qc1–Qc3, respectively
D11 is the control bit for QSync
FreezeDataInputProtocol
PackagingMechanical:52-PinLQFP(FC)
12.00 BSC
.472
Square
10.00 BSC
.394
0.09
0.20
Square
.004
.008
GAUGE PLANE
0
7
0.45
0.75
.018
.030
1.00 REF
.039
1.60
.063
Max.
.004
0.10
Seating Plane
1.35
1.45
0.05
0.15
0.65 BSC
.026
0.22
0.38
.009
.015
.053
.057
.002
.006
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
OrderingInformation
OrderingCode
PI6C2972FC
PI6C2972FCE
PackageCode
PackageType
52-pinLQFP
Pb-free&Green,52-pinLQFP
FC
FC
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
PericomSemiconductorCorporation•1-800-435-2336 • www.pericom.com
PS8590C
09/22/04
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