PI6C410MAE [PERICOM]
Clock Generator for Intel PCI Express Mobile Chipset; 时钟发生器为英特尔的PCI Express移动芯片组
| 型号： | PI6C410MAE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Clock Generator for Intel PCI Express Mobile Chipset |
| 文件： | 总21页 (文件大小：930K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C410M/410MA
Clock Generator for Intel PCI Express Mobile Chipset
Features
Description
•
14.318 MHz Crystal Input
PI6C410M is a high-speed, low-noise clock generator designed
to work with the Intel Mobile PCI Express Chipset. This Spread
Spectrum PLL based clock generator reduces EMI emission and
supports a wide range of frequencies.
•
Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz
CPU Output Frequencies
•
•
•
SMBus: Power Management Control
Spread Spectrum support (-0.5% down spread)
Jitter Performance
Packaging (Pb-free & Green available):
— 56-Pin TSSOP
• < 85ps Cycle-to-Cycle CPU 0/1 clock jitter
• < 125ps Cycle-to-Cycle CPU 2 clock jitter
• < 350ps Cycle-to-Cycle 48 MHz clock jitter
• < 500ps Cycle-to-Cycle PCI clock jitter
• < 125ps Cycle-to-Cycle SRC clock jitter
• < 1000ps Cycle-to-Cycle REF clock jitter
Output Features
•
•
•
•
•
•
•
Two Pairs of Differential CPU Clocks
One selectable of CPU/SRC Clock
Seven Pairs of SRC Clocks
Six PCI Clocks
Skew Performance
• < 100ps Output-to-output CPU 0/1 clock skew
• < 150ps Output-to-output CPU 2 clock skew
• < 500ps Output-to-output PCI clock skew
• < 250ps Output-to-output SRC clock skew
One 48 MHz USB clock
One REF clock
One 96 MHz Differential clock
Pin Configuration
Block Diagram
DOT_96
DOT 96#
VDD_PCI
VSS_PCI
PCI_3
PCI_4
PCI_5
VSS_PCI
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI_2
XTAL_IN
XTAL
OSC
PLL 2
PCI_STOP#
CPU_STOP#
FS_C / TEST_SEL
REF
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
SCL
VSS_CPU
CPU_0
CPU_0#
VDD_CPU
CPU_1
CPU_1#
IREF
VSS_A
VDD_A
CPU2_ITP / SRC7
CPU2_ITP# / SRC7#
VDD_SRC
SRC_6
SRC_6#
SRC_5
XTAL_OUT
USB_48 / FS_A
REF
/2
SDA
SMBus
Logic
VDD_PCI
PCIF_0 / ITP_EN
PCIF_1
SCL
9
PLL 1
VTT_PWRGD# / PWRDWN
VDD_48
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCIF_0 / ITP_EN
USB_48 / FS_A
USB_48/FS_A
VSS_48
C
O
N
T
R
O
L
PCI [2:5]
PCIF[0:1]
Div
Div
DOT_96
FS_B / TEST_MODE
FS_C / TEST_SEL
DOT_96#
FS_B / TEST_MODE
SRC_0
SRC [0:6]
SRC [0:6]#
VTT_PWRGD#
/ PWRDWN
SRC_0#
SRC_1
SRC_1#
VDD_SRC
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
CPU2_ITP / SRC7
CPU2_ITP# / SRC7#
PCI_STOP#
CPU_STOP#
CPU[0:1]
CPU[0:1]#
Div
SRC_4#
VDD_SRC
SRC_5#
VSS_SRC
PS8736C
12/19/05
1
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Pin Description
Pin Name
Type
Output
Input
Pin Number
Descriptions
REF
52
3.3V 14.31818 MHz output
14.31818 MHz crystal input
14.31818 MHz crystal output
Differential CPU outputs
XTAL_IN
50
49
XTAL_OUT
CPU[0:1] & CPU[0:1]#
Output
Output
40, 41, 43, 44
17, 18, 19, 20,
22, 23, 24, 25,
26, 27, 30, 31,
32, 33
SRC[0:6] & SRC[0:6]#
Output
Differential Serial Reference Clock outputs
Selectable Differential CPU or SRC clock output
ITP_EN = 0 @ Vtt_Pwrgd# assertion = SRC
ITP_EN = 1 @ Vtt_Pwrgd# assertion = CPU
CPU2_ITP / SRC_7 &
CPU2_ITP# / SRC_7#
Output
35, 36
Input /
Output
PCIF_0 / ITP_EN
8
33 MHz clock output / CPU2 select when HIGH
PCIF_1
Output
Output
9
33 MHz clocks outputs (free running)
33 MHz clocks outputs
PCI[2:5]
3, 4, 5, 56
Input /
Output
USB_48 / FS_A
DOT_96 & DOT_96#
PCI_STOP#
12
14, 15
55
48 MHz clock output / 3.3V LVTTL inputs for CPU frequency selection
Output
96 MHz differential clock output
3.3V LVTTL active low input for PCI Stop operation.
(150k-ohm internal pull-up resistor)
Input
3.3V LVTTL active low input for CPU Stop operation.
(150k-ohm internal pull-up resistor)
CPU_STOP#
Input
Input
54
16
3.3V LVTTL inputs for CPU frequency selection / Test Mode select: 0 =
Hi-Z, 1 = Ref/N
FS_B / TEST_MODE
3.3V LVTTL inputs for CPU frequency selection / Test Mode select if
pulled to 3.3V when Vtt_Pwrgd# is asserted LOW
FS_C / TEST_SEL
IREF
Input
Input
53
39
External resistor connection for internal current reference
3.3V LVTTL Level sensitive strobe used to determine to latch the FS_A,
FS_B/TEST_MODE, FS_C/TEST_SEL and PCIF0/ITP_EN inputs (ac-
tive low) / 3.3V LVTTL active high input for Power Down operation.
VTT_PWRGD# /
PWRDWN
Input
10
SDA
I/O
47
46
SMBus compatible SDATA
SMBus compatible SCLOCK
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
Ground for Outputs
SCL
Input
VDD_PCI
VDD_48
VDD_SRC
VDD_CPU
VDD_REF
VSS_PCI
VSS_48
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Power
Ground
1, 7
11
21, 28, 34
42
48
2, 6
13
Ground for Outputs
VSS_SRC
VSS_CPU
VSS_REF
VDD_A
VSS_A
29
Ground for Outputs
45
Ground for Outputs
51
Ground for Outputs
37
3.3V Power Supply for PLL
Ground for PLL
38
PS8736C
12/19/05
2
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Functionality
(1)
Frequency Selection
FS_C
FS_B
FS_A
CPU
SRC
PCIF / PCI
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
REF
DOT_96
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
USB_48
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
333 MHz
400 MHz
Reserved
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Note:
1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels.
(2)
Test Mode Selection
TEST_MODE
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCIF / PCI
REF/N
REF
REF
Hi-Z
DOT_96
USB_48
1
0
REF/N
Hi-Z
REF/N
Hi-Z
Hi-Z
Note:
2. Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
PWRDWN Functionality
PCIF /
PWRDWN
CPU
CPU#
Normal
Float
SRC
SRC#
Normal
Float
REF
DOT_96 DOT_96# USB_48
PCI
14.318
MHz
0
1
Normal
Normal
33 MHz
Normal
Normal
Float
48 MHz
Low
Iref × 2 or
Iref × 2 or
Iref × 2 or
Low
Low
Float
Float
Float
PCI_STOP# Functionality
PCIF /
PCI
PCI_STOP#
CPU
CPU#
Normal
Normal
SRC
SRC#
Normal
Low
REF
DOT_96 DOT_96# USB_48
14.318
MHz
1
0
Normal
Normal
Normal
33 MHz
Low
Normal
Normal
Normal
Normal
48 MHz
48 MHz
Iref × 6 or
14.318
MHz
Float
CPU_STOP# Functionality
PCIF /
PCI
CPU_STOP#
CPU
CPU#
Normal
Low
SRC
SRC#
Normal
Normal
REF
DOT_96 DOT_96# USB_48
14.318
MHz
1
0
Normal
Normal
Normal
33 MHz
33 MHz
Normal
Normal
Normal
Normal
48 MHz
48 MHz
Iref × 6 or
14.318
MHz
Float
PS8736C
12/19/05
3
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Serial Data Interface (SMBus)
PI6C410M is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
I/0
(1)
Data Protocol
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Byte
Count
= N
Data
Byte N
- 1
Start
bit
Register
offset
Data
Byte 0
Stop
bit
Slave Addr R/W
Ack
Ack
Ack
Ack
Ack
Note:
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
1
Data Byte 0: Control Register
Power Up
Condition
Source
Pin
Bit
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Output(s) Affected
SRC_0
Pin
SRC_0 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
0
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
17, 18
19, 20
22, 23
24, 25
26, 27
30, 31
32, 33
35, 36
NA
SRC_1 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
1
SRC_1
NA
NA
NA
NA
NA
NA
NA
SRC_2 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
2
SRC_2
SRC_3 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
3
SRC_3
SRC_4 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
4
SRC_4
SRC_5 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
5
SRC_5
SRC_6 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
6
SRC_6
CPU_2 / SRC_7 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
7
CPU_2 / SRC_7
PS8736C
12/19/05
4
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Data Byte 1: Control Register
Power Up
Condition
Source
Bit
Descriptions
Type
RW
Output(s) Affected
Pin
Pin
3, 4, 5, 8, 9, 17,
18, 19, 20, 22, 23,
24, 25, 26, 27, 30,
31, 32, 33, 35, 36,
40, 41, 43, 44, 56
Spread Spectrum
1 = Enable, 0 = Disable
CPU[0:2], SRC[0:7],
PCI[2:5], PCIF[0:1]
0
0 = Spread off
NA
CPU_0 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
1
RW
1 = Enabled
1 = Enabled
CPU_0, CPU_0#
CPU_1, CPU_1#
43, 44
40, 41
NA
NA
CPU_1 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
2
3
4
RW
RW
RW
Reserved
REF Output Enable
1 = Enabled, 0 = Disabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
REF
USB_48
52
12
NA
NA
NA
NA
USB_48 Output Enable
1 = Enabled, 0 = Disabled
5
6
7
RW
RW
RW
DOT_96 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
DOT_96 & DOT96#
PCIF_O
14, 15
8
PCIF_0 Output Enable
1 = Enabled, 0 = Disabled
Data Byte 2: Control Register
Power Up
Condition
Source
Pin
Bit
Descriptions
Type
Output(s) Affected
Pin
PCIF_1 Output Enable
1 = Enabled, 0 = Disabled
0
RW
1 = Enabled
PCIF_1
9
NA
NA
1
2
3
Reserved
Reserved
Reserved
RW
RW
RW
PCI _2 Output Enable
1 = Enabled, 0 = Disabled
4
5
6
7
RW
RW
RW
RW
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
PCI_2
PCI_3
PCI_4
PCI_5
56
3
NA
NA
NA
NA
PCI _3 Output Enable
1 = Enabled, 0 = Disabled
PCI _4 Output Enable
1 = Enabled, 0 = Disabled
4
PCI _5 Output Enable
1 = Enabled, 0 = Disabled
5
PS8736C
12/19/05
5
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Data Byte 3: Control Register
Power Up
Condition
Source
Pin
Bit
Descriptions
Type
Output(s) Affected
Pin
SRC_0 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
0
RW
SRC_0
SRC_1
SRC_2
SRC_3
SRC_4
SRC_5
SRC_6
SRC_7
17, 18
NA
SRC_1 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
1
2
3
4
5
6
7
RW
RW
RW
RW
RW
RW
RW
19, 20
22, 23
24, 25
26, 27
30, 31
32, 33
35, 36
NA
NA
NA
NA
NA
NA
NA
SRC_2 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
SRC_3 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
SRC_4 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
SRC_5 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
SRC_6 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
SRC_7 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
PS8736C
12/19/05
6
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Data Byte 4: Control Register
Power Up
Condition
Source
Pin
Bit
Descriptions
Type
Output(s) Affected
Pin
CPU_0 Output Control
0 = Free Running,
1 = Stopped with CPU_STOP#
1 = Stopped with
CPU_STOP#
assertion
0
RW
CPU_0
CPU_1
CPU_2
PCIF_0
PCIF_1
43, 44
NA
CPU_1 Output Control
0 = Free Running,
1 = Stopped with CPU_STOP#
1 = Stopped with
CPU_STOP#
assertion
1
2
3
4
RW
RW
RW
RW
40, 41
NA
NA
NA
NA
CPU_2 Output Control
0 = Free Running,
1 = Stopped with CPU_STOP#
1 = Stopped with
CPU_STOP#
assertion
35, 36
PCIF_0 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
8
9
PCIF_1 Output Control
0 = Free Running,
1 = Stopped with PCI_STOP#
0 = Free running,
not affected by
PCI_STOP#
5
6
7
Reserved
RW
RW
RW
DOT_Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
DOT_96 &
DOT_96#
14, 15
NA
Reserved
Data Byte 5: Control Register
Power Up
Condition
Source
Pin
Bit
Descriptions
Type
Output(s) Affected
CPU_0 & CPU_0#
CPU_1 & CPU_1#
CPU_2 & CPU_2#
Pin
CPU_0 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
0
RW
RW
RW
43, 44
40, 41
35, 36
NA
NA
NA
CPU_1 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
1
CPU_2 Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
2
17, 18, 19, 20, 22,
23, 24, 25, 26, 27,
30, 31, 32, 35, 36
SRC_Pwrdwn drive mode
1 = Hi-Z, 0 = Driven in Pwrdwn
0 = Driven in
power down
SRC[0:7] &
SRC[0:7]#
3
RW
NA
CPU_0 Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
0 = Driven in
CPU_STOP
4
5
6
RW
RW
RW
CPU_0 & CPU_0#
CPU_1 & CPU_1#
CPU_2 & CPU_2#
43, 44
40, 41
35, 36
NA
NA
NA
CPU_1 Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
0 = Driven in
CPU_STOP
CPU_2 Stop drive mode
1 = Hi-Z, 0 = Driven in CPU Stop
0 = Driven in
CPU_STOP
17, 18, 19, 20, 22,
23
24, 25, 26, 27, 30,
31
SRC_Stop drive mode
1 = Hi-Z, 0 = Driven in PCI Stop
0 = Driven in
PCI_STOP
SRC[0:7] &
SRC[0:7]#
7
RW
NA
32, 33, 35, 36
PS8736C
12/19/05
7
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Data Byte 6: Control Register
Power Up
Condition
Source
Bit
Descriptions
Type
Output(s) Affected
Pin
Pin
FS_A Reflects the value of the
FS_A pin sampled on power up
0 = FS_A was low during
Vtt_Pwrgd# assertion
Externally Se-
lected
35, 36, 40, 41, 43,
0
R
CPU[0:2]
NA
44
FS_B Reflects the value of the
FS_B pin sampled on power up
0 = FS_B was low during
Vtt_Pwrgd# assertion
Externally Se-
lected
35, 36, 40, 41, 43,
1
2
3
R
R
CPU[0:2]
CPU[0:2]
NA
44
FS_C Reflects the value of the
FS_C pin sampled on power up
0 = FS_C was low during
Vtt_Pwrgd# assertion
Externally Se-
lected
35, 36, 40, 41, 43,
NA
44
PCI_Stop control
1 = Disabled,
0 = Enabled, Stopped SRC and
PCI clocks
All PCI & SRC
clocks except PCIF
3, 4, 5, 17, 18, 19,
20, 22, 23, 24, 25,
and SRC clocks set to 26, 27, 30, 31, 32,
RW
1 = Disabled
1 = 2X
NA
free-running
33, 35, 36, 56
REF Output Drive Strength
0 = 1x, 1 = 2x
4
5
6
RW
RW
RW
REF
52
NA
NA
Reserved
Test Clock Mode Entry Control
0 = Disabled, 1 = REF/N or Hi-Z
0 = Disabled
0 = Hi-Z
3, 4, 5, 8, 9, 12,
14, 15, 17, 18, 19,
20, 22, 23, 24, 25,
26, 27, 30, 31, 32,
33, 35, 36, 40, 41,
43, 44, 52, 56
CPU[0:2],
SRC[0:7],
PCI[2:5],
Test Clock Mode
0 = Hi-Z, 1 = REF/N
7
RW
PCIF[0:1], REF,
USB_48, DOT_96
DataByte 7: Control Register
Bit
Descriptions
Type
R
Power Up Condition
Output(s) Affected
Pin
0
0
0
0
0
1
0
1
0
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1
R
Vendor ID
2
R
3
R
4
R
5
R
Revision Code
6
R
7
R
PS8736C
12/19/05
8
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Vtt_Pwrgd# Timing Diagram
Vcc to VRM 5/12V
Vtt
FS_A, FS_B, FS_C
Vtt_Pwrgd from VRM
Vtt_Pwrgd#
Vcc Core
PwrGood
Vcc Clock Gen
0.2-0.3ms
Delay
Wait for
Vtt_Pwrgd#
Clock State
Clock Outputs
Clock VCO
State 0
State 1
State 2
State 3
On
Off
Off
On
Figure 1. CPU power BEFORE clock power
Vcc to VRM 5/12V
Vtt
FS_A, FS_B, FS_C
Vtt_Pwrgd from VRM
Vtt_Pwrgd#
Vcc Core
PwrGood
Vcc Clock Gen
0.2-0.3ms
Delay
Wait for
Vtt_P wrgd#
Clock State State 0
State 1
State 2
State 3
Clock Outputs
Clock VCO
On
Off
Off
On
Figure 2. CPU power AFTER clock power
PS8736C
12/19/05
9
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Clock Power-Up State Machine
Vtt_Pwrgd# = Low
S1
S2
Delay
Sample
>0.25ms
Input Straps
Vdda = 2.0V
S0
Power Off
S3
Normal
Operation
Vdda = Off
Enable Outputs
Vtt_Pwrgd# = toggle
Figure 3. Power-Up State Diagram
Power Down (PWRDWN assertion)
PWRDWN
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
DOT, 96MHz
DOT#, 96MHz
PCI, 33MHz
REF
Figure 4. Power down sequence
PS8736C
12/19/05
10
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Power Down (PWRDWN De-assertion)
Tstable
<1.8ms
PWRDWN
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
DOT, 96MHz
DOT#, 96MHz
PCI, 33MHz
REF
Tdrive_PwrDwn
<300us, >200mV
Figure 5. Power down de-assetion
CPU STOP (CPU_STOP# assertation)
CPU_Stop#
CPU
CPU#
Figure 6. Assertion of CPU_Stop# Waveforms
PS8736C
12/19/05
11
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
CPU STOP (CPU_STOP# De-assertion)
CPU_Stop#
CPU
CPU#
CPU Internal
CPU# Internal
Tdrive_CPU_Stop#, 10ns
>200mV
Figure 7. CPU_STOP# De-assertion Waveform
PCI STOP (PCI_STOP# assertion)
T
(10ns min.)
SU
PCI_Stop#
PCIF[0:1], 33MHz
PCI[2:5], 33MHz
SRC, 100MHz
SRC#, 100MHz
Figure 8. Assertion of PCI_STOP# Waveform
PCI STOP (PCI_STOP# De-assertion)
T
SU (10ns mins.)
Tdrive_SRC < 15ns
PCI_Stop#
PCIF[0:1], 33MHz
PCI[2:5], 33MHz
SRC#, 100MHz
SRC, 100MHz
Figure 8. De-assertion of PCI_STOP# Waveform
PS8736C
12/19/05
12
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Tristate Specifications
CPU Tristate clock truth table
Pwrdwn
CPU_STOP#
Non-stop
Stoppable
Outputs
CPU_Stop
Tristate Bit
Pwrdwn
Tristate Bit
Signal
pin
0
pin
1
Outputs
Running
X
0
X
X
X
0
Running
0
0
Running
Driven @ Iref x 6
Tristate
CPU[0:2]
0
0
1
Running
1
X
X
X
X
Driven @ Iref x 2
Tristate
Driven @ Iref x 2
Tristate
1
1
SRC Tristate clock truth table
Pwrdwn
PCI_STOP#
Non-stop
Outputs
Stoppable
Outputs
PCI_Stop
Tristate Bit
Pwrdwn
Tristate Bit
Signal
pin
0
pin
1
X
0
X
X
X
0
Running
Running
0
0
Running
Driven @ Iref x 6
Tristate
SRC[0:7]
0
0
1
Running
1
X
X
X
X
Driven @ Iref x 2
Tristate
Driven @ Iref x 2
Tristate
1
1
DOT Tristate clock truth table
Pwrdwn
Stoppable
Signal
Pwrdwn Tristate Bit
pin
0
Outputs
Running
X
0
DOT96
1
Driven @ Iref x 2
Tristate
1
1
CPU Clock Tristate Timing
1.8ms
CPU_Stop#
PWRDWN
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
DOT
DOT#
Figure 10. CPU_STOP = Driven, CPU_PWRDWN = Driven, DOT_PWRDWN = Driven
PS8736C
12/19/05
13
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
1.8ms
CPU_Stop#
PWRDWN
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Figure 11. CPU_Stop = Tristate, CPU_PWRDWN = Driven
1.8ms
CPU_Stop#
PWRDWN
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
PU# (Stoppable)
Figure 12. CPU_Stop = Driven, CPU_PWRDWN = Tristate
1.8ms
CPU_Stop#
PWRDWN
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
DOT
DOT#
Figure 13. CPU_STOP = Tristate, CPU_PWRDWN = Tristate, DOT_PWRDWN = Tristate
PS8736C
12/19/05
14
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
1.8ms
PCI_Stop#
PCI (Free Running)
PWRDWN
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Figure 14. SRC_Stop = Driven, SRC_PWRDWN = Driven
1.8ms
PCI_Stop#
PCI (Free Running)
PWRDWN
CPU (Free Running)
CPU# (Free Running
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Figure 15. SRC_Stop = Tristate, SRC_PWRDWN = Tristate
1.8ms
PCI_Stop#
PCI (Free Running)
PWRDWN
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
Figure 16. SRC_STOP = Tristate, SRC_PWRDWN = Tristate, PCI_STOP# = Asserted
PS8736C
12/19/05
15
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Spread Spectrum Specifications
PI6C410M supports Spread Spectrum clocking and can be enabled and disabled via SMBus control. The maximum Spread Spec-
trum Modulation is –0.5% down spread with frequency from 30KHz to 33KHz.
Tperiod
Tperiod
Unit
SSC ON
SSC OFF
Min
Max
2.5133
3.016
3.77
Min
Max
CPU @ 399.000 MHz
CPU @ 332.500 MHz
CPU @ 266.000 MHz
CPU @ 199.500 MHz
CPU @ 166.250 MHz
CPU @ 133.000 MHz
CPU @ 99.750 MHz
2.4993
2.9991
3.7489
4.9985
5.9982
7.4978
9.997
CPU @ 400.000 MHz
CPU @ 333.333 MHz
CPU @ 266.666 MHz
CPU @ 200.000 MHz
CPU @ 166.666 MHz
CPU @ 133.333 MHz
CPU @ 100.000 MHz
2.4993
2.9991
3.7489
4.9985
5.9982
7.4978
9.997
2.5008
3.0009
3.7511
5.0015
6.0018
7.5023
10.003
5.0266
6.032
7.54
ns
10.0533
SRC @ 99.750 MHz
9.997
10.0533
30.1598
SRC @ 100.000 MHz
9.997
10.003
30.009
PCIF / PCI @ 33.250 MHz
29.991
PCIF / PCI @ 33.333 MHz
29.991
Current-mode output buffer characteristics of CPU, SRC, and DOT
Vdd
(3.3V ± 5%)
Slope ~1/R
o
Ro
lout
Ros
lout
0V
0.85V
Vout = 0.85V Max.
Figure 17. Simplified diagram of a current-mode output buffer
Host Clock Buffer Characteristics
Min
Max
R
3000 Ω
unspecified
N/A
N/A
O
R
unspecified
850mV
OS
V
OUT
PS8736C
12/19/05
16
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Cueernt Accuracy
Conditions
V = 3.30 ±5%
DD
Configuration
Rref = 475Ω
Iref = 2.32mA
Load
Min.
-12% x I
Max.
+12% x I
NOMINAL
Nominal test load for
given configuration
I
OUT
NOMINAL
Host Clock Output Current
Board Target
Trace/Term Z
Reference R,
Output Current
Voh @ Z
Iref = V /(3xRr)
DD
100Ω
Rref = 475 Ω
Iref = 2.32mA
Ioh = 6 x Iref
0.7V @ 50
(100Ω differential ≈ 8% coupling ratio)
(1)
Crystal Recommendations
Drive
Max.
Shunt Cap Motional Tolerance
Stability
Max.
Aging
Max.
Frequency
Cut Loading Load Cap
Max.
Cap Max.
Max.
14.31818 MHz
AT
Parallel
20pF
0.1mW
5pF
0.016pF
35ppm
30ppm
5ppm
Note:
1. External trim capacitors (Ce) are required. Ce = 2*CL – (Cs + Ci). Typical Ce = 33pF when Crystal-load = 20pF, Ctrace (Cs) = 2.8pF and
CXTAL = 4.5pF.
(1)
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameters
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Min.
-0.5
-0.5
Max.
4.6
Units
V
_A
DD
V
4.6
DD
V
V
4.6
IH
V
-0.5
-65
IL
Ts
Storage Temperature
ESD Protection
150
°C
V
V
2000
ESD
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PS8736C
12/19/05
17
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
DC Electrical Characteristics (V = 3.3±5%, V
= 3.3±5%)
DD
DD_A
Symbol
VDD_A
VDD
Parameters
Condition
Min.
3.135
3.135
2.0
Max.
3.465
3.465
Units
V
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current
3.3V Input High Voltage
3.3V Input Low Voltage
3.3V Output High Voltage
3.3V Output Low Voltage
V
V
V
V
+ 0.3
DD
IH
DD
V
V
V
– 0.3
SS
0.8
+5
+ 0.3
IL
I
0 < V < V
DD
-5
0.7
– 0.3
μA
V
IK
IN
V _FS
IH
DD
V _FS
IL
0.35
SS
V
I
= -1mA
OH
2.4
OH
V
I
= 1mA
OL
0.4
OL
12.2
-29
CPU, SRC, DOT: I = 6 x Iref,
OH
Iref = 2.32mA
15.6
-23
V
= 1.0V
OH
USB
I
Output High Current
OH
V
= 3.135V
OH
V
= 1.0V
-33
OH
mA
REF, PCI
V
= 3.135V
= 1.95V
-33
27
OH
V
29
30
OL
USB
V
= 0.4V
= 1.95V
= 0.4V
OL
OL
I
Output Low Current
OL
V
REF, PCI
V
38
5
OL
Cin
Cxtal
Cout
Lpin
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
3
3
pF
nH
mA
°C
6
6
7
I
Power Supply Current
Power Down Current
Power Down Current
Ambient Temperature
V
= 3.465V, F = 400 MHz
CPU
500
100
12
70
DD
DD
I
Driven outputs
Tristate outputs
SS
I
SS
Ta
0
PS8736C
12/19/05
18
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
AC Electrical Characteristics (V = 3.3±5%, V
= 3.3±5%)
DD
Parameters
Rise and fall Time
DD_A
Symbol
Outputs
Min.
175
0.5
Max. Units Notes
T
/ T
/ T
/ T
CPU, SRC, DOT
PCI/PCIF, REF
USB
700
2.0
2.0
ps
1,2
4
rise
fall
fall
fall
(measured between 0.175V to 0.525V)
Rise and fall Time
(measured between 0.8V to 2.0V)
T
rise
ns
ps
Rise and fall Time
(measured between 0.8V to 2.0V)
T
rise
1.0
5
ΔT / ΔT
CPU, SRC, DOT
CPU0, CPU1
CPU2
Rise and fall Time Variation
CPU – CPU Skew
125
100
200
250
1, 2
rise
fall
T
skew
T
skew
CPU – CPU Skew
1,3,6
4
T
skew
SRC
SRC – SRC Skew
PCI – PCI Skew / REF - REF Skew (measured at
1.5V)
T
skew
PCI/PCIF, REF
500
T
T
T
T
T
T
T
CPU0, CPU1
CPU2
Cycle – Cycle Jitter
85
125
125
250
500
350
1000
1150
jitter
jitter
jitter
jitter
jitter
jitter
ps
Cycle – Cycle Jitter
1, 3
SRC
Cycle – Cycle Jitter
DOT
Cycle – Cycle Jitter
PCI/PCIF
Cycle – Cycle Jitter (measured at 1.5V)
Cycle – Cycle Jitter (measured at 1.5V)
Cycle – Cycle Jitter (measured at 1.5V)
Voltage HIGH including overshoot
Voltage LOW including undershoot
Absolute crossing poing voltages
Total variation of Vcross over all edges
Duty-Cycle
4
5
4
USB
REF
jitter
V
V
CPU, SRC, DOT
CPU, SRC, DOT
CPU, SRC, DOT
CPU, SRC, DOT
CPU, SRC, DOT
660
-300
250
HIGH
LOW
mV
1, 2
Vcross
550
140
55
∆Vcross
T
45
45
%
%
1,3,6
4, 5
DC
T
REF, USB, PCI/PCIF Duty-Cycle (measured at 1.5V)
All clock stabilization from power-up
55
DC
T
stable
<1.8
ms
Fig 2
T
drive
Differential output enable after PwrDwn de-asser-
tion
300
5.0
µs
Pwrdwn
T
rise
/ T
fall
Power down rise and fall time
ns
Pwrdwn
Notes:
1. Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and CL = 2pF.
2. Single-Ended measurement.
3. Differential measurement.
4. PCI, PCIF, and REF CL(min) = 10pF, CL(max) = 30pF.
5. USB CL(min) = 10pF, CL(max) = 20pF.
6. CPU measured at 133 MHz.
PS8736C
12/19/05
19
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Configuration Test Load Board Termination
Clock
Rs = 33Ω
TLA
TLB
PI6C410M
Clock#
2pF
Rs = 33Ω
Rp = 50Ω
2pF
Rp = 50Ω
33Ω
Figure 18. Configuration test load board termination
Note:
1. Maximum 10" trace length for CPU @ 200 MHz, 16" trace for SRC @ 100 MHz.
PS8736C
12/19/05
20
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
Packaging Mechcanical: 56-Pin, 240mil wide, 0.5mm pitch TSSOP (A)
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(1,2,3)
Ordering Information
Ordering Code
PI6C410MA
Package Code
Package Description
A
A
A
A
56-Pin, 240mil wide, 0.5mm pitch TSSOP
PI6C410MAE
Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP
Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP
PI6C410MAAE
PI6C410MAAEX
Pb-free & Green 56-Pin, 240mil wide, 0.5mm pitch TSSOP , Tape and Reel
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS8736C
12/19/05
21
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Low Skew Clock Driver, 6C Series, 1 True Output(s), 1 Inverted Output(s), PDSO8, 0.173 INCH, TSSOP-8
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