PI6C49S1504 [PERICOM]
High Performance Selectable 1:4 Differential Fanout Buffer;
| 型号： | PI6C49S1504 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | High Performance Selectable 1:4 Differential Fanout Buffer |
| 文件： | 总10页 (文件大小：1189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Features
Description
ꢀÎ4 differential outputs with 2 banks
e PI6C49S1504 is a high performance fanout buffer device-
which supports up to 1.5GHz frequency. e device also uses
Pericom's proprietary input detection technique to make sure
illegal input conditions will be detected and reflected by output
states. is device is ideal for systems that need to distribute low
jitter clock signals to multiple destinations.
ꢀÎUser configurable output signaling standard for each bank:
LVDS or LVPECL or HCSL
ꢀÎLVCMOS reference output up to 200MHz
ꢀÎUp to 1.5GHz output frequency for differential outputs
ꢀÎUltra low additive phase jitter: < 0.03 ps (typ) (differential
156.25MHz, 12KHz to 20MHz integration range)
Applications
ꢀÎNetworking systems including switches and Routers
ꢀÎSelectable reference inputs support either single-ended
or differential or Xtal
ꢀÎHigh frequency backplane based computing and telecom
ꢀÎLow skew between outputs within banks (<40ps)
ꢀÎLow delay from input to output (Tpd typ. < 1.5ns)
ꢀÎSeparate Input output supply voltage for level shiꢀing
ꢀÎ2.5V / 3.3V power supply
platforms
ꢀÎIndustrial temperature support
ꢀÎTSSOP-28 package
Block Diagram
Pin Configuration (28-Pin TSSOP)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VEE/GND
NC
1
QA0
nQA0
2
OPMODEA[1:0]
CLK_SEL0
3
VDDO
QA[0:1]
2
CLK_SEL1
CLK0
4
OpModeA0
OpModeA1
QA1
X1
OSC
X2
5
OPMODEB[1:0]
CLK0
nCLK0
CLK1
6
nCLK0
QB[0:1]
2
7
nQA1
CLK1
nCLK1
Ref_out
nCLK1
Xtal_In
Xtal_Out
Sync_OE
IREF
8
Ref_Out
QB0
9
CLK_SEL[1:0]
nQB0
10
11
12
13
14
Sync_OE
Iref
Sync
OpModeB1
OpModeB0
VDDO
VDD
QB1
nQB1
PI6C49S1504
RevA
04/01/13
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Pinout Table
Pin #
Pin Name
Type
Description
1
2
3
4
VEE
Power
-
Negative power supply
No Connect
NC
CLK_SEL0
CLK_SEL1
CLK0
Input
Input
Clock input source selection pin
Clock input source selection pin
5, 6
7, 8
Input
Input
Differential clock input
Differential clock input
nCLK0
CLK1
nCLK1
XTAL_In
XTAL_Out
9
Input
Xtal input pin
Xtal output pin
10
Output
Synchronous output enable for Ref_Out, see Table 3
for functions
11
Sync_OE
IREF
Input
External 475Ω resistor connection to set differential
output current
12
Output
Power
13, 16, 26
VDD
Power supply for core
nQB1
14, 15
Output
Differential output clock
QB1
16, 26
17
VDDO
Power
Input
Input
Power supply for outputs
OpModeB0
OpModeB1
nQB0
Bank B output clock type selection pin
Bank B output clock type selection pin
18
19, 20
21
Output
Output
Output
Differential output clock
Reference output clock
Differential output clock
QB0
Ref_Out
nQA1
22, 23
QA1
24
25
OpModeA1
OpModeA0
nQA0
Input
Input
Bank A output clock type selection pin
Bank A output clock type selection pin
27, 28
Output
Differential output clock
QA0
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Function Table
Table 1: Input select function
CLK_SEL [1]
CLK_SEL [0]
Function
0
0
1
0
XTAL is the selected input
1
CLK0 is the selected reference input
CLK1 is the selected reference input
X
Table 2: Output Mode select function
OPMODEA/B [1]
OPMODEA/B [0]
Output Bank A / Bank B Mode
0
0
1
1
0
1
0
1
LVPECL
LVDS
HCSL
Hi-Z
Table 3: Reference output enable function
Sync_OE
Ref_Out
0
1
Hi-Z
Output enabled
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Storage temperature...................................................-55 to +150ºC
Supply Voltage to Ground Potential (VDD) ............ -0.5 to +4.6V
Inputs (Referenced to GND) ..............................-0.5 to Vcc+0.5V
Clock Output (Referenced to GND)..................-0.5 to Vcc+0.5V
Soldering Temperature (Max of 10 seconds) ....................+260ºC
Latch up..................................................................................200mA
ESD Protection (Input) ..................................2000 V min (HBM)
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. is
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Power Supply Characteristics and Operating Conditions
Symbol
Parameter
Test Condition
Min.
2.375
2.375
Typ.
Max.
3.465
3.465
70
Units
Core Supply Voltage
Output Supply Voltage
Core Power Supply Current
V
V
VDD
VDDO
IDD
All LVPECL outputs unloaded
All LVDS outputs loaded
60
70
45
mA
°C
Output Power Supply Current
IDDO
All HCSL outputs unloaded
Ambient Operating Temperature
-40
85
TA
DC Electrical Specifications - Differential Inputs
Symbol
Parameter
Min.
Typ.
Max.
Units
uA
uA
pF
Input High current
Input Low current
Input capacitance
Input high voltage
Input low voltage
150
IIH
Input = VDD
Input = GND
-150
IIL
3
CIN
VIH
VIL
V
VDD+0.3
-0.3
V
Input Differential Amplitude
PK-PK
0.15
1.3
mV
V
VID
Common model input voltage
GND + 0.5
VCM
VDD-0.85
PI6C49S1504
RevA
04/01/13
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
DC Electrical Specifications - LVCMOS Inputs
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
Input High current
150
uA
IIH
Input = VDD
Input Low current
Input high voltage
Input low voltage
Input high voltage
Input low voltage
Input = GND
VDD=3.3V
VDD=3.3V
VDD=2.5V
VDD=2.5V
-150
2.0
uA
V
IIL
VIH
VIL
VIH
VIL
VDD+0.3
0.8
-0.3
1.7
V
V
VDD+0.3
0.7
-0.3
V
DC Electrical Specifications- LVPECL Outputs
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
2.1
2.6
VDD=3.3V
Output High voltage
V
VOH
1.3
1.6
VDD=2.5V
1.2
0.4
1.8
0.8
V
DD=3.3V
Output Low voltage
V
VOL
VDD=2.5V
DC Electrical Specifications- LVDS Outputs
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
Differential Output Voltage
Output commode voltage
0.35
1.1
0.55
1.3
V
V
VOD
Vocm
1.2
Change in Vocm between com-
pletely output states
DVOcm
50
mV
W
Ro
Output impedance
85
140
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RevA
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
DC Electrical Specifications- HCSL Outputs
Parameter Description
Conditions
Min.
520
0
Typ.
Max.
900
Units
mV
Output High voltage
Output Low voltage
VOH
VOL
150
mV
AC Electrical Specifications – Differential Outputs
Parameter Description
Conditions
Min.
Typ.
Max. Units
LVPECL, LVDS
1500
MHz
250
Clock output frequency
FOUT
Tr
HCSL
Output rise time
Output fall time
Output duty cycle
From 20% to 80%, LVPECL, LVDS
From 20% to 80%, HCSL
From 80% to 20%, LVPECL, LVDS
From 80% to 20%, HCSL
Frequency<650MHz, LVPECL
Frequency<650MHz, LVDS
LVPECL outputs
120
350
120
350
48
150
460
150
460
300
650
300
650
52
ps
ps
ps
Tf
ps
%
TODC
47
53
%
400
250
480
mV
mV
mV
ps
Output swing Single-ended
LVDS outputs, <650MHz
HCSL outputs
VPP
Buffer additive jitter RMS
Absolute crossing voltage
0.03
T
j
HCSL
160
460
140
mV
mV
VCROSS
Total variation of crossing voltage HCSL
DVCROSS
10 outputs devices, outputs in same
tank, with same load, at DUT.
Output Skew
40
ps
TSK
Propagation Delay
Valid to HiZ
1500
ps
ns
ns
TPD
TOD
TOE
200
200
HiZ to valid
Notes:
1. is parameter is guaranteed by design
PI6C49S1504
RevA
04/01/13
6
6
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Output Skew
Propagation Delay
Output Skew T
SK
Propagation Delay T
PD
VOH
CLK/nCLK
QAn/QBn
V
OL
TPLHx
T
PHLx
CLK/ nCLK
VOH
TPLH
T
PHL
VOH
VOL
T
SK
T
SK
VOH
QA/QB
VOL
TR
TF
QAn+1/QBn+1
VOL
T
PLHy
T
PHLy
TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1
T
SK = TPLHy - TPLHx or TSK = TPHLy - TPHLx
Part to Part Skew
Part-to-Part Skew
VOH
CLK/nCLK
VOL
T
PLH1
T
PHL1
VOH
Part1 QA/QB
Part2 QA/QB
V
OL
T
SK
T
SK
VOH
VOL
T
PLH2
T
PHL2
T
SK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1
PI6C49S1504
RevA
04/01/13
7
13-0025
PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Configuration Test Load Board Termination for HCSL Outputs
Rs
33Ω
5%
Clock
TLA
TLB
DUT
Rs
33Ω
5%
Clock#
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
475Ω
1%
1%
Configuration Test Load Board Termination for LVPECL/ LVDS Outputs
LVPECL/LVDS Buffer
VDDQx
Z = 50Ω
o
L = 0 ~ 10 in.
100Ω
Z = 50Ω
o
150*Ω
150*Ω
* remove for LVDS
PI6C49S1504
RevA
04/01/13
8
13-0025
PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Configuration Test Load Board Termination for LVCMOS Outputs
3.3V ±5%
V
V
DD
DDO
15pF
GND
PI6C49S1504
RevA
04/01/13
9
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PI6C49S1504
High Performance Selectable 1:4 Differential Fanout Buffer
Packaging Mechanical: 28-Pin TSSOP (L)
DATE: 05/03/12
REVISION: E
DESCRIPTION: 28 pin, 173mil wide, TSSOP
PACKAGE CODE: L
Notes:
1. Refer JEDEC: MO-153F/AE
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
DOCUMENT CONTROL #: PD-1313
Ordering Code
PI6C49S1504LIE
Notes:
Package Code Package Type
Operating Temperature
L
Pb-free & Green, 28-pin TSSOP
-40 °C to 85 °C
1. ermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. “E” denotes Pb-free and Green
3. Adding an “X” at the end of the ordering code denotes tape and Reel packaging
PI6C49S1504
RevA
04/01/13
10
13-0025
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