PI6CV857LK [PERICOM]

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型号：	PI6CV857LK
厂家：	PERICOM SEMICONDUCTOR CORPORATION
描述：	暂无描述时钟驱动器动态存储器双倍数据速率
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PI6CV857L

PLL Clock Driver for

2.5V DDR-SDRAM Memory

ProductFeatures

ProductDescription

PLL clock distribution optimized for Double Data Rate

SDRAMapplications.

PI6CV857LPLLclockdeviceisdevelopedforregisteredDDRDIMM

applicationsThisPLLClockBufferisdesignedfor2.5V and2.5V

DDQ

Distributes one differential clock input pair to ten differential

clock output pairs.

operation and differential data input and output levels.

PackageoptionsincludeplasticThinShrinkSmall-OutlinePackage

(TSSOP).The device is a zero delay buffer that distributes a differ-

ential clock input pair (CLK, CLK) to ten differential pairs of clock

outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock

outputs(FBOUT,FBOUT). Theclockoutputsarecontrolledbythe

inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V

LVCMOSinput(PWRDWN)andtheAnalogPowerinput(AV ).

When input PWRDWN is low while power is applied, the input

receiversaredisabled,thePLListurnedoffandthedifferentialclock

Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2

Input PWRDWN: LVCMOS

Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2

Externalfeedbackpins(FBIN,FBIN)areusedto

synchronize the outputs to the clock input.

Operates at AV = 2.5V for core circuit and internal PLL,

and V

= 2.5V for differential output drivers

DDQ

AvailablePackages:Plastic48-pinTSSOP

outputs are 3-stated. When the AV is strapped low, the PLL is

turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

willenteralowpowermode.Aninputfrequencydetectioncircuitwill

detectthelowfrequencyconditionandperformthesamelowpower

features as when the PWRDWN input is low.

ThePLLinthePI6CV857Lclockdriverusestheinputclocks(CLK,

CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-

mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).

ThePI6CV857LisalsoabletotrackSpreadSpectrumClockingfor

reducedEMI.

BlockDiagram/PinConfiguration

GND

D D Q

GND

48-Pin

D D Q

CLK

D D Q

P W R DW N

FBIN

D D Q

FBOUT

D D

AGND

GND

D D Q

GND

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

PinoutTable

Pin Name

Pin No.

I/O Type

Description

CLK

Reference Clock input

3,5,10,20,22,27,29,39,44,46

2,6,9,19,23,26,30,40,43,47

Clock outputs.

Complement Clock outputs.

FBOUT

Feedback output, and Complement Feedback Output

FBIN

Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0,

the part is powered down and the differential clock outputs are disabled to a

3-state. When PWRDWN = 1, all differential clock outputs are enabled and run

at the same frequency as CLK.

PWRDWN

4,11,12,15,21,28,34,38,45

Power Supply for I/O.

DDQ

Analog /core power supply. AV can be used to bypass the PLL for testing

Power

purposes. When AV is strapped to ground, PLL is bypassed and CLK is

buffered directly to the device outputs.

AGND

GND

Analog/core ground. Provides the ground reference for the analog/core circuitry

Ground

1,7,8,18,24,25,31,41,42,48

FunctionTable

Inputs

Outputs

FBOUT

PLL State

CLK

FBOUT

GND

Bypassed/off

off

2.5V(nom)

(1)

<20 MHz

Notes: For testing and power saving purposes, PI6CV857L will power down if the frequency of the reference inputs CLK, CLK is well

below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857L will be

powered down when the CLK,CLK stop running.

Z = High impedance

X = Dont care

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

AbsoluteMaximumRatings(Overoperatingfree-airtemperaturerange)

Symbol

Parameter

I/O supply voltage range and analog/core supply voltage range

Input voltage range

Min.

0.5

Max.

Units

V_DDQ, AV_DD

3.6

V_I

V_DDQ±0.5

V_O

Tstg

Output voltage range

Storage temperature

150

^oC

Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

TimingRequirements(Overrecommendedoperatingfree-airtemperature)

AV , V

= 2.5V ±0.2V

DDQ

Symbol

Description

Units

Min.

Max.

170

(1,2)

Operating clock frequency

MHz

(3)

Application clock frequency

Input clock duty cycle

µs

PLL stabilization time after powerup

100

STAB

Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the

other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

DCSpecifications

Recommended Operating Conditions

Symbol

Parameter

Min.

2.3

0.3

1.7

1.8

Nom.

2.5

Max.

2.7

Units

Analog/core supply voltage

DDQ

Output supply voltage

2.5

2.7

Low-level input voltage for PWRDWN pin

High-level input voltage for PWRDWN pin

High-level output voltage

0.7

+0.3

DDQ

Low-level output voltage

0.5

Input differential-pair crossing voltage

Output differential-pair crossing voltage at the DRAM clock input

Input voltage level

/2) 0.2

/2) +0.2

DDQ

/2) 0.2

DDQ

/2) +0.2

DDQ

0.3

+0.3

+0.6

DDQ

Input differential voltage between CK and CK

Output differential voltage between Y[n] &Y[n] and FBOUT & FBOUT

Operating free air temperature

0.36

0.7

DDQ

°C

ElectricalCharacteristics

Parameter

Test Conditions

I = 18mA

, V

Min.

Typ. Max. Units

VDD

DDQ

All inputs

2.3V

1.2

CK, FBIN

V = V

or GND

DDQ

±10

µA

PWRDWN

V = V

DDQ

2.7V

Dynamic supply current of V

= 2.7V

300

100

µA

DDQ

CK & CK <20 MHz or

PWRDWN = Low

Static supply current

(1)

Dynamic supply current of AV

Static supply current

= 2.7V

µA

ADD

CK & CK <20 MHz or

PWRDWN = Low

100

(1)

CK and CK

V = V or GND

2.5V

2.0

3.0

FBIN and FBIN

Note:

1. The maximum power-down clock frequency is below 20 MHz.

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

ACSpecifications

Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 )

AV , V

= 2.5V ±0.2V

DDQ

Parameter

Description

Diagram

Units

Min.

Nom.

Max

tjit(cc)

t( )

Cycle-to-cycle jitter

see Figure 3

see Figure 4

see Figure 5

see Figure 6

see Figure 7

see Figure 8

(1)

Static phase offset

tsk(o)

tjit(per)

tjit(hper)

tsl(i)

Output clock skew

Period jitter

100

1.0

Half-period jitter

Input clock slew rate

100

2.0

(2)

V/ns

tsl(o)

Output clock slew rate

1.0

The PLL on the PI6CV857L is capable of meeting all the above parameters while supporting SSC synthesizers with the following

(3)

parameters

SSC modulation frequency

SSC clock input frequency deviation

PLL loop bandwidth

30.00

0.00

50.00

0.50

kHz

MHz

degrees

Phase angle

0.031

Notes:

1. Static Phase offset does not include Jitter.

2. The slew rate is determined from the IBIS model with test load shown in Figure1.

3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

Z=60Ω

DDR

SDRAM

R=120Ω

DDR

SDRAM

PI6CV857

Figure1.IBISModelOutputLoad

DDQ

Z= 60Ω

R = 10Ω

Z= 50Ω

C = 14pF

R = 50Ω

–V

DDQ

GND

C = 14pF

R = 50Ω

DDQ

GND

PI6CV857

SCOPE

–V

DDQ

Figure2.OutputLoadTestCircuit

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

Yx,FBOUT

t_{cycle n}

t_{cycle n+1}

t_jit(cc)= t_{cycle n}- t_{cycle n+1}

Figure3.Cycle-to-CycleJitter

FBIN

t₍

)

n+1

n=N

t₍

∑

) n

(N is a large number of samples)

Figure 4. Static Phase Offset

Yx, FBOUT

t_sk(o)

Figure5.OutputSkew

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

Yx, FBOUT

t_{cycle n}

Yx, FBOUT

f_O

t _jit(per)

t_{cycle n}

Figure 6. Period Jitter

Yx, FBOUT

t _n+1

t_{half period n}

half period

f_O

2*f_O

t_jit(hper)= t_{half period n}

Figure7.Half-PeriodJitter

80%

V_ID

20%

Clock Inputs

and Outputs

t_sl(i),t_sl(o)

Figure8.InputandOutputSlewRates

PS8543

06/11/01

PI6CV857L

PLLClockDriverfor

2.5V DDR-SDRAM Memory

PackagingMechanical:48-PinTSSOP

.236

.244

6.0

6.2

.488 12.4

.496 12.6

.047

1.20 Max

SEATING PLANE

0.09

0.20

.004

.008

0.45 .018

0.75 .030

.002

.006

0.05

0.15

.007

.010

.0197

BSC

.319

BSC

X.XX

DENOTES DIMENSIONS

IN MILLIMETERS

0.50

0.17

0.27

8.1

OrderingInformation

Ordering Code

Package Name

Package Type

48-pin, 240-mil wide TSSOP

PI6CV857LA

A48

Pericom Semiconductor Corporation

2380BeringDrive SanJose,CA951311-800-435-2336 Fax(408)435-1100 http://www.pericom.com

PS8543

06/11/01

PI6CV857LK [PERICOM]

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