PI7C8154NAE-33 [PERICOM]
PCI Bus Controller, CMOS, PBGA304, PLASTIC, BGA-304;
| 型号： | PI7C8154NAE-33 |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PCI Bus Controller, CMOS, PBGA304, PLASTIC, BGA-304 时钟 PC 外围集成电路 |
| 文件： | 总110页 (文件大小：809K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI7C8154
2-Port PCI-to-PCI Bridge
REVISION 1.02
2380 Bering Drive, San Jose, CA 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Email: solutions@pericom.com
Internet: http://www.pericom.com
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life
support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the manufacturer and an officer of PSC.
1) Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2) A critical component is any component of a life support device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products
or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom Semiconductor does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The
Company makes no representations that circuitry described herein is free from patent infringement or
other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
REVISION HISTORY
Date
12/5/02
2/20/03
Revision Number
1.00
1.01
Description
First Release of Data Sheet
Correct pin designation errors/omissions:
page 17: S_PAR64 should be N21
page 17: S_REQ64_L should be B19
page 17: S_ACK64_L should be C18
page 19: pin A14 should be SM66EN
page 20: pin D11 should be PMEENA_L
Added PMEENA_L pin description on page 18.
Added GPIO register descriptions
Bit [31:8] offset 64h
05/16/03
1.02
Added Signal Types for configuration register (section 12.1)
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
TABLE OF CONTENTS
1
SIGNAL DEFINITIONS ................................................................................................................... 11
1.1
1.2
1.2.1
SIGNAL TYPES .......................................................................................................................... 11
SIGNALS ..................................................................................................................................... 11
PRIMARY BUS INTERFACE SIGNALS.......................................................................... 11
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION .................................. 13
SECONDARY BUS INTERFACE SIGNALS.................................................................... 14
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION ............................ 16
CLOCK SIGNALS............................................................................................................... 17
MISCELLANEOUS SIGNALS........................................................................................... 18
GENERAL PURPOSE I/O INTERFACE SIGNALS ........................................................ 18
JTAG BOUNDARY SCAN SIGNALS ................................................................................ 18
POWER AND GROUND..................................................................................................... 19
PIN LIST ...................................................................................................................................... 19
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.3
2
SIGNAL DEFINITIONS ................................................................................................................... 22
2.1
TYPES OF TRANSACTIONS..................................................................................................... 22
SINGLE ADDRESS PHASE........................................................................................................ 23
DUAL ADDRESS PHASE........................................................................................................... 23
DEVICE SELECT (DEVSEL_L) GENERATION....................................................................... 24
DATA PHASE.............................................................................................................................. 24
WRITE TRANSACTIONS .......................................................................................................... 24
MEMORY WRITE TRANSACTIONS................................................................................ 24
MEMORY WRITE AND INVALIDATE............................................................................ 25
DELAYED WRITE TRANSACTIONS............................................................................... 26
WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 27
BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 27
FAST BACK-TO-BACK WRITE TRANSACTIONS ......................................................... 27
READ TRANSACTIONS............................................................................................................ 28
PREFETCHABLE READ TRANSACTIONS.................................................................... 28
NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 28
READ PREFECTCH ADDRESS BOUNDARIES............................................................. 28
DELAYED READ REQUESTS .......................................................................................... 29
DELAYED READ COMPLETION ON TARGET BUS .................................................... 30
DELAYED READ COMPLETION ON INITIATOR BUS................................................ 30
FAST BACK-TO-BACK READ TRANSACTION ............................................................. 31
CONFIGURATION TRANSACTIONS ...................................................................................... 31
TYPE 0 ACCESS TO PI7C8154 ......................................................................................... 32
TYPE 1 TO TYPE 0 CONVERSION.................................................................................. 32
TYPE 1 TO TYPE 1 FORWARDING................................................................................. 34
SPECIAL CYCLES ............................................................................................................. 34
64-BIT OPERATION................................................................................................................... 35
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154................................ 35
64-BIT TRANSACTIONS – ADDRESS PHASE............................................................... 36
64-BIT TRANSACTIONS – DATA PHASE....................................................................... 36
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154 ................................................... 37
64-BIT TRANSACTIONS – SUPPORT DURING RESET............................................... 37
2.2
2.3
2.4
2.5
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
2.10 TRANSACTION FLOW THROUGH.......................................................................................... 38
2.11 TRANSACTION TERMINATION.............................................................................................. 38
2.11.1 MASTER TERMINATION INITIATED BY PI7C8154.................................................... 39
2.11.2 MASTER ABORT RECEIVED BY PI7C8154................................................................... 39
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
2.11.3 TARGET TERMINATION RECEIVED BY PI7C8154 .................................................... 40
2.11.4 TARGET TERMINATION INITIATED BY PI7C8154 .................................................... 42
3
ADDRESS DECODING..................................................................................................................... 44
3.1
3.2
3.2.1
3.2.2
ADDRESS RANGES ................................................................................................................... 44
I/O ADDRESS DECODING ........................................................................................................ 45
I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 45
ISA MODE........................................................................................................................... 46
MEMORY ADDRESS DECODING............................................................................................ 46
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 47
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS................. 48
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS.............................. 49
VGA SUPPORT........................................................................................................................... 50
VGA MODE......................................................................................................................... 50
VGA SNOOP MODE........................................................................................................... 50
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
4
5
TRANSACTION ORDERING.......................................................................................................... 51
4.1
TRANSACTIONS GOVERNED BY ORDERING RULES........................................................ 51
GENERAL ORDERING GUIDELINES...................................................................................... 52
ORDERING RULES.................................................................................................................... 52
DATA SYNCHRONIZATION .................................................................................................... 54
4.2
4.3
4.4
ERROR HANDLING......................................................................................................................... 54
5.1
5.2
ADDRESS PARITY ERRORS .................................................................................................... 54
DATA PARITY ERRORS............................................................................................................ 55
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 55
READ TRANSACTIONS .................................................................................................... 56
DELAYED WRITE TRANSACTIONS............................................................................... 56
POSTED WRITE TRANSACTIONS.................................................................................. 59
DATA PARITY ERROR REPORTING SUMMARY ................................................................. 60
SYSTEM ERROR (SERR_L) REPORTING ............................................................................... 64
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
6
7
EXCLUSIVE ACCESS...................................................................................................................... 65
6.1
6.2
6.2.1
6.2.2
6.3
CONCURRENT LOCKS ............................................................................................................. 65
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154........................................................ 65
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 65
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 67
ENDING EXCLUSIVE ACCESS................................................................................................ 67
PCI BUS ARBITRATION................................................................................................................. 68
7.1
7.2
PRIMARY PCI BUS ARBITRATION......................................................................................... 68
SECONDARY PCI BUS ARBITRATION .................................................................................. 68
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 68
PREEMPTION.................................................................................................................... 70
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 70
BUS PARKING.................................................................................................................... 70
7.2.1
7.2.2
7.2.3
7.2.4
8
9
GENERAL PURPOSE I/O INTERFACE........................................................................................ 71
8.1
GPIO CONTROL REGISTERS ................................................................................................... 71
SECONDARY CLOCK CONTROL............................................................................................ 72
LIVE INSERTION ....................................................................................................................... 73
8.2
8.3
CLOCKS............................................................................................................................................. 74
9.1
PRIMARY AND SECONDARY CLOCK INPUTS .................................................................... 74
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
9.2
SECONDARY CLOCK OUTPUTS............................................................................................. 74
10
PCI POWER MANAGEMENT.................................................................................................... 74
11
RESET............................................................................................................................................. 75
11.1 PRIMARY INTERFACE RESET ................................................................................................ 75
11.2 SECONDARY INTERFACE RESET.......................................................................................... 76
11.3 CHIP RESET................................................................................................................................ 76
12
CONFIGURATION REGISTERS................................................................................................ 76
12.1 CONFIGURATION REGISTER.................................................................................................. 77
12.1.1 SIGNAL TYPES .................................................................................................................. 77
12.1.2 VENDOR ID REGISTER – OFFSET 00h......................................................................... 78
12.1.3 DEVICE ID REGISTER – OFFSET 00h .......................................................................... 78
12.1.4 COMMAND REGISTER – OFFSET 04h.......................................................................... 78
12.1.5 STATUS REGISTER – OFFSET 04h................................................................................ 79
12.1.6 REVISION ID REGISTER – OFFSET 08h ...................................................................... 80
12.1.7 CLASS CODE REGISTER – OFFSET 08h....................................................................... 80
12.1.8 CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 80
12.1.9 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 80
12.1.10
12.1.11
12.1.12
12.1.13
12.1.14
12.1.15
12.1.16
12.1.17
12.1.18
12.1.19
12.1.20
12.1.21
12.1.22
HEADER TYPE REGISTER – OFFSET 0Ch............................................................... 80
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 81
SECONDARY BUS NUMBER REGISTER – OFFSET 18h........................................ 81
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 81
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 81
I/O BASE ADDRESS REGISTER – OFFSET 1Ch ...................................................... 81
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch..................................................... 81
SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 82
MEMORY BASE ADDRESS REGISTER – OFFSET 20h........................................... 82
MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 83
PEFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h............. 83
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h......... 83
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
OFFSET 28h ....................................................................................................................................... 84
12.1.23 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
OFFSET 2Ch....................................................................................................................................... 84
12.1.24
12.1.25
12.1.26
12.1.27
12.1.28
12.1.29
12.1.30
12.1.31
12.1.32
12.1.33
4Ch
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.......................... 84
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 84
ECP POINTER REGISTER – OFFSET 34h................................................................. 84
INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 85
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 85
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 85
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 87
ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 88
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 88
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
.......................................................................................................................................... 89
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 89
GPIO DATA REGISTER – OFFSET 64h...................................................................... 90
GPIO CONTROL REGISTER – OFFSET 64h ............................................................. 90
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h................................. 91
P_SERR_L STATUS REGISTER – OFFSET 68h........................................................ 92
PORT OPTION REGISTER – OFFSET 74h ................................................................ 93
RETRY COUNTER REGISTER – OFFSET 78h.......................................................... 94
12.1.34
12.1.35
12.1.36
12.1.37
12.1.38
12.1.39
12.1.40
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.41
12.1.42
12.1.43
12.1.44
12.1.45
12.1.46
12.1.47
12.1.48
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 94
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 82h ............................... 94
CAPABILITY ID REGISTER – OFFSET DCh............................................................. 94
NEXT ITEM POINTER REGISTER – OFFSET DDh................................................. 94
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DEh ................. 94
POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 95
PPB SUPPORT EXTENSIONS REGISTER – OFFSET E2h...................................... 95
DATA REGISTER – OFFSET E3h................................................................................ 95
13
14
BRIDGE BEHAVIOR.................................................................................................................... 95
13.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES................................................................ 96
13.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 96
13.2.1 MASTER ABORT................................................................................................................ 96
13.2.2 PARITY AND ERROR REPORTING ................................................................................ 96
13.2.3 REPORTING PARITY ERRORS ....................................................................................... 97
13.2.4 SECONDARY IDSEL MAPPING ...................................................................................... 97
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 97
14.1 BOUNDARY SCAN ARCHITECTURE..................................................................................... 97
14.1.1 TAP PINS ............................................................................................................................ 98
14.1.2 INSTRUCTION REGISTER .............................................................................................. 98
14.2 BOUNDARY SCAN INSTRUCTION SET................................................................................. 99
14.3 TAP TEST DATA REGISTERS .................................................................................................. 99
14.4 BYPASS REGISTER ................................................................................................................. 100
14.5 BOUNDARY-SCAN REGISTER.............................................................................................. 100
14.6 TAP CONTROLLER ................................................................................................................. 100
15
ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 104
15.1 MAXIMUM RATINGS ............................................................................................................. 104
15.2 DC SPECIFICATIONS.............................................................................................................. 105
15.3 AC SPECIFICATIONS.............................................................................................................. 105
15.4 66MHZ PCI SIGNALING TIMING........................................................................................... 106
15.5 33MHZ PCI SIGNALING TIMING........................................................................................... 106
15.6 RESET TIMING......................................................................................................................... 106
15.7 GPIO TIMING (66MHZ AND 33MHZ) .................................................................................... 106
15.8 JTAG TIMING........................................................................................................................... 107
15.9 POWER CONSUMPTION......................................................................................................... 107
16
PACKAGE INFORMATION...................................................................................................... 108
16.1 304-BALL PBGA PACKAGE DIAGRAM................................................................................ 108
16.2 ORDERING INFORMATION................................................................................................... 108
LIST OF TABLES
Table 1-1 PIN LIST – 304-BALL PBGA...................................................................................................... 19
Table 2-1 PCI TRANSACTIONS ................................................................................................................. 22
Table 2-2 WRITE TRANSACTION FORWARDING ................................................................................... 24
Table 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES.......................................... 27
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES .......................................................................... 29
Table 2-5 READ TRANSACTION PREFETCHING.................................................................................... 29
Table 2-6 DEVICE NUMBER TO IDSEL S_AD PIN MAPPING ............................................................... 33
Table 2-7 DELAYED WRITE TARGET TERMINATION RESPONSE....................................................... 41
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Table 2-8 RESPONSE TO POSTED WRITE TARGET TERMINATION .................................................... 41
Table 2-9 RESPONSE TO DELAYED READ TARGET TERMINATION ................................................... 42
Table 4-1 SUMMARY OF TRANSACTION ORDERING........................................................................... 53
Table 5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT (bit 31 of Offset 04h)
...................................................................................................................................................................... 60
Table 5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT ........................ 61
Table 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (bit 24 of Offset 04h)
...................................................................................................................................................................... 61
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT.......................... 62
Table 5-5 ASSERTION OF P_PERR_L....................................................................................................... 63
Table 5-6 ASSERTION OF S_PERR_L....................................................................................................... 63
Table 5-7 ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS...................................................... 64
Table 8-1 GPIO OPERATION .................................................................................................................... 72
Table 8-2 GPIO SERIAL DATA FORMAT.................................................................................................. 72
Table 10-1 POWER MANAGEMENT TRANSITIONS ................................................................................ 75
Table 12-1 CONFIGURATION SPACE MAP............................................................................................. 77
Table 14-1 TAP PINS.................................................................................................................................. 99
Table 14-2 JTAG BOUNDARY REGISTER ORDER ................................................................................ 101
LIST OF FIGURES
Figure 7-1 SECONDARY ARBITER EXAMPLE......................................................................................... 69
Figure 14-1 TEST ACCESS PORT BLOCK DIAGRAM.............................................................................. 98
Figure 15-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS ..................................................... 105
Figure 16-1 304-BALL PBGA PACKAGE OUTLINE............................................................................... 108
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
1
SIGNAL DEFINITIONS
1.1
SIGNAL TYPES
Signal Type
Description
Input Only
I
O
P
TS
STS
Output Only
Power
Tri-State bi-directional
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
Open Drain
OD
1.2
SIGNALS
Note: Signal names that end with “_L” are active LOW.
1.2.1
PRIMARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
P_AD[31:0]
U2, U4, U1, V2, V1, V3,
W2, W1, W4, Y3, AA1,
AA3, Y4, AB3, AA4, Y5,
AB8, AA8, AC9, AB9,
AA9, AC10, AA10, Y11,
AB11, AA11, AA12, AB12,
AB13, AA13, Y13, AA14
TS
Primary Address / Data: Multiplexed address
and data bus. Address is indicated by
P_FRAME_L assertion. Write data is stable
and valid when P_IRDY_L is asserted and
read data is stable and valid when P_TRDY_L
is asserted. Data is transferred on rising clock
edges when both P_IRDY_L and P_TRDY_L
are asserted. During bus idle, PI7C8154 drives
P_AD[31:0] to a valid logic level when
P_GNT_L is asserted.
P_CBE[3:0]
P_PAR
Y2, AB4, AA7, AC11
TS
TS
Primary Command/Byte Enables:
Multiplexed command field and byte enable
field. During address phase, the initiator drives
the transaction type on these pins. After that,
the initiator drives the byte enables during data
phases. During bus idle, PI7C8154 drives
P_CBE[3:0] to a valid logic level when
P_GNT_L is asserted.
AB7
Primary Parity. P_PAR is even parity of
P_AD[31:0] and P_CBE[3:0] (i.e. an even
number of 1’s). P_PAR is valid and stable one
cycle after the address phase (indicated by
assertion of P_FRAME_L) for address parity.
For write data phases, P_PAR is valid one
clock after P_IRDY_L is asserted. For read
data phase, P_PAR is valid one clock after
P_TRDY_L is asserted. Signal P_PAR is tri-
stated one cycle after the P_AD lines are tri-
stated. During bus idle, PI7C8154 drives
P_PAR to a valid logic level when P_GNT_L
is asserted.
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
P_FRAME_L
AA5
STS
Primary FRAME (Active LOW). Driven by
the initiator of a transaction to indicate the
beginning and duration of an access. The de-
assertion of P_FRAME_L indicates the final
data phase requested by the initiator. Before
being tri-stated, it is driven to a de-asserted
state for one cycle.
P_IRDY_L
AC5
AB5
AA6
STS
STS
STS
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability
to complete current data phase on the primary
side. Once asserted in a data phase, it is not
de-asserted until the end of the data phase.
Before tri-stated, it is driven to a de-asserted
state for one cycle.
Primary TRDY (Active LOW). Driven by
the target of a transaction to indicate its ability
to complete current data phase on the primary
side. Once asserted in a data phase, it is not
de-asserted until the end of the data phase.
Before tri-stated,
P_TRDY_L
P_DEVSEL_L
it is driven to a de-asserted state for one cycle.
Primary Device Select (Active LOW).
Asserted by the target indicating that the
device is accepting the transaction. As a
master, PI7C8154 waits for the assertion of
this signal within 5 cycles of P_FRAME_L
assertion; otherwise, terminate with master
abort. Before tri-stated, it is driven to a
de-asserted state for one cycle.
P_STOP_L
P_LOCK_L
AC6
AB6
STS
I
Primary STOP (Active LOW). Asserted by
the target indicating that the target is
requesting the initiator to stop the current
transaction. Before tri-stated, it is driven to a
de-asserted state for one cycle.
Primary LOCK (Active LOW). Asserted by
an initiator, one clock cycle after the first
address phase of a transaction, attempting to
perform an operation that may take more than
one PCI transaction to complete.
Primary ID Select. Used as a chip select line
for Type 0 configuration access to PI7C8154
configuration space.
Primary Parity Error (Active LOW).
Asserted when a data parity error is detected
for data received on the primary interface.
Before being tri-stated, it is driven to a de-
asserted state for one cycle.
Primary System Error (Active LOW). Can
be driven LOW by any device to indicate a
system error condition. PI7C8154 drives this
pin on:
P_IDSEL
Y1
I
P_PERR_L
AC7
STS
P_SERR_L
Y7
OD
!
!
Address parity error
Posted write data parity error on target
bus
!
!
Secondary S_SERR_L asserted
Master abort during posted write
transaction
!
Target abort during posted write
transaction
!
!
!
!
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor
for proper operation.
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
P_REQ_L
U3
TS
Primary Request (Active LOW): This is
asserted by PI7C8154 to indicate that it wants
to start a transaction on the primary bus.
PI7C8154 de-asserts this pin for at least 2 PCI
clock cycles before asserting it again.
Primary Grant (Active LOW): When
asserted, PI7C8154 can access the primary bus.
During idle and P_GNT_L asserted, PI7C8154
will drive P_AD, P_CBE, and P_PAR to valid
logic levels.
P_GNT_L
R2
I
P_RESET_L
P_M66EN
R3
I
I
Primary RESET (Active LOW): When
P_RESET_L is active, all PCI signals should
be asynchronously tri-stated.
AB10
Primary Interface 66MHz Operation.
This input is used to specify if PI7C8154 is
capable of running at 66MHz. For 66MHz
operation on the Primary bus, this signal
should be pulled “HIGH”. For 33MHz
operation on the Primary bus, this signal
should be pulled “LOW”. In this condition,
S_M66EN will be driven “LOW”, forcing the
secondary bus to run at 33MHz also.
1.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION
Name
Pin #
Type
Description
P_AD[63:32]
AA16, AB16, AA17, AB17,
Y17, AB18, AC18, AA18,
AC19, AA19, AB20, Y19,
AA20, AB21, AC21, AA21,
Y20, AA23, Y21, W20,
Y23, W21, W23, W22, V21,
V23, V22, U23, U20, U22,
T23, T22
TS
Primary Upper 32-bit Address / Data:
Multiplexed address and data bus providing an
additional 32 bits to the primary. When a dual
address command is used and P_REQ64_L is
asserted, the initiator drives the upper 32 bits
of the 64-bit address. Otherwise, these bits are
undefined and driven to valid logic levels.
During the data phase of a transaction, the
initiator drives the upper 32 bits of the 64-bit
write data, or the target drives the upper 32 bits
of the 64-bit read data, when P_REQ64_L and
P_ACK64_L are both asserted. Otherwise,
these bits are pulled up to a valid logic level
through external resistors.
P_CBE[7:4]
AA15, AB15, Y15, AC15
TS
Primary Upper 32-bit Command/Byte
Enables: Multiplexed command field and byte
enable field. During address phase, when the
dual address command is used and
P_REQ64_L is asserted, the initiator drives the
transaction type on these pins. Otherwise, these
bits are undefined, and the initiator drives a
valid logic level onto the pins. For read and
write transactions, the initiator drives these bits
for the P_AD[63:32] data bits when
P_REQ64_L and P_ACK64_L are both
asserted. When not driven, these bits are
pulled up to a valid logic level through external
resistors.
Page 13 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
P_PAR64
T21
TS
Primary Upper 32-bit Parity: P_PAR64
carries the even parity of P_AD[63:32] and
P_CBE[7:4] for both address and data phases.
P_PAR64 is driven by the initiator and is valid
1 cycle after the first address phase when a
dual address command is used and
P_REQ64_L is asserted. P_PAR64 is valid 1
clock cycle after the second address phase of a
dual address transaction when P_REQ64_L is
asserted. P_PAR64 is valid 1 cycle after valid
data is driven when both P_REQ64_L and
P_ACK64_L are asserted for that data phase.
P_PAR64 is driven by the device driving read
or write data 1 cycle after the P_AD lines are
driven. P_PAR64 is tri-stated 1 cycle after the
P_AD lines are tri-stated. Devices receive data
sample P_PAR64 as an input to check for
possible parity errors during 64-bit
transactions. When not driven, P_PAR64 is
pulled up to a valid logic level through external
resistors.
P_REQ64_L
AC14
STS
Primary 64-bit Transfer Request:
P_REQ64_L is asserted by the initiator to
indicate that the initiator is requesting a 64-bit
data transfer. P_REQ64_L has the same
timing as P_FRAME_L. When P_REQ64_L is
asserted LOW during reset, a 64-bit data path
is supported. When P_REQ64_L is HIGH
during reset, PI7C8154 drives P_AD[63:32],
P_CBE[7:4], and P_PAR64 to valid logic
levels. When deasserting, P_REQ64_L is
driven to a deasserted state for 1 cycle and then
sustained by an external pull-up resistor.
Primary 64-bit Transfer Acknowledge:
P_ACK64_L is asserted by the target only
when P_REQ64_L is asserted by the initiator
to indicate the target’s ability to transfer data
using 64 bits. P_ACK64_L has the same
timing as P_DEVSEL_L. When deasserting,
P_ACK64_L is driven to a deasserted state for
1 cycle and then is sustained by an external
pull-up resistor.
P_ACK64_L
AB14
STS
1.2.3
SECONDARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
S_AD[31:0]
C3, A3, B3, C4, A4, B4, C5,
B5, A6, A7, D7, B7, A8,
B8, C8, A9, C13, B13, A13,
D13, C14, B14, C15, B15,
C16, B16, C17, B17, D17,
A17, B18, A18
TS
Secondary Address/Data: Multiplexed
address and data bus. Address is indicated by
S_FRAME_L assertion. Write data is stable
and valid when S_IRDY_L is asserted and
read data is stable and valid when S_IRDY_L
is asserted. Data is transferred on rising clock
edges when both S_IRDY_L and S_TRDY_L
are asserted. During bus idle, PI7C8154 drives
S_AD[31:0] to a valid logic level when
S_GNT_L is asserted respectively.
Page 14 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
S_CBE[3:0]
C6, D9, C12, A15
TS
Secondary Command/Byte Enables:
Multiplexed command field and byte enable
field. During address phase, the initiator
drives the transaction type on these pins. The
initiator then drives the byte enables during
data phases. During bus idle, PI7C8154 drives
S_CBE[3:0] to a valid logic level when the
internal grant is asserted.
S_PAR
B12
TS
Secondary Parity: S_PAR is an even parity of
S_AD[31:0] and S_CBE[3:0] (i.e. an even
number of 1’s). S_PAR is valid and stable one
cycle after the address phase (indicated by
assertion of S_FRAME_L) for address parity.
For write data phases, S_PAR is valid one
clock after S_IRDY_L is asserted. For read
data phase, S_PAR is valid one clock after
S_TRDY_L is asserted. Signal S_PAR is tri-
stated one cycle after the S_AD lines are tri-
stated. During bus idle, PI7C8154 drives
S_PAR to a valid logic level when the internal
grant is asserted.
Secondary FRAME (Active LOW): Driven
by the initiator of a transaction to indicate the
beginning and duration of an access. The de-
assertion of S_FRAME_L indicates the final
data phase requested by the initiator. Before
being tri-stated, it is driven to a de-asserted
state for one cycle.
S_FRAME_L
S_IRDY_L
B9
STS
STS
STS
STS
C9
Secondary IRDY (Active LOW): Driven by
the initiator of a transaction to indicate its
ability to complete current data phase on the
secondary side. Once asserted in a data phase,
it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-
asserted state for one cycle.
S_TRDY_L
S_DEVSEL_L
A10
B10
Secondary TRDY (Active LOW): Driven by
the target of a transaction to indicate its ability
to complete current data phase on the
secondary side. Once asserted in a data phase,
it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-
asserted state for one cycle.
Secondary Device Select (Active LOW):
Asserted by the target indicating that the
device is accepting the transaction. As a
master, PI7C8154 waits for the assertion of
this signal within 5 cycles of S_FRAME_L
assertion; otherwise, terminate with master
abort. Before tri-stated, it is driven to a de-
asserted state for one cycle.
S_STOP_L
S_LOCK_L
C10
A11
STS
STS
Secondary STOP (Active LOW): Asserted
by the target indicating that the target is
requesting the initiator to stop the current
transaction. Before tri-stated, it is driven to a
de-asserted state for one cycle.
Secondary LOCK (Active LOW): Asserted
by an initiator, one clock cycle after the first
address phase of a transaction, when it is
propagating a locked transaction downstream.
PI7C8154 does not propagate locked
transactions upstream.
S_PERR_L
C11
STS
Secondary Parity Error (Active LOW):
Asserted when a data parity error is detected
for data received on the secondary interface.
Before being tri-stated, it is driven to a de-
asserted state for one cycle.
Page 15 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
S_SERR_L
B11
I
Secondary System Error (Active LOW):
Can be driven LOW by any device to indicate
a system error condition.
S_REQ_L[8:0]
S_GNT_L[8:0]
E1, E3, D2, D1, E4, D3, C2,
C1, D4
I
Secondary Request (Active LOW): This is
asserted by an external device to indicate that it
wants to start a transaction on the secondary
bus. The input is externally pulled up through
a resistor to VDD.
H1, G3, G2, G4, G1, F2, F1,
F3, E2
TS
Secondary Grant (Active LOW): PI7C8154
asserts these pins to allow external masters to
access the secondary bus. PI7C8154 de-asserts
these pins for at least 2 PCI clock cycles before
asserting it again. During idle and S_GNT_L
deasserted, PI7C8154 will drive S_AD,
S_CBE, and S_PAR.
S_RESET_L
H2
O
Secondary RESET (Active LOW): Asserted
when any of the following conditions are met:
1.
2.
Signal P_RESET_L is asserted.
Secondary reset bit in bridge control
register in configuration space is set.
The chip reset bit in the chip control
register in configuration space is set.
3.
When asserted, all control signals are tri-stated
and zeroes are driven on S_AD, S_CBE,
S_PAR, and S_PAR64.
S_M66EN
S_CFN_L
A14
K1
I/OD
Secondary Interface 66MHz Operation:
This input is used to specify if PI7C8154 is
capable of running at 66MHz on the secondary
side. When HIGH, the Secondary bus may run
at 66MHz. When LOW, the Secondary bus
may only run at 33MHz.
If P_M66EN is pulled LOW, the S_M66EN is
driven LOW.
I
Secondary Bus Central Function Control
Pin: When tied LOW, it enables the internal
arbiter. When tied HIGH, an external arbiter
must be used. S_REQ_L[0] is reconfigured to
be the secondary bus grant input, and
S_GNT_L[0] is reconfigured to be the
secondary bus request output.
1.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION
Name
Pin #
Type
Description
S_AD[63:32]
C20, A21, D20, C21, C23,
C22, D21, E20, D22, E21,
E23, F21, F23, F22, G20,
G22, G21, H23, H22, H21,
J23, J20, J22, K23, K22,
K21, L23, L21, L22, M22,
M23, M21
TS
Secondary Upper 32-bit Address/Data:
Multiplexed address and data bus. Address is
indicated by S_FRAME_L assertion. Write
data is stable and valid when S_IRDY_L is
asserted and read data is stable and valid when
S_IRDY_L is asserted. Data is transferred on
rising clock edges when both S_IRDY_L and
S_TRDY_L are asserted. During bus idle,
PI7C8154 drives S_AD to a valid logic level
when S_GNT_L is asserted respectively.
Secondary Upper 32-bit Command/Byte
Enables: Multiplexed command field and byte
enable field. During address phase, the
initiator drives the transaction type on these
pins. The initiator then drives the byte enables
during data phases. During bus idle, PI7C8154
drives S_CBE[7:0] to a valid logic level when
the internal grant is asserted.
S_CBE[7:4]
A19, C19, A20, D19
TS
Page 16 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
S_PAR64
N21
TS
Secondary Upper 32-bit Parity: S_PAR64
carries the even parity of S_AD[63:32] and
S_CBE[7:4] for both address and data phases.
S_PAR64 is driven by the initiator and is valid
1 cycle after the first address phase when a
dual address command is used and
S_REQ64_L is asserted. S_PAR64 is valid 1
clock cycle after the second address phase of a
dual address transaction when S_REQ64_L is
asserted. S_PAR64 is valid 1 cycle after valid
data is driven when both S_REQ64_L and
S_ACK64_L are asserted for that data phase.
S_PAR64 is driven by the device driving read
or write data 1 cycle after the S_AD lines are
driven. S_PAR64 is tri-stated 1 cycle after the
S_AD lines are tri-stated. Devices receive data
sample S_PAR64 as an input to check for
possible parity errors during 64-bit
transactions. When not driven, S_PAR64 is
pulled up to a valid logic level through external
resistors.
S_REQ64_L
B19
STS
Secondary 64-bit Transfer Request:
S_REQ64_L is asserted by the initiator to
indicate that the initiator is requesting a 64-bit
data transfer. S_REQ64_L has the same
timing as S_FRAME_L. When S_REQ64_L is
asserted LOW during reset, a 64-bit data path
is supported. When S_REQ64_L is HIGH
during reset, PI7C8154 drives S_AD[63:32],
S_CBE[7:4], and S_PAR64 to valid logic
levels. When deasserting, S_REQ64_L is
driven to a deasserted state for 1 cycle and then
sustained by an external pull-up resistor.
Secondary 64-bit Transfer Acknowledge:
S_ACK64_L is asserted by the target only
when S_REQ64_L is asserted by the initiator
to indicate the target’s ability to transfer data
using 64 bits. S_ACK64_L has the same
timing as S_DEVSEL_L. When deasserting,
S_ACK64_L is driven to a deasserted state for
1 cycle and then is sustained by an external
pull-up resistor.
S_ACK64_L
C18
STS
1.2.5
CLOCK SIGNALS
Name
Pin #
Type
Description
P_CLK
T3
I
Primary Clock Input: Provides timing for all
transactions on the primary interface.
Secondary Clock Input: Provides timing for
all transactions on the secondary interface.
Secondary Clock Output: Provides secondary
clocks phase synchronous with the P_CLK.
S_CLKIN
J4
I
S_CLKOUT[9:0]
P1, P2, P3, N1, N3, M2,
M1, M3, L3, L2
O
When these clocks are used, one of the clock
outputs must be fed back to S_CLKIN. Unused
outputs may be disabled by:
1. Writing the secondary clock disable bits in
the configuration space
2. Using the serial disable mask using the
GPIO pins and MSK_IN
3. Terminating them electrically.
Page 17 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
1.2.6
MISCELLANEOUS SIGNALS
Name
Pin #
Type
Description
MSK_IN
R21
I
Secondary Clock Disable Serial Input: This
pin is used by PI7C8154 to disable secondary
clock outputs. The serial stream is received by
MSK_IN, starting when P_RESET is detected
deasserted and S_RESET_L is detected as
being asserted. The serial data is used for
selectively disabling secondary clock outputs
and is shifted into the secondary clock control
configuration register. This pin can be tied
LOW to enable all secondary clock outputs or
tied HIGH to drive all the secondary clock
outputs HIGH.
P_VIO
S_VIO
R20
N22
I
I
Primary I/O Voltage: This pin is used to
determine either 3.3V or 5V signaling on the
primary bus. P_VIO must be tied to 3.3V only
when all devices on the primary bus use 3.3V
signaling. Otherwise, P_VIO is tied to 5V.
Secondary I/O Voltage: This pin is used to
determine either 3.3V or 5V signaling on the
secondary bus. S_VIO must be tied to 3.3V
only when all devices on the secondary bus use
3.3V signaling. Otherwise, S_VIO is tied to
5V.
Bus/Power Clock Control Management Pin:
When this pin is tied HIGH and the PI7C8154
is placed in the D2 or D3HOT power state, it
enables the PI7C8154 to place the secondary
bus in the B2 power state. The secondary
clocks are disabled and driven to 0. When this
pin is tied LOW, there is no effect on the
secondary bus clocks when the PI7C8154
enters the D2 or D3HOT power state.
66MHz Configuration: This pin indicates if
the PI7C8154 is capable of running at 66MHz
operation. Tie HIGH to set bit [21] of offset
04h of the status register.
Power Management Enable Support: This
pin sets bits [31:27] offset DEh of the Power
Management Capabilities Register. When tied
LOW, bits [31:27] offset DEh are set to 11111
to indicate that the secondary devices are
capable of asserting PME_L. When this pin is
tied HIGH, bits [31:27] offset DEh are set to
00000 to indicate that PI7C8154 does not
support the PME_L pin.
BPCCE
R4
I
CONFIG66
R22
D11
I
I
PMEENA_L
1.2.7
1.2.8
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name
Pin #
Type
Description
GPIO[3:0]
K2, K3, L4, L1
TS
General Purpose I/O Data Pins: The 4
general-purpose signals are programmable as
either input-only or bi-directional signals by
writing the GPIO output enable control register
in the configuration space.
JTAG BOUNDARY SCAN SIGNALS
Name
Pin #
Type
Description
Page 18 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Name
Pin #
Type
Description
TCK
N20
I
Test Clock. Used to clock state information
and data into and out of the PI7C8154 during
boundary scan.
TMS
TDO
P21
P22
I
Test Mode Select. Used to control the state of
the Test Access Port controller.
Test Data Output. Used as the serial output
for the test instructions and data from the test
logic.
Test Data Input. Serial input for the JTAG
instructions and test data.
Test Reset. Active LOW signal to reset the
Test Access Port (TAP) controller into an
initialized state.
O
TDI
P23
I
I
TRST_L
N23
1.2.9
POWER AND GROUND
Name
Pin #
Type
Description
VDD
A2, A22, B1, B6, B20, B23,
D5, D6, D10, D11, D14,
D15, D18, E22, H4, H20,
J1, J3, J21, M4, M20, N4,
R1, R23, T1, T4, T20, W3,
Y6, Y10, Y14, Y18, Y22,
AB1, AB19, AB23, AC2,
AC3, AC8, AC12, AC16,
AC22
P
Power: +3.3V Digital power.
VSS
A1, A5, A12, A16, A23, B2,
B21, B22, C7, D8, D12,
D16, D23, F4, F20, G23,
H3, J2, K4, K20, L20, N2,
P4, P20, T2, U21, V4, V20,
Y8, Y9, Y12, Y16, AA2,
AA22, AB2, AB22, AC1,
AC4, AC13, AC17, AC20,
AC23
P
Ground: Digital ground.
1.3
PIN LIST
Table 1-1 PIN LIST – 304-BALL PBGA
BALL
LOCATION
A1
PIN NAME
TYPE
BALL
PIN NAME
TYPE
LOCATION
A2
VSS
S_AD[30]
VSS
P
TS
P
VDD
P
A3
A4
S_AD[27]
S_AD[23]
S_AD[19]
S_TRDY_L
VSS
TS
TS
TS
STS
P
A5
A6
A7
S_AD[22]
S_AD[16]
S_LOCK_L
S_AD13]
S_CBE[0]
S_AD[2]
S_CBE[7]
S_AD[62]
VSS
TS
TS
STS
TS
TS
TS
TS
TS
P
A8
A9
A10
A12
A14
A16
A18
A20
A22
-
A11
A13
A15
A17
A19
A21
A23
B1
SM66EN
VSS
I/OD
P
S_AD[0]
S_CBE[5]
VDD
TS
TS
P
-
-
P
VDD
P
B2
VSS
B3
S_AD[29]
S_AD[24]
S_AD[20]
S_FRAME_L
TS
TS
TS
STS
B4
S_AD[26]
VDD
TS
P
B5
B6
B7
B8
S_AD[18]
S_DEVSEL_L
TS
STS
B9
B10
Page 19 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
BALL
LOCATION
B11
B13
B15
B17
B19
B21
B23
C1
PIN NAME
TYPE
BALL
LOCATION
B12
B14
B16
B18
B20
B22
-
PIN NAME
TYPE
S_SERR_L
S_AD[14]
S_AD[8]
S_AD[4]
S_REQ64_L
VSS
I
S_PAR
S_AD[10]
S_AD[6]
S_AD[1]
VDD
VSS
-
TS
TS
TS
TS
P
TS
TS
TS
STS
P
P
VDD
P
I
TS
TS
P
-
S_REQ_L[1]
S_AD[31]
S_AD[25]
VSS
C2
S_REQ_L[2]
S_AD[28]
S_CBE[3]
S_AD[17]
S_STOP_L
S_CBE[1]
S_AD[11]
S_AD[7]
S_ACK64_L
S_AD[63]
S_AD[58]
-
I
C3
C4
TS
TS
TS
STS
TS
TS
TS
STS
TS
TS
-
C5
C6
C7
C8
C9
S_IRDY_L
S_PERR_L
S_AD[15]
S_AD[9]
S_AD[5]
S_CBE[6]
S_AD[60]
S_AD[59]
S_REQ_L[5]
S_REQ_[3]
VDD
S_AD[21]
S_CBE[2]
PMEENA_L
S_AD[12]
VDD
S_AD[3]
S_CBE[4]
S_AD[57]
VSS
S_REQ_L[8]
S_REQ_L[7]
-
STS
STS
TS
TS
TS
TS
TS
TS
I
C10
C12
C14
C16
C18
C20
C22
-
C11
C13
C15
C17
C19
C21
C23
D1
D2
S_REQ_L[6]
S_REQ_L[0]
VDD
I
D3
I
P
D4
I
D5
D6
P
D7
TS
TS
I
D8
VSS
P
D9
D10
D12
D14
D16
D18
D20
D22
-
VDD
P
D11
D13
D15
D17
D19
D21
D23
E1
VSS
P
TS
P
VDD
P
VSS
P
TS
TS
TS
P
VDD
P
S_AD[61]
S_AD[55]
-
TS
TS
-
I
E2
E4
S_GNT_L[0]
S_REQ_L[4]
S_AD[56]
VDD
TS
I
E3
-
I
-
E20
E22
-
TS
P
E21
E23
F1
S_AD[54]
S_AD[53]
S_GNT_L[2]
S_GNT_L[1]
-
TS
TS
TS
TS
-
-
-
F2
F4
S_GNT_L[3]
VSS
TS
P
F3
-
F20
F22
-
VSS
P
F21
F23
G1
S_AD[52]
S_AD[51]
S_GNT_L[4]
S_GNT_L[7]
-
TS
TS
TS
TS
-
S_AD[50]
-
TS
-
G2
G4
S_GNT_L[6]
S_GNT_L[5]
S_AD[49]
S_AD[48]
-
TS
TS
TS
TS
-
G3
-
G20
G22
-
G21
G23
H1
S_AD[47]
VSS
TS
P
S_GNT_L[8]
VSS
TS
P
H2
H4
S_RESET_L
VDD
O
H3
-
P
-
-
H20
H22
-
VDD
P
H21
H23
J1
S_AD[44]
S_AD[46]
VDD
TS
TS
P
S_AD[45]
-
TS
-
J2
J4
VSS
P
I
J3
-
VDD
P
S_CLKIN
S_AD[42]
S_AD[41]
-
-
-
J20
J22
-
TS
TS
-
J21
J23
K1
VDD
P
S_AD[43]
S_CFN_L
GPIO[2]
-
TS
I
K2
K4
GPIO[3]
VSS
TS
P
K3
TS
-
-
K20
K22
-
VSS
P
K21
K23
L1
S_AD[38]
S_AD[40]
GPIO[0]
TS
TS
TS
S_AD[39]
-
TS
-
L2
S_CLKOUT[0]
O
Page 20 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
BALL
LOCATION
L3
PIN NAME
TYPE
BALL
LOCATION
L4
PIN NAME
TYPE
S_CLKOUT[1]
-
S_AD[36]
S_AD[37]
S_CLKOUT[3]
S_CLKOUT[2]
-
S_AD[32]
S_AD[33]
S_CLKOUT[6]
S_CLKOUT[5]
-
O
-
GPIO[1]
VSS
TS
P
-
L20
L22
-
L21
L23
M1
M3
-
TS
TS
O
S_AD[35]
-
TS
-
M2
M4
M20
M22
-
S_CLKOUT[4]
VDD
O
P
O
-
VDD
P
M21
M23
N1
TS
TS
O
S_AD[34]
-
TS
-
N2
N4
VSS
P
N3
-
O
VDD
P
-
N20
N22
-
TCK
I
N21
N23
P1
S_PAR64
TRST_L
S_CLKOUT[9]
S_CLKOUT[7]
-
TS
I
S_VIO
-
I
-
O
P2
P4
S_CLKOUT[8]
VSS
O
P
P3
-
O
-
P20
P22
-
VSS
P
P21
P23
R1
TMS
I
TDO
O
-
TDI
I
-
VDD
P
R2
R4
P_GNT_L
BPCCE
P_VIO
CONFIG66
-
I
R3
-
P_RESET_L
-
I
I
-
R20
R22
-
I
R21
R23
T1
MSK_IN
VDD
I
I
P
-
VDD
P
T2
T4
VSS
P
T3
-
P_CLK
I
VDD
P
-
-
T20
T22
-
VDD
P
T21
T23
U1
P_PAR64
P_AD[33]
P_AD[29]
P_REQ_L
-
TS
TS
TS
TS
-
P_AD[32]
-
TS
-
U2
U4
P_AD[31]
P_AD[30]
P_AD[35]
P_AD[34]
-
TS
TS
TS
TS
-
U3
-
U20
U22
-
U21
U23
V1
VSS
P
P_AD[36]
P_AD[27]
P_AD[26]
-
TS
TS
TS
-
V2
V4
P_AD[28]
VSS
TS
P
V3
-
V20
V22
-
Reserved1
P_AD[37]
-
P
V21
V23
W1
W3
-
P_AD[39]
P_AD[38]
P_AD[24]
VDD
TS
TS
TS
P
TS
-
W2
W4
W20
W22
-
P_AD[25]
P_AD[23]
P_AD[44]
P_AD[40]
-
TS
TS
TS
TS
-
-
-
W21
W23
Y1
P_AD[42]
P_AD[41]
P_IDSEL
P_AD[22]
P_AD[16]
P_SERR_L
VSS
TS
TS
I
Y2
P_CBE[3]
P_AD[19]
VDD
TS
TS
P
Y3
TS
TS
OD
P
Y4
Y5
Y6
Y7
Y8
VSS
P
Y9
Y10
Y12
Y14
Y16
Y18
Y20
Y22
-
VDD
P
Y11
Y13
Y15
Y17
Y19
Y21
Y23
AA1
AA3
AA5
P_AD[8]
P_AD[1]
P_CBE[5]
P_AD[59]
P_AD[52]
P_AD[45]
P_AD[43]
P_AD[21]
P_AD[20]
P_FRAME_L
TS
TS
TS
TS
TS
TS
TS
TS
TS
STS
VSS
P
VDD
P
VSS
P
Reserved2
P_AD[47]
VDD
P
TS
P
-
-
P
AA2
AA4
AA6
VSS
P_AD[17]
P_DEVSEL_L
TS
STS
1 Connected to GROUND
2 Connected to VDD
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2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
BALL
LOCATION
AA7
PIN NAME
TYPE
BALL
LOCATION
AA8
PIN NAME
TYPE
P_CBE[1]
P_AD[11]
P_AD[6]
P_AD[2]
P_CBE[7]
P_AD[61]
P_AD[54]
P_AD[48]
P_AD[46]
VDD
P_AD[18]
P_TRDY_L
P_PAR
P_AD[12]
P_AD[7]
P_AD[3]
P_CBE[6]
P_AD[60]
VDD
P_AD[50]
VDD
VSS
VDD
P_IRDY_L
P_PERR_L
P_AD[13]
P_CBE[0]
VSS
P_CBE[4]
VSS
P_AD[55]
P_AD[49]
VSS
TS
TS
TS
TS
TS
TS
TS
TS
TS
P
TS
STS
TS
TS
TS
TS
TS
TS
P
TS
P
P
P
STS
STS
TS
TS
P
TS
P
TS
TS
P
P_AD[14]
P_AD[9]
P_AD[5]
P_AD[0]
P_AD[63]
P_AD[56]
P_AD[51]
VSS
TS
TS
TS
TS
TS
TS
TS
P
AA9
AA10
AA12
AA14
AA16
AA18
AA20
AA22
-
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB1
-
-
P
AB2
VSS
AB3
AB4
P_CBE[2]
P_LOCK_L
P_AD[15]
P_M66EN
P_AD[4]
P_ACK64_L
P_AD[62]
P_AD[58]
P_AD[53]
VSS
TS
I
AB5
AB6
AB7
AB8
TS
I
AB9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
-
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC1
TS
STS
TS
TS
TS
P
-
-
AC2
VDD
P
AC3
AC4
VSS
P
AC5
AC6
P_STOP_L
VDD
STS
P
AC7
AC8
AC9
AC10
AC12
AC14
AC16
AC18
AC20
AC22
-
P_AD[10]
VDD
TS
P
AC11
AC13
AC15
AC17
AC19
AC21
AC23
P_REQ64_L
VDD
STS
P
P_AD[57]
VSS
TS
P
VDD
-
P
-
2
SIGNAL DEFINITIONS
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C8154, and transaction termination. The PI7C8154 has two 128-byte buffers for read
data buffering of upstream and downstream transactions. Also, PI7C8154 has two 128-byte
buffers for write data buffering of upstream and downstream transactions.
2.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8154. Table 2-1
lists the command code and name of each PCI transaction. The Master and Target columns
indicate support for each transaction when PI7C8154 initiates transactions as a master, on
the primary and secondary buses, and when PI7C8154 responds to transactions as a target,
on the primary and secondary buses.
Table 2-1 PCI TRANSACTIONS
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000 Interrupt Acknowledge
N
N
N
N
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Types of Transactions
Initiates as Master
Responds as Target
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Special Cycle
Y
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
N
I/O Read
Y
Y
I/O Write
Y
Y
Reserved
Reserved
N
N
N
N
Memory Read
Memory Write
Reserved
Y
Y
Y
Y
N
N
Reserved
N
N
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
N
N
Y (Type 1 only)
Y (Type 1 only)
Y
Y
Y
Y
Y
Y
Y
Y
As indicated in Table 2-1, the following PCI commands are not supported by PI7C8154:
!
PI7C8154 never initiates a PCI transaction with a reserved command code and, as a
target, PI7C8154 ignores reserved command codes.
!
PI7C8142 does not generate interrupt acknowledge transactions. PI7C8154 ignores
interrupt acknowledge transactions as a target.
!
PI7C8154 does not respond to special cycle transactions. PI7C8154 cannot guarantee
delivery of a special cycle transaction to downstream buses because of the broadcast nature
of the special cycle command and the inability to control the transaction as a target. To
generate special cycle transactions on other PCI buses, either upstream or downstream, Type
1 configuration write must be used.
!
PI7C8154 neither generates Type 0 configuration transactions on the primary PCI bus nor
responds to Type 0 configuration transactions on the secondary PCI bus.
2.2
2.3
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the
bus command is driven on P_CBE[3:0]. PI7C8154 supports the linear increment address
mode only, which is indicated when the lowest two address bits are equal to zero. If either of
the lowest two address bits is nonzero, PI7C8154 automatically disconnects the transaction
after the first data transfer.
DUAL ADDRESS PHASE
A 64-bit address uses two address phases. The first address phase is denoted by the asserting
edge of FRAME_L. The second address phase always follows on the next clock cycle.
For a 32-bit interface, the first address phase contains dual address command code on the
CBE[3:0] lines, and the low 32 address bits on the AD[31:0] lines. The second address
phase consists of the specific memory transaction command code on the CBE[3:0] lines, and
the high 32 address bits on the AD[31:0] lines. In this way, 64-bit addressing can be
supported on 32-bit PCI buses.
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The PCI-to-PCI Bridge Architecture Specification supports the use of dual address
transactions in the prefetchable memory range only. See Section 3.3.3 for a discussion of
prefetchable address space. The PI7C8154 supports dual address transactions in both the
upstream and the downstream direction. The PI7C8154 supports a programmable 64-bit
address range in prefetchable memory for downstream forwarding of dual address
transactions. Dual address transactions falling outside the prefetchable address range are
forwarded upstream, but not downstream. Prefetching and posting are performed in a manner
consistent with the guidelines given in this document for each type of memory transaction in
prefetchable memory space.
2.4
2.5
DEVICE SELECT (DEVSEL_L) GENERATION
PI7C8154 always performs positive address decoding (medium decode) when accepting
transactions on either the primary or secondary buses. PI7C8154 never does subtractive
decode.
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data
phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted. A transfer
of data occurs only when both IRDY_L and TRDY_L are asserted during the same PCI
clock cycle. The last data phase of a transaction is indicated when FRAME_L is de-asserted
and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L are asserted.
See Section 2.11for further discussion of transaction termination.
Depending on the command type, PI7C8154 can support multiple data phase PCI
transactions. For detailed descriptions of how PI7C8154 imposes disconnect boundaries, see
Section 2.6.4for write address boundaries and Section 2.7.3 read address boundaries.
2.6
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 2-2
shows the method of forwarding used for each type of write operation.
Table 2-2 WRITE TRANSACTION FORWARDING
Type of Transaction
Memory Write
Type of Forwarding
Posted (except VGA memory)
Posted
Memory Write and Invalidate
Memory Write to VGA memory
I/O Write
Delayed
Delayed
Delayed
Type 1 Configuration Write
2.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
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When PI7C8154 determines that a memory write transaction is to be forwarded across the
bridge, PI7C8154 asserts DEVSEL_L with medium decode timing and TRDY_L in the next
cycle, provided that enough buffer space is available in the posted memory write queue for
the address and at least one DWORD of data. Under this condition, PI7C8154 accepts write
data without obtaining access to the target bus. The PI7C8154 can accept one DWORD of
write data every PCI clock cycle. That is, no target wait state is inserted. The write data is
stored in an internal posted write buffers and is subsequently delivered to the target. The
PI7C8154 continues to accept write data until one of the following events occurs:
!
!
The initiator terminates the transaction by de-asserting FRAME_L and IRDY_L.
An internal write address boundary is reached, such as a cache line boundary or an
aligned 4KB boundary, depending on the transaction type.
!
The posted write data buffer fills up.
When one of the last two events occurs, the PI7C8154 returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C8154 asserts its
request on the target bus. This can occur while PI7C8154 is still receiving data on the
initiator bus. When the grant for the target bus is received and the target bus is detected in
the idle condition, PI7C8154 asserts FRAME_L and drives the stored write address out on
the target bus. On the following cycle, PI7C8154 drives the first DWORD of write data and
continues to transfer write data until all write data corresponding to that transaction is
delivered, or until a target termination is received. As long as write data exists in the queue,
PI7C8154 can drive one DWORD of write data in each PCI clock cycle; that is, no master
wait states are inserted. If write data is flowing through PI7C8154 and the initiator stalls,
PI7C8154 will signal the last data phase for the current transaction at the target bus if the
queue empties. PI7C8154 will restart the follow-on transactions if the queue has new data.
PI7C8154 ends the transaction on the target bus when one of the following conditions is met:
!
!
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C8154 starts another
transaction to deliver the rest of the write data).
!
!
The target returns a target abort (PI7C8154 discards remaining write data).
The master latency timer expires, and PI7C8154 no longer has the target bus grant
(PI7C8154 starts another transaction to deliver remaining write data).
Section 2.11.3.2 provides detailed information about how PI7C8154 responds to target
termination during posted write transactions.
2.6.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions.
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The PI7C8154 disconnects Memory Write and Invalidate commands at aligned cache line
boundaries. The cache line size value in the cache line size register gives the number of
DWORD in a cache line.
If the value in the cache line size register does meet the memory write and invalidate
conditions, the PI7C8154 returns a target disconnect to the initiator on a cache line
boundary.
2.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write
transactions.
A delayed write transaction guarantees that the actual target response is returned back to the
initiator without holding the initiating bus in wait states. A delayed write transaction is
limited to a single DWORD data transfer.
When a write transaction is first detected on the initiator bus, and PI7C8154 forwards it as a
delayed transaction, PI7C8154 claims the access by asserting DEVSEL_L and returns a
target retry to the initiator. During the address phase, PI7C8154 samples the bus command,
address, and address parity one cycle later. After IRDY_L is asserted, PI7C8154 also
samples the first data DWORD, byte enable bits, and data parity. This information is placed
into the delayed transaction queue. The transaction is queued only if no other existing
delayed transactions have the same address and command, and if the delayed transaction
queue is not full. When the delayed write transaction moves to the head of the delayed
transaction queue and all ordering constraints with posted data are satisfied. The PI7C8154
initiates the transaction on the target bus. PI7C8154 transfers the write data to the target. If
PI7C8154 receives a target retry in response to the write transaction on the target bus, it
continues to repeat the write transaction until the data transfer is completed, or until an error
condition is encountered.
If PI7C8154 is unable to deliver write data after 224 (default) or 232 (maximum) attempts,
PI7C8154 will report a system error. PI7C8154 also asserts P_SERR_L if the primary
SERR_L enable bit is set in the command register. See Section 5.4for information on the
assertion of P_SERR_L. When the initiator repeats the same write transaction (same
command, address, byte enable bits, and data), and the completed delayed transaction is at
the head of the queue, the PI7C8154 claims the access by asserting DEVSEL_L and returns
TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator
requests multiple DWORD, PI7C8154 also asserts STOP_L in conjunction with TRDY_L to
signal a target disconnect. Note that only those bytes of write data with valid byte enable bits
are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding
byte of write data is not compared.
If the initiator repeats the write transaction before the data has been transferred to the target,
PI7C8154 returns a target retry to the initiator. PI7C8154 continues to return a target retry to
the initiator until write data is delivered to the target, or until an error condition is
encountered. When the write transaction is repeated, PI7C8154 does not make a new entry
into the delayed transaction queue. Section 2.11.3.1 provides detailed information about how
PI7C8154 responds to target termination during delayed write transactions.
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PI7C8154 implements a discard timer that starts counting when the delayed write completion
is at the head of the delayed transaction completion queue. The initial value of this timer can
be set to the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard timer expires,
PI7C8154 discards the delayed write completion from the delayed transaction completion
queue. PI7C8154 also conditionally asserts P_SERR_L (see Section 5.4).
2.6.4
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8154 imposes internal address boundaries when accepting write data. The aligned
address boundaries are used to prevent PI7C8154 from continuing a transaction over a
device address boundary and to provide an upper limit on maximum latency. PI7C78154
returns a target disconnect to the initiator when it reaches the aligned address boundaries
under conditions shown in Table 2-3.
Table 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type of Transaction
Delayed Write
Condition
Aligned Address Boundary
Disconnects after one data transfer
4KB aligned address boundary
All
Posted Memory Write
Memory write disconnect control
bit = 0(1)
Posted Memory Write
Memory write disconnect control
bit = 1(1)
Disconnects at cache line boundary
4KB aligned address boundary
Posted Memory Write and
Invalidate
Posted Memory Write and Cache line size = 1, 2, 4, 8
Invalidate
Cache line size ≠ 1, 2, 4, 8, 16
Cache line boundary if posted memory
write data FIFO does not have enough
space for the next cache line
Posted Memory Write and Cache line size = 16
Invalidate
16-DWORD aligned address boundary
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
2.6.5
2.6.6
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8154 continues to accept posted memory write transactions as long as space for at least
one DWORD of data in the posted write data buffer remains. If the posted write data buffer
fills before the initiator terminates the write transaction, PI7C8154 returns a target
disconnect to the initiator.
Delayed write transactions are accepted as long as at least one open entry in the delayed
transaction queue exists. Therefore, several posted and delayed write transactions can exist
in data buffers at the same time. See Chapter 4 for information about how multiple posted
and delayed write transactions are ordered.
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C8154 is capable of decoding and forwarding fast back-to-back write transactions. When
PI7C8154 cannot accept the second transaction because of buffer space limitations, it returns
a target retry to the initiator. The fast back-to-back enable bit must be set in the command
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register for upstream write transactions, and in the bridge control register for downstream
write transactions.
2.7
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8154. Delayed read
transactions are treated as either prefetchable or non-prefetchable. Table 2-5 shows the read
behavior, prefetchable or non-prefetchable, for each type of read operation.
2.7.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8154 performs speculative
DWORD reads, transferring data from the target before it is requested from the initiator.
This behavior allows a prefetchable read transaction to consist of multiple data transfers.
However, byte enable bits cannot be forwarded for all data phases as is done for the single
data phase of the non-prefetchable read transaction. For prefetchable read transactions,
PI7C8154 forces all byte enable bits to be on for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions,
as well as for memory read transactions that fall into prefetchable memory space.
The amount of data that is prefetched depends on the type of transaction. The amount of
prefetching may also be affected by the amount of free buffer space available in PI7C8154,
and by any read address boundaries encountered.
Prefetching should not be used for those read transactions that have side effects in the target
device, that is, control and status registers, FIFO’s, and so on. The target device’s base
address register or registers indicate if a memory address region is prefetchable.
2.7.2
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C8154 requests one and
only one DWORD from the target and disconnects the initiator after delivery of the first
DWORD of read data. Unlike prefetchable read transactions, PI7C8154 forwards the read
byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for
memory read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO, use
non-prefetchable read transactions to those locations. Accordingly, if it is important to retain
the value of the byte enable bits during the data phase, use non-prefetchable read
transactions. If these locations are mapped in memory space, use the memory read command
and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-
prefetching behavior.
2.7.3
READ PREFECTCH ADDRESS BOUNDARIES
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PI7C8154 imposes internal read address boundaries on read prefetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8154 stops pre-fetched
data, unless the target signals a target disconnect before the read prefetched boundary is
reached. When PI7C8154 finishes transferring this read data to the initiator, it returns a
target disconnect with the last data transfer, unless the initiator completes the transaction
before all pre-fetched read data is delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME_L. Section 2.7.6 describes flow-
through mode during read operations.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIESshows the read pre-fetch address
boundaries for read transactions during non-flow-through mode.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES
Type of Transaction
Address Space
Cache Line Size Prefetch Aligned Address
(CLS)
Boundary
Configuration Read
I/O Read
Memory Read
Memory Read
-
-
*
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address
boundary
*
Non-Prefetchable
Prefetchable
*
CLS = 0 or 16
Memory Read
Memory Read Line
Prefetchable
-
CLS = 1, 2, 4, 8
CLS = 0 or 16
Cache line address boundary
16-DWORD aligned address
boundary
Memory Read Line
Memory Read Multiple
Memory Read Multiple
- does not matter if it is prefetchable or non-prefetchable
* don’t care
-
-
-
CLS = 1, 2, 4, 8
CLS = 0 or 16
CLS = 1, 2, 4, 8
Cache line boundary
Queue full
Second cache line boundary
Table 2-5 READ TRANSACTION PREFETCHING
Type of Transaction
I/O Read
Configuration Read
Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Memory Read
Memory Read Line
Memory Read Multiple
Prefetching always used
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
2.7.4
DELAYED READ REQUESTS
PI7C8154 treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the
target is placed in the read data queue directed toward the initiator bus interface and is
transferred to the initiator when the initiator repeats the read transaction.
PI7C8154 accepts a delayed read request, by sampling the read address, read bus command,
and address parity. When IRDY_L is asserted, PI7C8154 then samples the byte enable bits
for the first data phase. This information is entered into the delayed transaction queue.
PI7C8154 terminates the transaction by signaling a target retry to the initiator. Upon
reception of the target retry, the initiator is required to continue to repeat the same read
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transaction until at least one data transfer is completed, or until a target response (target abort
or master abort) other than a target retry is received.
2.7.5
DELAYED READ COMPLETION ON TARGET BUS
When delayed read request reaches the head of the delayed transaction queue, PI7C8154
arbitrates for the target bus and initiates the read transaction only if all previously queued
posted write transactions have been delivered. PI7C8154 uses the exact read address and
read command captured from the initiator during the initial delayed read request to initiate
the read transaction. If the read transaction is a non-prefetchable read, PI7C8154 drives the
captured byte enable bits during the next cycle. If the transaction is a prefetchable read
transaction, it drives all byte enable bits to zero for all data phases. If PI7C8154 receives a
target retry in response to the read transaction on the target bus, it continues to repeat the
read transaction until at least one data transfer is completed, or until an error condition is
encountered. If the transaction is terminated via normal master termination or target
disconnect after at least one data transfer has been completed, PI7C8154 does not initiate any
further attempts to read more data.
If PI7C8154 is unable to obtain read data from the target after 224 (default) or 232 (maximum)
attempts, PI7C8154 will report system error. The number of attempts is programmable.
PI7C8154 also asserts P_SERR_L if the primary SERR_L enable bit is set in the command
register. See Section 5.4 for information on the assertion of P_SERR_L.
Once PI7C8154 receives DEVSEL_L and TRDY_L from the target, it transfers the data read
to the opposite direction read data queue, pointing toward the opposite inter-face, before
terminating the transaction. For example, read data in response to a downstream read
transaction initiated on the primary bus is placed in the upstream read data queue. The
PI7C8154 can accept one DWORD of read data each PCI clock cycle; that is, no master wait
states are inserted. The number of DWORD’s transferred during a delayed read transaction
matches the prefetch address boundary given in Table 2-4 READ PREFETCH ADDRESS
BOUNDARIES (assuming no disconnect is received from the target).
2.7.6
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at
the head of the read data queue, and all ordering constraints with posted write transactions
have been satisfied, the PI7C8154 transfers the data to the initiator when the initiator repeats
the transaction. For memory read transactions, PI7C8154 aliases memory read line and
memory read multiple bus commands to memory read when matching the bus command of
the transaction to the bus command in the delayed transaction queue if bit[3] of offset 74h is
set to ‘1’. PI7C8154 returns a target disconnect along with the transfer of the last DWORD
of read data to the initiator. If PI7C8154 initiator terminates the transaction before all read
data has been transferred, the remaining read data left in data buffers is discarded.
When the master repeats the transaction and starts transferring prefetchable read data from
data buffers while the read transaction on the target bus is still in progress and before a read
boundary is reached on the target bus, the read transaction starts operating in flow-through
mode. Because data is flowing through the data buffers from the target to the initiator, long
read bursts can then be sustained. In this case, the read transaction is allowed to continue
until the initiator terminates the transaction, or until an aligned 4KB address boundary is
reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8154
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reflects the stalled condition to the initiator by disconnecting the initiator with data. The
initiator may retry the transaction later if data are needed. If the initiator does not need any
more data, the initiator will not continue the disconnected transaction. In this case, PI7C8154
will start the master timeout timer. The remaining read data will be discarded after the
master timeout timer expires. To provide better latency, if there are any other pending data
for other transactions in the RDB (Read Data Buffer), the remaining read data will be
discarded even though the master timeout timer has not expired.
PI7C8154 implements a master timeout timer that starts counting when the delayed read
completion is at the head of the delayed transaction queue, and the read data is at the head of
the read data queue. The initial value of this timer is programmable through configuration
transaction. If the initiator does not repeat the read transaction and before the master timeout
timer expires (215 default), PI7C8154 discards the read transaction and read data from its
queues. PI7C8154 also conditionally asserts P_SERR_L (see Section 5.4).
PI7C8154 has the capability to post multiple delayed read requests, up to a maximum of four
in each direction. If an initiator starts a read transaction that matches the address and read
command of a read transaction that is already queued, the current read command is not
posted as it is already contained in the delayed transaction queue.
See Section 4 for a discussion of how delayed read transactions are ordered when crossing
PI7C8154.
2.7.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C8154 is capable of decoding fast back-to-back read transactions on both the primary and
secondary. Also, PI7C8154 cannot generate fast back-to-back read transactions on the
secondary or primary even though bit[23] of offset 3Ch is set to ‘1’ or bit[9] of offset 04h is
set to ‘1’.
2.8
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device
has a configuration space that is accessed by configuration commands. All registers are
accessible in configuration space only.
In addition to accepting configuration transactions for initialization of its own configuration
space, the PI7C8154 also forwards configuration transactions for device initialization in
hierarchical PCI systems, as well as for special cycle generation.
To support hierarchical PCI bus systems, two types of configuration transactions are
specified: Type 0 and Type 1.
Type 0 configuration transactions are issued when the intended target resides on the same
PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration
command and the lowest two bits of the address set to 00b.
Type 1 configuration transactions are issued when the intended target resides on another PCI
bus, or when a special cycle is to be generated on another PCI bus.
A Type 1 configuration command is identified by the configuration command and
the lowest two address bits set to 01b.
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The register number is found in both Type 0 and Type 1 formats and gives the DWORD
address of the configuration register to be accessed. The function number is also included in
both Type 0 and Type 1 formats and indicates which function of a multifunction device is to
be accessed. For single-function devices, this value is not decoded. The addresses of Type 1
configuration transaction include a 5-bit field designating the device number that identifies
the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1
transactions specifies the PCI bus to which the transaction is targeted.
2.8.1
TYPE 0 ACCESS TO PI7C8154
The configuration space is accessed by a Type 0 configuration transaction on the primary
interface. The configuration space cannot be accessed from the secondary bus. The
PI7C8154 responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when
the following conditions are met during the address phase:
!
!
!
The bus command is a configuration read or configuration write transaction.
Lowest two address bits P_AD[1:0] must be 00b.
Signal P_IDSEL must be asserted.
PI7C8154 limits all configuration access to a single DWORD data transfer and returns
target-disconnect with the first data transfer if additional data phases are requested. Because
read transactions to configuration space do not have side effects, all bytes in the requested
DWORD are returned, regardless of the value of the byte enable bits.
Type 0 configuration write and read transactions do not use data buffers; that is, these
transactions are completed immediately, regardless of the state of the data buffers. The
PI7C8154 ignores all Type 0 transactions initiated on the secondary interface.
2.8.2
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a
hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should
respond to a Type 1 configuration command. Type 1 configuration commands are used when
the configuration access is intended for a PCI device that resides on a PCI bus other than the
one where the Type 1 transaction is generated.
PI7C8154 performs a Type 1 to Type 0 translation when the Type 1 transaction
is generated on the primary bus and is intended for a device attached directly to the
secondary bus. PI7C8154 must convert the configuration command to a Type 0 format so
that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed
only in the downstream direction; that is, PI7C8154 generates a Type 0 transaction only on
the secondary bus, and never on the primary bus.
PI7C8154 responds to a Type 1 configuration transaction and translates it into a Type 0
transaction on the secondary bus when the following conditions are met during the address
phase:
!
The lowest two address bits on P_AD[1:0] are 01b.
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!
!
The bus number in address field P_AD[23:16] is equal to the value in the secondary
bus number register in configuration space.
The bus command on P_CBE[3:0] is a configuration read or configuration write
transaction.
When PI7C8154 translates the Type 1 transaction to a Type 0 transaction on the secondary
interface, it performs the following translations to the address:
!
!
Sets the lowest two address bits on S_AD[1:0] to 0.
Decodes the device number and drives the bit pattern specified in Table 2-6on
S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.
!
!
Sets S_AD[15:11] to 0.
Leaves unchanged the function number and register number fields.
PI7C8154 asserts a unique address line based on the device number. These address lines
may be used as secondary bus IDSEL signals. The mapping of the address lines depends on
the device number in the Type 1 address bits P_AD[15:11]. Table 2-6 presents the mapping
that PI7C8154 uses.
Table 2-6 DEVICE NUMBER TO IDSEL S_AD PIN MAPPING
Device Number
P_AD[15:11]
00000
Secondary IDSEL S_AD[31:16]
0000 0000 0000 0001
S_AD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
0h
1h
00001
0000 0000 0000 0010
2h
00010
0000 0000 0000 0100
3h
00011
0000 0000 0000 1000
4h
00100
0000 0000 0001 0000
5h
00101
0000 0000 0010 0000
6h
00110
0000 0000 0100 0000
7h
00111
0000 0000 1000 0000
8h
01000
0000 0001 0000 0000
9h
01001
0000 0010 0000 0000
Ah
Bh
Ch
Dh
Eh
01010
0000 0100 0000 0000
01011
0000 1000 0000 0000
01100
0001 0000 0000 0000
01101
0010 0000 0000 0000
01110
0100 0000 0000 0000
Fh
10h – 1Eh
1Fh
01111
1000 0000 0000 0000
10000 – 11110
11111
0000 0000 0000 0000
Generate special cycle (P_AD[7:2] = 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
-
PI7C8154 can assert up to 16 unique address lines to be used as IDSEL signals for
up to 16 devices on the secondary bus, for device numbers ranging from 0 through 8.
Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should
not be necessary. However, if device numbers greater than 16 are desired, some external
method of generating IDSEL lines must be used, and no upper address bits are then asserted.
The configuration transaction is still translated and passed from the primary bus to the
secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a
master abort.
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PI7C8154 forwards Type 1 to Type 0 configuration read or write transactions as delayed
transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single
32-bit data transfer.
2.8.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism
when two or more levels of PCI-to-PCI bridges are used.
When PI7C8154 detects a Type 1 configuration transaction intended for a PCI bus
downstream from the secondary bus, PI7C8154 forwards the transaction unchanged to the
secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command
or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to
Type 1 forwarding occurs when the following conditions are met during the address phase:
!
!
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
!
The bus command is a configuration read or write transaction.
PI7C8154 also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to support upstream special cycle generation. A Type 1 configuration command is
forwarded upstream when the following conditions are met:
!
!
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
!
!
!
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
The PI7C8154 forwards Type 1 to Type 1 configuration write transactions as delayed
transactions. Types 1 to Type 1 configuration write transactions are limited to a single data
transfer.
2.8.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in
hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are
not forwarded across the bridge. Special cycle transactions can be generated from Type 1
configuration write transactions in either the upstream or the down-stream direction.
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PI7C8154 initiates a special cycle on the target bus when a Type 1 configuration write
transaction is being detected on the initiating bus and the following conditions are met
during the address phase:
!
!
!
!
!
The lowest two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in
configuration space for downstream forwarding or equal to the value in the primary bus
number register in configuration space for upstream forwarding.
!
The bus command on CBE is a configuration write command.
When PI7C8154 initiates the transaction on the target interface, the bus command is changed
from configuration write to special cycle. The address and data are for-warded unchanged.
Devices that use special cycles ignore the address and decode only the bus command. The
data phase contains the special cycle message. The transaction is forwarded as a delayed
transaction, but in this case the target response is not forwarded back (because special cycles
result in a master abort). Once the transaction is completed on the target bus, through
detection of the master abort condition, PI7C8154 responds with TRDY_L to the next
attempt of the con-figuration transaction from the initiator. If more than one data transfer is
requested, PI7C8154 responds with a target disconnect operation during the first data phase.
2.9
64-BIT OPERATION
Both the primary and secondary interfaces of the PI7C8154 support 32-bit operation and 64-
bit operation. This chapter describes how to use the 64-bit operations as well as the
conditions that go along with it.
2.9.1
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154
64-bit transactions are requested by asserting P_REQ64_L on the primary and S_REQ64_L
on the secondary during the address phase. REQ64_L is asserted and deasserted during the
same cycles as FRAME_L. Under certain conditions, PI7C8154 does not use the 64-bit
extension when initiating transactions. In this case, REQ64_L is not asserted.
If REQ64_L is not asserted, the transaction is initiated as a 32-bit transaction when any of
the following conditions are met:
!
P_REQ64_L was not asserted by the primary during reset (64-bit extension not
supported on the primary) for upstream transactions only
!
!
PI7C8154 is initiating an I/O transaction
PI7C8154 is initiating a special cycle transaction
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!
!
!
!
!
!
!
PI7C8154 is initiating a configuration transaction
PI7C8154 is initiating a nonprefetchable memory read transaction
The address is not QUADWORD aligned
The address is near the top of a cache line
A single DWORD read transaction is being performed
A single or two-DWORD memory write transaction is being performed
PI7C8154 is resuming memory write transaction after a target disconnect, and
ACK64_L was not asserted by the target in the previous transaction – does not apply
when the previous target termination was a target retry
2.9.2
64-BIT TRANSACTIONS – ADDRESS PHASE
When a transaction using the primary bus 64-bit extension is a single address cycle, the
upper 32-bits of the address, AD[63:32], are assumed to be 0 and CBE[7:4] are not defined
but driven to valid logic levels during the address phase.
When a transaction using the primary bus 64-bit extension is a dual address cycle, the upper
32-bit of the address, AD[63:32], contain the upper 32-bits of the address and CBE[7:4]
contain memory bus command during both address phases. A 64-bit target then has the
opportunity to decode the entire 64-bit address and bus command after the first address
phase. A 32-bit target needs both address phases to decode the full address and bus
command.
2.9.3
64-BIT TRANSACTIONS – DATA PHASE
PI7C8154 asserts REQ64_L to indicate it is initiating a 64-bit transfer during memory write
transactions. During the data phase, PI7C8154 asserts the following:
!
!
!
!
The low 32 bits of data on AD[31:0]
The low 4 bits on CBE[3:0]
The high 32 bits of data on AD[63:32]
The high 4 bits on CBE[7:4]
Every data phase will consist of 64 bits and 8 byte enable bits when PI7C8154 detects
ACK64#_L asserted by the target at the same time it detects DEVSEL_L.
For write transactions, PI7C8154 redirects the write data that it has on the AD[63:32] bus to
AD[31:0] during the second data phase if it does not detect ACK64_L asserted at the same
time that it detects DEVSEL_L asserted. Also, the CBE[7:4] is redirected to CBE[3:0]
during the second data phase.
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For 64-bit memory write transactions that end at an odd DWORD boundary, PI7C8154
drives the byte enable bits to 1 during the last data phase. AD[63:32] are then unpredictable
but are driven to a valid logic level.
For read transactions, PI7C8154 drives 8 bits of byte enables on CBE[7:0] when it has
asserted REQ64_L. CBE[7:0] is always 0 because the only read transactions that use the 64-
bit extension are prefetchable memory reads. No special redirection is needed based on the
target’s assertion or lack of assertion of ACK64_L. When the target asserts ACK64_L at the
same time that it asserts DEVSEL_L, all read data transfers consist of 64 bits and the target
asserts PAR64, which covers AD[63:32] and CBE[7:4]. All data phase consist of 32-bit
transactions when the target does not assert ACK64_L and asserts DEVSEL_L.
2.9.4
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154
PI7C8154 does one of 2 things when it is the target of a transaction and REQ64_L is
asserted. PI7C8154 either asserts ACK64_L at the same time it asserts DEVSEL_L to
indicate its ability to perform 64-bit data transfers, or it does not use the 64-bit extension as a
target and does not assert ACK64_L. PI7C8154 does not assert ACK64_L under any of the
following conditions:
!
!
!
!
!
REQ64_L was not asserted by the initiator
PI7C8154 is responding to a nonprefetchable memory read transaction
PI7C8154 is responding to an I/O transaction
PI7C8154 is responding to a configuration transaction
Only 1 DWORD of data was read from the target
If PI7C8154 is the target of a 64-bit memory write transaction, it is able to accept 64 bits of
data during each data phase. If PI7C8154 is the target of a memory read transaction, it
delivers 64 bits of read data during each data phase and drives PAR64 corresponding to
AD[63:32] and CBE[7:4] for each data phase. If an odd number of DWORDS is read from
the target and PI7C8154 has asserted ACK64_L when returning read data to the initiator,
PI7C8154 disconnects before the last DWORD is returned. PI7C8154 may have read an odd
number of DWORD’s because of either a target disconnect or a master latency timer
expiration during 32-bit data transfers on the opposite interface.
2.9.5
64-BIT TRANSACTIONS – SUPPORT DURING RESET
PI7C8154 checks P_REQ64_L while P_RESET_L is asserted to determine whether the 64-
bit extensions are connected. If P_REQ64_L is HIGH, PI7C8154 knows that the 64-bit
extension signals are not connected so it always drives the 64-bit extension outputs to have
valid logic levels on the inputs. PI7C8154 will then treat all transactions on the primary as
32-bit. If P_REQ64_L is LOW, the 64-bit signals should be connected to pull-up resistors
on the board and PI7C8154 does not perform any input biasing. PI7C8154 can then treat
memory write and prefetchabel memory read transactions as 64-bit transactions on the
primary.
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PI7C8154 always asserts S_REQ64_L LOW during S_RESET_L to indicate that the 64-bit
extension is supported on the secondary bus. Individual pull-up resistors must always be
supplied for S_AD[63:32], S_CBE[7:4], and S_PAR64.
2.10
TRANSACTION FLOW THROUGH
Transaction flow through refers to data being removed from the read/write buffers
concurrently as data is still being written to the buffer.
For reads, flow through occurs when the initiator repeats the delayed transaction while some
read data is in the buffer, but the transaction is still ongoing on the target bus. For read flow
through to occur, there can be no other reads or writes previously posted in the same
direction.
For writes, flow through occurs when PI7C8154 is able to arbitrate for the target bus, initiate
the transaction and receive TRDY_L from the target, while receiving data from the same
transaction on the initiator bus. Flow through can only occur if the writes that were
previously posted in the same direction are completed.
2.11
TRANSACTION TERMINATION
This section describes how PI7C8154 returns transaction termination conditions back to the
initiator.
The initiator can terminate transactions with one of the following types of termination:
!
Normal termination
Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the
last data phase, and de-asserts IRDYL at the end of the last data phase in conjunction with
either TRDY_L or STOP_L assertion from the target.
!
Master abort
A master abort occurs when no target response is detected. When the initiator does not detect
a DEVSEL_L from the target within five clock cycles after asserting FRAME_L, the
initiator terminates the transaction with a master abort. If FRAME_L is still asserted, the
initiator de-asserts FRAME_L on the next cycle, and then de-asserts IRDY_L on the
following cycle. IRDY_L must be asserted in the same cycle in which FRAME_L deasserts.
If FRAME_L is already deasserted, IRDY_L can be deasserted on the next clock cycle
following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
!
Normal termination
TRDY_L and DEVSEL_L asserted in conjunction with FRAME_L deasserted and IRDY_L
asserted.
!
Target retry
STOP_L and DEVSEL_L asserted with TRDY_L deasserted during the first data phase. No
data transfers occur during the transaction. This transaction must be repeated.
!
Target disconnect with data transfer
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STOP_L, DEVSEL_L and TRDY_L asserted. It signals that this is the last data transfer of
the transaction.
!
Target disconnect without data transfer
STOP_L and DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers
have been made, indicating that no more data transfers will be made during this transaction.
!
Target abort
STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will
never be able to complete this transaction. DEVSEL_L must be asserted for at least one
cycle during the transaction before the target abort is signaled.
2.11.1
MASTER TERMINATION INITIATED BY PI7C8154
PI7C8154, as an initiator, uses normal termination if DEVSEL_L is returned by target within
five clock cycles of PI7C8154’s assertion of FRAME_L on the target bus. As an initiator,
PI7C8154 terminates a transaction when the following conditions are met:
!
!
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
!
!
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data
buffers to the target.
!
!
For burst transfer, with the exception of “Memory Write and Invalidate” transactions,
the master latency timer expires and the PI7C8154’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
If PI7C8154 is delivering posted write data when it terminates the transaction because the
master latency timer expires, it initiates another transaction to deliver the remaining write
data. The address of the transaction is updated to reflect the address of the current DWORD
to be delivered.
If PI7C8154 is pre-fetching read data when it terminates the transaction because the master
latency timer expires, it does not repeat the transaction to obtain more data.
2.11.2
MASTER ABORT RECEIVED BY PI7C8154
If the initiator initiates a transaction on the target bus and does not detect DEVSEL_L
returned by the target within five clock cycles of the assertion of FRAME_L, PI7C8154
terminates the transaction with a master abort. This sets the received-master-abort bit in the
status register corresponding to the target bus.
For delayed read and write transactions, PI7C8154 is able to reflect the master abort
condition back to the initiator. When PI7C8154 detects a master abort in response to a
delayed transaction, and when the initiator repeats the transaction, PI7C8154 does not
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respond to the transaction with DEVSEL_L, which induces the master abort condition back
to the initiator. The transaction is then removed from the delayed transaction queue. When a
master abort is received in response to a posted write transaction, PI7C8154 discards the
posted write data and makes no more attempts to deliver the data. PI7C8154 sets the
received-master-abort bit in the status register when the master abort is received on the
primary bus, or it sets the received master abort bit in the secondary status register when the
master abort is received on the secondary interface. When master abort is detected in posted
write transaction with both master-abort-mode bit (bit[5] of bridge control register) and the
SERR_L enable bit (bit 8 of command register for secondary bus) are set, PI7C8154 asserts
P_SERR_L if the master-abort-on-posted-write is not set. The master-abort-on-posted-write
bit is bit 4 of the P_SERR_L event disable register (offset 64h).
Note: When PI7C8154 performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort
received bit is not set, and the Type 1 configuration transaction is disconnected after the first
data phase.
2.11.3
TARGET TERMINATION RECEIVED BY PI7C8154
When PI7C8154 initiates a transaction on the target bus and the target responds with
DEVSEL_L, the target can end the transaction with one of the following types
of termination:
!
!
!
!
Normal termination (upon de-assertion of FRAME_L)
Target retry
Target disconnect
Target abort
PI7C8154 handles these terminations in different ways, depending on the type of transaction
being performed.
2.11.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8154 initiates a delayed write transaction, the type of target termination received
from the target can be passed back to the initiator. Table 2-7 shows the response to each type
of target termination that occurs during a delayed write transaction.
PI7C8154 repeats a delayed write transaction until one of the following conditions is met:
!
!
!
PI7C8154 completes at least one data transfer.
PI7C8154 receives a master abort.
PI7C8154 receives a target abort.
PI7C8154 makes 224 (default) or 232 (maximum) write attempts resulting in a response of
target retry.
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Table 2-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination
Response
Normal
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Target Retry
Target Disconnect
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Target Abort
After the PI7C8154 makes 224 (default) attempts of the same delayed write trans-action on
the target bus, PI7C8154 asserts P_SERR_L if the SERR_L enable bit (bit 8 of command
register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8154 will report system error. See Section 5.4 for a description of system error
conditions.
2.11.3.2
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8154 initiates a posted write transaction, the target termination cannot be passed
back to the initiator. Table 2-8 shows the response to each type of target termination that
occurs during a posted write transaction.
Table 2-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
Target Termination
Normal
Repsonse
No additional action.
Target Retry
Repeating write transaction to target.
Target Disconnect
Target Abort
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Note that when a target retry or target disconnect is returned and posted write data associated
with that transaction remains in the write buffers, PI7C8154 initiates another write
transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact
same address will be driven as for the initial write trans-action attempt. If a target disconnect
is received, the address that is driven on a subsequent write transaction attempt will be
updated to reflect the address of the current DWORD. If the initial write transaction is
Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is
performed before a target disconnect is received, PI7C8154 will use the memory write
command to deliver the rest of the write data. It is because an incomplete cache line will be
transferred in the subsequent write transaction attempt.
After the PI7C8154 makes 224 (default) write transaction attempts and fails to deliver all
posted write data associated with that transaction, PI7C8154 asserts P_SERR_L if the
primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and posted-
write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of P_SERR_L
event disable register (offset 64h). PI7C8154 will report system error. See Section 5.4 for a
discussion of system error conditions.
2.11.3.3
DELAYED READ TARGET TERMINATION RESPONSE
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When PI7C8154 initiates a delayed read transaction, the abnormal target responses can be
passed back to the initiator. Other target responses depend on how much data the initiator
requests. Table 2-9 shows the response to each type of target termination that occurs during a
delayed read transaction.
PI7C8154 repeats a delayed read transaction until one of the following conditions is met:
!
!
!
PI7C8154 completes at least one data transfer.
PI7C8154 receives a master abort.
PI7C8154 receives a target abort.
PI7C8154 makes 224 (default) read attempts resulting in a response of target retry.
Table 2-9 RESPONSE TO DELAYED READ TARGET TERMINATION
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
Target Retry
Target Disconnect
If initiator requests more data than read from target, return target disconnect to
initiator.
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
Target Abort
After PI7C8154 makes 224(default) attempts of the same delayed read transaction on the
target bus, PI7C8154 asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of
command register for secondary bus) and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8154 will report system error. See Section 5.4 for a description of system error
conditions.
2.11.4
TARGET TERMINATION INITIATED BY PI7C8154
PI7C8154 can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
2.11.4.1
TARGET RETRY
PI7C8154 returns a target retry to the initiator when it cannot accept write data or return read
data as a result of internal conditions. PI7C8154 returns a target retry to an initiator when
any of the following conditions is met:
FOR DELAYED WRITE TRANSACTIONS:
!
!
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target response
has not yet been received.
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!
Target response has been received but has not progressed to the head of the return
queue.
!
!
!
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C8154, and the write transaction is not
a locked transaction.
!
!
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
FOR DELAYED READ TRANSACTIONS:
!
!
!
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a
posted write transaction precedes it.
!
!
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been
queued.
!
A locked sequence is being propagated across PI7C8154, and the read transaction is not
a locked transaction.
!
!
!
PI7C78154 is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
FOR POSTED WRITE TRANSACTIONS:
!
!
!
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C8154, and the write transaction is not
a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator must
repeat the transaction with the same address and bus command as well as the data if it is
a write transaction, within the time frame specified by the master timeout value.
Otherwise, the transaction is discarded from the buffers.
2.11.4.2
TARGET DISCONNECT
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PI7C8154 returns a target disconnect to an initiator when one of the following conditions is
met:
!
!
!
PI7C8154 hits an internal address boundary.
PI7C8154 cannot accept any more write data.
PI7C8154 has no more read data to deliver.
See Section 2.6.4 for a description of write address boundaries, and Section 2.7.3 for a
description of read address boundaries.
2.11.4.3
TARGET ABORT
PI7C8154 returns a target abort to an initiator when one of the following conditions is met:
!
!
PI7C8154 is returning a target abort from the intended target.
When PI7C8154 returns a target abort to the initiator, it sets the signaled target abort bit
in the status register corresponding to the initiator interface.
3
ADDRESS DECODING
PI7C8154 uses three address ranges that control I/O and memory transaction forwarding.
These address ranges are defined by base and limit address registers in the configuration
space. This chapter describes these address ranges, as well as ISA-mode and VGA-
addressing support.
3.1
ADDRESS RANGES
PI7C8154 uses the following address ranges that determine which I/O and memory
transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the
secondary bus to the primary bus:
!
!
!
Two 32-bit I/O address ranges
Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
Two 32-bit prefetchable memory address ranges
Transactions falling within these ranges are forwarded downstream from the primary PCI
bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded
upstream from the secondary PCI bus to the primary PCI bus.
No address translation is required in PI7C8154. The addresses that are not marked for
downstream are always forwarded upstream.
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3.2
I/O ADDRESS DECODING
PI7C8154 uses the following mechanisms that are defined in the configuration space to
specify the I/O address space for downstream and upstream forwarding:
!
!
!
!
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
This section provides information on the I/O address registers and ISA mode Section 3.4
provides information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the
command register in configuration space. All I/O transactions initiated on the primary bus
will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O
transactions, the master enable bit must be set in the command register. If the master-enable
bit is not set, PI7C8154 ignores all I/O and memory transactions initiated on the secondary
bus.
The master-enable bit also allows upstream forwarding of memory transactions
if it is set.
CAUTION
If any configuration state affecting I/O transaction forwarding is changed by a configuration
write operation on the primary bus at the same time that I/O transactions are ongoing on the
secondary bus, PI7C8154 response to the secondary bus I/O transactions is not predictable.
Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA
snoop bit before setting I/O enable and master enable bits, and change them subsequently
only when the primary and secondary PCI buses are idle.
3.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
PI7C8154 implements one set of I/O base and limit address registers in configuration space
that define an I/O address range per port downstream forwarding. PI7C8154 supports 32-bit
I/O addressing, which allows I/O addresses downstream of PI7C8154 to be mapped
anywhere in a 4GB I/O address space.
I/O transactions with addresses that fall inside the range defined by the I/O base and limit
registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O
transactions with addresses that fall outside this range are forwarded upstream from the
secondary PCI bus to the primary PCI bus.
The I/O range can be turned off by setting the I/O base address to a value greater than that of
the I/O limit address. When the I/O range is turned off, all I/O trans-actions are forwarded
upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum
granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in
size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-
bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base
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address. The bottom 4 bits read only as 1h to indicate that PI7C8154 supports 32-bit I/O
addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the
base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register
at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are
read/write. After primary bus reset or chip reset, the value
of the I/O base address is initialized to 0000 0000h.
The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field
at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The
bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0]
of the limit address are assumed to be FFFh, which naturally aligns the limit address to the
top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register
at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are
read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to
0000 0FFFh.
Note: The initial states of the I/O base and I/O limit address registers define an I/O range of
0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers
with their appropriate values before setting either the I/O enable bit or the master enable bit
in the command register in configuration space.
3.2.2
ISA MODE
PI7C8154 supports ISA mode by providing an ISA enable bit in the bridge control register in
configuration space. ISA mode modifies the response of PI7C8154 inside the I/O address
range in order to support mapping of I/O space in the presence of an ISA bus in the system.
This bit only affects the response of PI7C8154 when the transaction falls inside the address
range defined by the I/O base and limit address registers, and only when this address also
falls inside the first 64KB of I/O space (address bits [31:16] are 0000h).
When the ISA enable bit is set, PI7C8154 does not forward downstream any I/O transactions
addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing
the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are
forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded
as defined by the address range defined by the I/O base and limit registers.
Accordingly, if the ISA enable bit is set, PI7C8154 forwards upstream those I/O transactions
addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space.
The master enable bit in the command configuration register must also be set to enable
upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded
upstream only if they fall outside the I/O address range.
When the ISA enable bit is set, devices downstream of PI7C8154 can have I/O space
mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere
in I/O space above the 64KB boundary.
3.3
MEMORY ADDRESS DECODING
PI7C8154 has three mechanisms for defining memory address ranges for forwarding of
memory transactions:
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!
!
!
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
This section describes the first two mechanisms. Section 3.4.1 describes VGA mode. To
enable downstream forwarding of memory transactions, the memory enable bit must be set
in the command register in configuration space. To enable upstream forwarding of memory
transactions, the master-enable bit must be set in the command register. The master-enable
bit also allows upstream forwarding of I/O transactions if it is set.
CAUTION
If any configuration state affecting memory transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that memory transactions
are ongoing on the secondary bus, response to the secondary bus memory transactions is not
predictable. Configure the memory-mapped I/O base and limit address registers,
prefetchable memory base and limit address registers, and VGA mode bit before setting the
memory enable and master enable bits, and change them subsequently only when the
primary and secondary PCI buses are idle.
3.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that
cannot automatically be pre-fetched but that can be conditionally pre-fetched based on
command type should be mapped into this space. Read transactions to non-prefetchable
space may exhibit side effects; this space may have non-memory-like behavior. PI7C8154
prefetches in this space only if the memory read line or memory read multiple commands are
used; transactions using the memory read command are limited to a single data transfer.
The memory-mapped I/O base address and memory-mapped I/O limit address registers
define an address range that PI7C8154 uses to determine when to forward memory
commands. PI7C8154 forwards a memory transaction from the primary to the secondary
interface if the transaction address falls within the memory-mapped I/O address range.
PI7C8154 ignores memory transactions initiated on the secondary interface that fall into this
address range. Any transactions that fall outside this address range are ignored on the
primary interface and are forwarded upstream from the secondary interface (provided that
they do not fall into the prefetchable memory range or are not forwarded downstream by the
VGA mechanism).
The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge
Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O
space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The
maximum memory-mapped I/O address range is 4GB.
The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base
address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit
address register at offset 22h. The top 12 bits of each of these registers correspond to bits
[31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the
memory-mapped I/O base address are assumed to be 0 0000h, which results in a natural
alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address
are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block.
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Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The
initial state of the memory-mapped I/O limit address register is 000F FFFFh. Note that the
initial states of these registers define a memory-mapped I/O range at the bottom 1MB block
of memory. Write these registers with their appropriate values before setting either the
memory enable bit or the master enable bit in the command register in configuration space.
To turn off the memory-mapped I/O address range, write the memory-mapped I/O base
address register with a value greater than that of the memory-mapped I/O limit address
register.
3.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS
REGISTERS
Locations accessed in the prefetchable memory address range must have true memory-like
behavior and must not exhibit side effects when read. This means that extra reads to a
prefetchable memory location must have no side effects. PI7C8154 pre-fetches for all types
of memory read commands in this address space.
The prefetchable memory base address and prefetchable memory limit address registers
define an address range that PI7C8154 uses to determine when to forward memory
commands. PI7C8154 forwards a memory transaction from the primary to the secondary
interface if the transaction address falls within the prefetchable memory address range.
PI7C8154 ignores memory transactions initiated on the secondary interface that fall into this
address range. PI7C8154 does not respond to any transactions that fall outside this address
range on the primary interface and forwards those transactions upstream from the secondary
interface (provided that they do not fall into the memory-mapped I/O range or
are not forwarded by the VGA mechanism).
The prefetchable memory range supports 64-bit addressing and provides additional registers
to define the upper 32 bits of the memory address range, the prefetchable memory base
address upper 32 bits register, and the prefetchable memory limit address upper 32 bits
register. For address comparison, a single address cycle (32-bit address) prefetchable
memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the
address are equal to 0. This upper 32-bit value of 0 is compared to the prefetchable memory
base address upper 32 bits register and the prefetchable memory limit address upper 32 bits
register. The prefetchable memory base address upper 32 bits register must be 0 to pass any
single address cycle transactions downstream.
Prefetchable memory address range has a granularity and alignment of 1MB. Maximum
memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory
address range is defined by a 16-bit prefetchable memory base address register at
configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset
26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory
address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable
memory base address are assumed to be 0 0000h, which results in a natural alignment to a
1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to
be FFFFFh, which results in an alignment to the top of a 1MB block.
Note: The initial state of the prefetchable memory base address register is 0000 0000h. The
initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the
initial states of these registers define a prefetchable memory range at the bottom 1MB block
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of memory. Write these registers with their appropriate values before setting either the
memory enable bit or the master enable bit in the command register in configuration space.
To turn off the prefetchable memory address range, write the prefetchable memory base
address register with a value greater than that of the prefetchable memory limit address
register. The entire base value must be greater than the entire limit value, meaning that the
upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits
registers can both be set to the same value, while the lower base register is set greater than
the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32-
bit limit.
3.3.3
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS
PI7C8154 supports 64-bit memory address decoding for forwarding of dual address memory
transactions. Dual address cycle is used for 64-bit addressing. The first address phase of the
dual address cycle contains the low 32 bits of the address and the second address phase
contains the high 32 bits. The high 32 bits must never be 0 during a dual address cycle.
The prefetchable memory address range is defined by implementing the prefetchable
memory base address upper 32 bits register and the prefetchable memory limit address upper
32 bits register. The prefetchable address space can be defined as either:
!
!
!
Residing entirely in the first 4GB of memory
Residing entirely above the first 4GB of memory
Crossing the first 4GB memory boundary
If the prefetchable memory space on the secondary bus resides entirely in the first 4GB of
memory, both upper 32 bit register must be set to 0. PI7C8154 then ignores all dual address
cycles initiated on the primary interface and forwards all dual address transactions initiated
on the secondary interface upstream.
If the prefetchable memory space on the secondary bus resides entirely above the first 4GB
of memory, both the prefetchable memory base address upper 32 bit register and the
prefetchable memory limit address upper 32 bit register must be initialized to nonzero
values. PI7C8154 ignores all single address memory transactions initiated on the primary
and forwards all single address memory transactions initiated on the secondary upstream,
unless the memory falls within the memory mapped I/O or VGA memory range. A dual
address memory transaction is forwarded downstream from the primary if it falls within the
address range defined by the prefetchable memory base address, prefetchable memory base
address upper 32 bits, prefetchable memory limit address, and prefetchable memory limit
address upper 32 bits. If the dual address cycle initiated on the secondary falls outside this
address range, it is forwarded upstream to the primary. PI7C8154 does not respond to a dual
address cycle initiated on the primary that falls outside this address range, or to a dual
address cycle initiated on the secondary that falls within the address range.
If the prefetchable memory space on the secondary bus resides on top of the 4GB boundary,
the prefetchable memory base address upper 32 bit register is set to 0 and the prefetchable
memory limit address upper 32 bit register is initialized to a nonzero value. Single address
cycle memory transactions are compared to the prefetchable memory base address register
only. A transaction initiated on the primary is forwarded downstream if the address is
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greater than or equal to the base address. A transaction initiated on the secondary is
forwarded upstream if the address is less than the base address. Dual address cycles are
compared to the prefetchable memory limit address and the prefetchable memory limit
address upper 32 bit register. If the address of the dual address cycle is less than or equal to
the limit, the transaction is forwarded downstream from the primary and is ignored on the
secondary. If the address of the dual address cycle is greater than this limit, the transaction
is ignored on the primary and is forwarded upstream from the secondary.
The prefetchable memory base address upper 32 bit register is located at offset 28h of the
configuration register and the prefetchable memory limit address upper 32 bit register is
located at offset 2Ch. Both registers are reset to 0.
3.4
VGA SUPPORT
PI7C8154 provides two modes for VGA support:
!
!
VGA mode, supporting VGA-compatible addressing
VGA snoop mode, supporting VGA palette forwarding
3.4.1
VGA MODE
When a VGA-compatible device exists downstream from PI7C8154, set the VGA mode bit
in the bridge control register in configuration space to enable VGA mode. When PI7C8154
is operating in VGA mode, it forwards downstream those transactions addressing the VGA
frame buffer memory and VGA I/O registers, regardless of the values of the base and limit
address registers. PI7C8154 ignores transactions initiated on the secondary interface
addressing these locations.
The VGA frame buffer consists of the following memory address range:
000A 0000h–000B FFFFh
Read transactions to frame buffer memory are treated as non-prefetchable. PI7C8154
requests only a single data transfer from the target, and read byte enable bits are forwarded to
the target bus.
The VGA I/O addresses are in the range of 3B0h–3BBh and 3C0h–3DFh I/O. These I/O
addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that
address bits [5:10] are not decoded and can be any value, while address bits [31:16] must be
all 0’s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.
3.4.2
VGA SNOOP MODE
PI7C8154 provides VGA snoop mode, allowing for VGA palette write transactions to be
forwarded downstream. This mode is used when a graphics device downstream from
PI7C8154 needs to snoop or respond to VGA palette write transactions. To enable the
mode, set the VGA snoop bit in the command register in configuration space. Note that
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PI7C8154 claims VGA palette write transactions by asserting DEVSEL_L in VGA snoop
mode.
When VGA snoop bit is set, PI7C8154 forwards downstream transactions within the 3C6h,
3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of
the VGA compatibility mode previously described. Again, address bits [15:10] are not
decoded, while address bits [31:16] must be equal to 0, which means that these addresses are
aliases every 1KB throughout the first 64KB of I/O space.
Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8154 behaves in the
same way as if only the VGA mode bit were set.
4
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C8154 complies with the ordering rules set
forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the bridge.
This chapter describes the ordering rules that control transaction forwarding across
PI7C8154.
4.1
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing
PI7C8154:
Posted write transactions, comprised of memory write and memory write and
invalidate transactions.
Posted write transactions complete at the source before they complete at the destination; that
is, data is written into intermediate data buffers before it reaches the target.
Delayed write request transactions, comprised of I/O write and configuration write
transactions.
Delayed write requests are terminated by target retry on the initiator bus and
are queued in the delayed transaction queue. A delayed write transaction must complete on
the target bus before it completes on the initiator bus.
Delayed write completion transactions, comprised of I/O write and configuration write
transactions.
Delayed write completion transactions complete on the target bus, and the target response is
queued in the buffers. A delayed write completion transaction proceeds
in the direction opposite that of the original delayed write request; that is, a delayed write
completion transaction proceeds from the target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and
configuration read transactions.
Delayed read requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue.
Delayed read completion transactions, comprised of all memory read, I/O read, &
configuration read transactions.
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Delayed read completion transactions complete on the target bus, and the read data is queued
in the read data buffers. A delayed read completion transaction proceeds in the direction
opposite that of the original delayed read request; that is, a delayed read completion
transaction proceeds from the target bus to the initiator bus.
PI7C8154 does not combine or merge write transactions:
!
PI7C8154 does not combine separate write transactions into a single write
transaction—this optimization is best implemented in the originating master.
!
PI7C8154 does not merge bytes on separate masked write transactions to the same
DWORD address—this optimization is also best implemented in the originating
master.
!
PI7C8154 does not collapse sequential write transactions to the same address into a
single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
4.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when
those transactions cross PI7C8154.
The following general ordering guidelines govern transactions crossing PI7C8154:
!
!
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed requests is important, the initiator should not start a second
delayed transaction until the first one has been completed. If more than one delayed
transaction is initiated, the initiator should repeat all delayed transaction requests, using
some fairness algorithm. Repeating a delayed transaction cannot be contingent on
completion of another delayed transaction. Otherwise, a deadlock can occur.
!
Write transactions flowing in one direction have no ordering requirements with respect
to write transactions flowing in the other direction. PI7C8154 can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
!
!
The acceptance of a posted memory write transaction as a target can never be contingent
on the completion of a non-locked, non-posted transaction as a master. This is true for
PI7C8154 and must also be true for other bus agents. Otherwise, a deadlock can occur.
PI7C8154 accepts posted write transactions, regardless of the state of completion of any
delayed transactions being forwarded across PI7C8154.
4.3
ORDERING RULES
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Table 4-1 shows the ordering relationships of all the transactions and refers by number to the
ordering rules that follow.
Table 4-1 SUMMARY OF TRANSACTION ORDERING
Pass
Posted
Write
Delayed
Read
Request
Yes5
Delayed
Write
Request
Yes5
Delayed Read
Completion
Delayed Write
Completion
Posted Write
No1
No2
No4
No3
Yes5
Yes
Yes
No
Yes5
Yes
Yes
No
Delayed Read Request
Delayed Write Request
Delayed Read
No
No
No
Yes
No
Yes
Completion
Delayed Write
Yes
Yes
Yes
No
No
NCotoem:pTlehtioensuperscript accompanying some of the table entries refers to any applicable
ordering rule listed in this section. Many entries are not governed by these ordering rules;
therefore, the implementation can choose whether or not the transactions pass each other.
The entries without superscripts reflect the PI7C8154’s implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is
followed by an explanation, and the ordering rules are referred to by number in Table 4-1.
These ordering rules apply to posted write transactions, delayed write and read requests, and
delayed write and read completion transactions crossing PI7C8154 in the same direction.
Note that delayed completion transactions cross PI7C8154 in the direction opposite that of
the corresponding delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they were
received on the initiator bus. The subsequent posted write transaction can be setting a flag
that covers the data in the first posted write transaction; if the second transaction were to
complete before the first transaction, a device checking the flag could subsequently consume
stale data.
2. A delayed read request traveling in the same direction as a previously queued posted
write transaction must push the posted write data ahead of it. The posted write transaction
must complete on the target bus before the delayed read request can be attempted on the
target bus. The read transaction can be to the same location as the write data, so if the read
transaction were to pass the write transaction, it would return stale data.
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data
traveling in the same direction. In this case, the read data is traveling in the same direction as
the write data, and the initiator of the read transaction is on the same side of PI7C8154 as the
target of the write transaction. The posted write transaction must complete to the target
before the read data is returned
to the initiator. The read transaction can be a reading to a status register of the initiator of the
posted write data and therefore should not complete until the write transaction is complete.
4. Delayed write requests cannot pass previously queued posted write data. For posted
memory write transactions, the delayed write transaction can set a flag that covers the data in
the posted write transaction. If the delayed write request were to complete before the earlier
posted write transaction, a device checking the flag could subsequently consume stale data.
5. Posted write transactions must be given opportunities to pass delayed read and write
requests and completions. Otherwise, deadlocks may occur when some bridges which
support delayed transactions and other bridges which do not support delayed transactions are
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being used in the same system. A fairness algorithm is used to arbitrate between the posted
write queue and the delayed transaction queue.
4.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery.
The PCI Local Bus Specification, Revision 2.2, provides the following alternative methods
for synchronizing data and interrupts:
!
!
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device
before accessing data written by the device (software).
!
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
PI7C8154 does not have a hardware mechanism to guarantee data synchronization for posted
write transactions. Therefore, all posted write transactions must be followed by a read
operation, either from the device to the location just written (or some other location along the
same path), or from the device driver to one of the device registers.
5
ERROR HANDLING
PI7C8154 checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8154 always tries to forward the existing parity
condition on one bus to the other bus, along with address and data. PI7C8154 always
attempts to be transparent when reporting errors, but this is not always possible, given the
presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8154 implements the following:
!
!
!
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
This chapter provides detailed information about how PI7C8154 handles errors.
It also describes error status reporting and error operation disabling.
5.1
ADDRESS PARITY ERRORS
PI7C8154 checks address parity for all transactions on both buses, for all address and all bus
commands. When PI7C8154 detects an address parity error on the primary interface, the
following events occur:
!
If the parity error response bit is set in the command register, PI7C8154 does not claim
the transaction with P_DEVSEL_L; this may allow the transaction to terminate in a
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master abort. If parity error response bit is not set, PI7C8154 proceeds normally and
accepts the transaction if it is directed to or across PI7C8154.
!
!
PI7C8154 sets the detected parity error bit in the status register.
PI7C8154 asserts P_SERR_L and sets signaled system error bit in the status register, if
both the following conditions are met:
!
!
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
!
!
When PI7C8154 detects an address parity error on the secondary interface, the
following events occur:
If the parity error response bit is set in the bridge control register, PI7C8154 does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate in
a master abort. If parity error response bit is not set, PI7C8154 proceeds normally and
accepts transaction if it is directed to or across PI7C8154.
!
!
PI7C8154 sets the detected parity error bit in the secondary status register.
PI7C8154 asserts P_SERR_L and sets signaled system error bit in status register, if both
of the following conditions are met:
!
!
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
5.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8154 attempts to pass the data parity condition from one
interface to the other unchanged, whenever possible, to allow the master and target devices
to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is forwarded
across PI7C8154.
5.2.1
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8154 detects a data parity error during a Type 0 configuration write transaction to
PI7C8154 configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8154 asserts P_TRDY_L
and writes the data to the configuration register. PI7C8154 also asserts P_PERR_L. If the
parity error response bit is not set, PI7C8154 does not assert P_PERR_L.
PI7C8154 sets the detected parity error bit in the status register, regardless of the state of the
parity error response bit.
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5.2.2
READ TRANSACTIONS
When PI7C8154 detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L.
For downstream transactions, when PI7C8154 detects a read data parity error on the
secondary bus, the following events occur:
!
PI7C8154 asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
!
!
PI7C8154 sets the detected parity error bit in the secondary status register.
PI7C8154 sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
!
PI7C8154 forwards the bad parity with the data back to the initiator on the primary bus.
If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
!
PI7C8154 completes the transaction normally.
For upstream transactions, when PI7C8154 detects a read data parity error on the primary
bus, the following events occur:
!
PI7C8154 asserts P_PERR_L 2 cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
!
!
PI7C8154 sets the detected parity error bit in the primary status register.
PI7C8154 sets the data parity detected bit in the primary status register, if the primary
interface parity-error-response bit is set in the command register.
!
PI7C8154 forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
!
PI7C8154 completes the transaction normally.
PI7C8154 returns to the initiator the data and parity that was received from the target. When
the initiator detects a parity error on this read data and is enabled to report it, the initiator
asserts PERR_L two cycles after the data transfer occurs. It is assumed that the initiator takes
responsibility for handling a parity error condition; therefore, when PI7C8154 detects
PERR_L asserted while returning read data to the initiator, PI7C8154 does not take any
further action and completes the transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
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When PI7C8154 detects a data parity error during a delayed write transaction, the initiator
drives data and data parity, and the target checks parity and conditionally asserts PERR_L.
For delayed write transactions, a parity error can occur at the following times:
!
!
!
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8154 completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity,
data, byte enable bits, and data parity are all captured and a target retry is returned to the
initiator. When PI7C8154 detects a parity error on the write data for the initial delayed write
request transaction, the following events occur:
!
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8154 asserts
TRDY_L to the initiator and the transaction is not queued. If multiple data phases are
requested, STOP_L is also asserted to cause a target disconnect. Two cycles after the
data transfer, PI7C8154 also asserts PERR_L.
!
!
If the parity-error-response bit is not set, PI7C8154 returns a target retry.
It queues the transaction as usual. PI7C8154 does not assert PERR_L.
In this case, the initiator repeats the transaction.
PI7C8154 sets the detected-parity-error bit in the status register corresponding to the
initiator bus, regardless of the state of the parity-error-response bit.
Note: If parity checking is turned off and data parity errors have occurred for queued or
subsequent delayed write transactions on the initiator bus, it is possible that the initiator’s re-
attempts of the write transaction may not match the original queued delayed write
information contained in the delayed transaction queue. In this case, a master timeout
condition may occur, possibly resulting in a system error (P_SERR_L assertion).
For downstream transactions, when PI7C8154 is delivering data to the target on the
secondary bus and S_PERR_L is asserted by the target, the following events occur:
!
PI7C8154 sets the secondary interface data parity detected bit in the secondary status
register, if the secondary parity error response bit is set in the bridge control register.
!
PI7C8154 captures the parity error condition to forward it back to the initiator on the
primary bus.
Similarly, for upstream transactions, when PI7C8154 is delivering data to the target on the
primary bus and P_PERR_L is asserted by the target, the following events occur:
!
PI7C8154 sets the primary interface data-parity-detected bit in the status register, if the
primary parity-error-response bit is set in the command register.
!
PI7C8154 captures the parity error condition to forward it back to the initiator on the
secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the
write transaction with the same address, command, data, and byte enable bits as the delayed
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write command that is at the head of the posted data queue. Note that the parity bit is not
compared when determining whether the transaction matches those in the delayed
transaction queues.
Two cases must be considered:
!
When parity error is detected on the initiator bus on a subsequent re-attempt of the
transaction and was not detected on the target bus
!
When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the initiator
bus and PI7C8154 has write status to return, the following events occur:
!
PI7C8154 first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if the
primary interface parity-error-response bit is set in the command register.
!
!
PI7C8154 sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8154 has write status to return, the following events occur:
!
PI7C8154 first asserts S_TRDY_L and then asserts S_PERR_L two cycles later; if the
secondary interface parity-error-response bit is set in the bridge control register (offset
3Ch).
!
!
PI7C8154 sets the secondary interface parity-error-detected bit in the secondary status
register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
!
PI7C8154 asserts P_PERR_L two cycles after the data transfer, if the following are both
true:
!
!
The parity-error-response bit is set in the command register of the primary interface.
The parity-error-response bit is set in the bridge control register of the secondary
interface.
!
PI7C8154 completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus and
the parity error condition was not originally detected on the initiator bus, the following
events occur:
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!
!
PI7C8154 asserts S_PERR_L two cycles after the data transfer, if the following are both
true:
!
!
The parity error response bit is set in the command register of the primary interface.
The parity error response bit is set in the bridge control register of the secondary
interface.
PI7C8154 completes the transaction normally.
5.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8154 responds as a target, it detects
a data parity error on the initiator (primary) bus and the following events occur:
!
PI7C8154 asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
!
!
!
PI7C8154 sets the parity error detected bit in the status register of the primary interface.
PI7C8154 captures and forwards the bad parity condition to the secondary bus.
PI7C8154 completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C8154 responds as a target, it
detects a data parity error on the initiator (secondary) bus, the following events occur:
!
PI7C8154 asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
!
PI7C8154 sets the parity error detected bit in the status register of the secondary
interface.
!
!
PI7C8154 captures and forwards the bad parity condition to the primary bus.
PI7C8154 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
!
PI7C8154 sets the data parity detected bit in the status register of secondary interface, if
the parity error response bit is set in the bridge control register of the secondary
interface.
!
PI7C8154 asserts P_SERR_L and sets the signaled system error bit in the status register,
if all the following conditions are met:
!
!
The SERR_L enable bit is set in the command register.
The posted write parity error bit of P_SERR_L event disable register is not set.
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!
The parity error response bit is set in the bridge control register of the secondary
interface.
!
!
The parity error response bit is set in the command register of the primary interface.
PI7C8154 has not detected the parity error on the primary (initiator) bus which the
parity error is not forwarded from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
!
PI7C8154 sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
!
PI7C8154 asserts P_SERR_L and sets the signaled system error bit in the status register,
if all the following conditions are met:
!
!
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the secondary
interface.
!
!
The parity error response bit is set in the command register of the primary interface.
PI7C8154 has not detected the parity error on the secondary (initiator) bus, which
the parity error is not forwarded from the secondary bus to the primary bus.
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no errors,
there is no other way to signal this information back to the initiator. If the parity error has
forwarded from the initiating bus to the target bus, P_SERR_L will not be asserted.
5.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8154 to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8154 to data parity errors according to the status bits that PI7C8154 sets and the signals
that it asserts.
Table 5-1 shows setting the detected parity error bit in the status register, corresponding to
the primary interface. This bit is set when PI7C8154 detects a parity error on the primary
interface.
Table 5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT (bit 31
of Offset 04h)
Primary Detected Transaction Type
Parity Error Bit
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
0
0
1
0
Read
Read
Read
Read
Downstream
Downstream
Upstream
Primary
Secondary
Primary
x / x
x / x
Upstream
Secondary
x / x
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Primary Detected Transaction Type
Parity Error Bit
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
1
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Primary
0
Secondary
Primary
x / x
0
x / x
0
Upstream
Secondary
Primary
x / x
1
Downstream
Downstream
Upstream
x / x
0
Secondary
Primary
x / x
0
x / x
0
Upstream
Secondary
x / x
X = don’t care
Table 5-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8154 detects a parity
error on the secondary interface.
Table 5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT
Secondary
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Detected Parity
Error Bit
Secondary Parity
Error Response
Bits
x / x
0
Read
Downstream
Downstream
Upstream
Primary
1
Read
Secondary
Primary
x / x
0
Read
x / x
0
Read
Upstream
Secondary
Primary
x / x
0
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
x / x
0
Secondary
Primary
x / x
0
x / x
1
Upstream
Secondary
Primary
x / x
0
Downstream
Downstream
Upstream
x / x
0
Secondary
Primary
x / x
0
x / x
1
Upstream
Secondary
x / x
X = don’t care
Table 5-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
!
!
PI7C8154 must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
!
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Table 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (bit 24
of Offset 04h)
Primary
Data Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Parity Bit
Secondary Parity
Error Response
Bits
x / x
0
0
1
0
Read
Read
Read
Read
Downstream
Downstream
Upstream
Primary
Secondary
Primary
x / x
1 / x
Upstream
Secondary
x / x
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Primary
Data Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Parity Bit
Secondary Parity
Error Response
Bits
x / x
0
0
1
0
0
0
1
0
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Primary
Secondary
Primary
x / x
1 / x
Upstream
Secondary
Primary
x / x
Downstream
Downstream
Upstream
x / x
Secondary
Primary
x / x
1 / x
Upstream
Secondary
x / x
X = don’t care
Table 5-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
!
!
The PI7C8154 must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
!
The S_PERR_L signal is detected asserted or a parity error is detected on the secondary
bus.
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT
Secondary
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Detected Parity
Detected Bit
Secondary Parity
Error Response
Bits
x / x
0
Read
Downstream
Downstream
Upstream
Primary
1
Read
Secondary
Primary
x / 1
0
Read
x / x
0
Read
Upstream
Secondary
Primary
x / x
0
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
x / x
1
Secondary
Primary
x / 1
0
x / x
0
Upstream
Secondary
Primary
x / x
0
Downstream
Downstream
Upstream
x / x
1
Secondary
Primary
x / 1
0
x / x
0
Upstream
Secondary
x / x
X= don’t care
Table 5-5 shows assertion of P_PERR_L. This signal is set under the following conditions:
!
PI7C8154 is either the target of a write transaction or the initiator of a read transaction
on the primary bus.
!
!
The parity-error-response bit must be set in the command register of primary interface.
PI7C8154 detects a data parity error on the primary bus or detects S_PERR_L asserted
during the completion phase of a downstream delayed write transaction on the target
(secondary) bus.
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Table 5-5 ASSERTION OF P_PERR_L
P_PERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
1 (de-asserted)
Read
Downstream
Downstream
Upstream
Primary
1
Read
Secondary
Primary
x / x
0 (asserted)
Read
1 / x
1
Read
Upstream
Secondary
Primary
x / x
0
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
1 / x
1
Secondary
Primary
x / x
1
x / x
1
Upstream
Secondary
Primary
x / x
0
Downstream
Downstream
Upstream
1 / x
02
Secondary
Primary
1 / 1
1
x / x
1
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-6 shows assertion of S_PERR_L that is set under the following conditions:
!
!
!
PI7C8154 is either the target of a write transaction or the initiator of a read transaction
on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8154 detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
Table 5-6 ASSERTION OF S_PERR_L
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
1 (de-asserted)
Read
Downstream
Downstream
Upstream
Primary
0 (asserted)
Read
Secondary
Primary
x / 1
1
Read
x / x
1
Read
Upstream
Secondary
Primary
x / x
1
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
x / x
1
Secondary
Primary
x / x
1
x / x
0
Upstream
Secondary
Primary
x / 1
1
Downstream
Downstream
Upstream
x / x
1
Secondary
Primary
x / x
02
1 / 1
0
Upstream
Secondary
x / 1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-7 shows assertion of P_SERR_L. This signal is set under the following conditions:
!
PI7C8154 has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
!
PI7C8154 did not detect the parity error as a target of the posted write transaction.
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!
!
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
The SERR_L enable bit must be set in the command register.
Table 5-7 ASSERTION OF P_SERR_L FOR DATA PARITY ERRORS
P_SERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
1 (de-asserted)
Read
Downstream
Downstream
Upstream
Primary
1
Read
Secondary
Primary
x / x
1
Read
x / x
1
Read
Upstream
Secondary
Primary
x / x
1
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
x / x
02 (asserted)
Secondary
Primary
1 / 1
03
1 / 1
1
Upstream
Secondary
Primary
x / x
1
Downstream
Downstream
Upstream
x / x
1
Secondary
Primary
x / x
1
x / x
1
Upstream
Secondary
x / x
X = don’t care
2
3
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
5.4
SYSTEM ERROR (SERR_L) REPORTING
PI7C8154 uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 5.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
!
For PI7C8154 to assert P_SERR_L for any reason, the SERR_L enable bit must be set
in the command register.
!
Whenever PI7C8154 asserts P_SERR_L, PI7C8154 must also set the signaled system
error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8154 asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8154 also
sets the received system error bit in the secondary status register.
PI7C8154 also conditionally asserts P_SERR_L for any of the following reasons:
!
!
!
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 224 (default) attempts to deliver (224 target retries
received)
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!
!
Parity error reported on target bus during posted write transaction (see previous section)
Delayed write data discarded after 224 (default) attempts to deliver (224 target retries
received)
!
!
Delayed read data cannot be transferred from target after 224 (default) attempts (224 target
retries received)
Master timeout on delayed transaction
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion for
specific events. The master timeout condition has a SERR_L enable bit for that event in the
bridge control register and therefore does not have a device-specific disable bit.
6
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK_L signal to implement exclusive access to a
target for transactions that cross PI7C8154.
6.1
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a locked
transaction crosses PI7C8154. A primary master can lock a primary target without affecting
the status of the lock on the secondary bus, and vice versa. This means that a primary master
can lock a primary target at the same time that a secondary master locks a secondary target.
6.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154
For any PCI bus, before acquiring access to the LOCK_L signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions are
met:
!
!
The PCI bus must be idle.
The LOCK_L signal must be de-asserted.
The initiator leaves the LOCK_L signal de-asserted during the address phase and asserts
LOCK_L one clock cycle later. Once a data transfer is completed from the target, the target
lock has been achieved.
6.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
Locked transactions can cross PI7C8154 only in the downstream direction, from the primary
bus to the secondary bus.
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When the target resides on another PCI bus, the master must acquire not only the lock on its
own PCI bus but also the lock on every bus between its bus and the target’s bus. When
PI7C8154 detects on the primary bus, an initial locked transaction intended for a target on
the secondary bus, PI7C8154 samples the address, transaction type, byte enable bits, and
parity, as described in Section 2.7.4. It also samples the lock signal. If there is a lock
established between 2 ports or the target bus is already locked by another master, then the
current lock cycle is retried without forward. Because a target retry is signaled to the
initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is
not yet established.
The first locked transaction must be a memory read transaction. Subsequent locked
transactions can be memory read or memory write transactions. Posted memory write
transactions that are a part of the locked transaction sequence are still posted. Memory read
transactions that are a part of the locked transaction sequence are not pre-fetched.
When the locked delayed memory read request is queued, PI7C8154 does not queue any
more transactions until the locked sequence is finished. PI7C8154 signals a target retry to all
transactions initiated subsequent to the locked read transaction that are intended for targets
on the other side of PI7C8154. PI7C8154 allows any transactions queued before the locked
transaction to complete before initiating the locked transaction.
When the locked delayed memory read request transaction moves to the head of the delayed
transaction queue, PI7C8154 initiates the transaction as a locked read transaction by de-
asserting LOCK_L on the target bus during the first address phase, and by asserting
LOCK_L one cycle later. If LOCK_L is already asserted (used by another initiator),
PI7C8154 waits to request access to the secondary bus until LOCK_L is de-asserted when
the target bus is idle. Note that the existing lock on the target bus could not have crossed
PI7C8154. Otherwise, the pending queued locked transaction would not have been queued.
When PI7C8154 is able to complete a data transfer with the locked read transaction, the lock
is established on the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the same
address, transaction type, and byte enable bits, PI7C8154 transfers the read data back to the
initiator, and the lock is then also established on the primary bus.
For PI7C8154 to recognize and respond to the initiator, the initiator’s subsequent attempts of
the read transaction must use the locked transaction sequence (de-assert LOCK_L during
address phase, and assert LOCK_L one cycle later). If the LOCK_L sequence is not used in
subsequent attempts, a master timeout condition may result. When a master timeout
condition occurs, SERR_L is conditionally asserted (see Section 5.4), the read data and
queued read transaction are discarded, and the LOCK_L signal is de-asserted on the target
bus.
Once the intended target has been locked, any subsequent locked transactions initiated on the
initiator bus that are forwarded by PI7C8154 are driven as locked transactions on the target
bus.
The first transaction to establish LOCK_L must be Memory Read. If the first transaction is
not Memory read, the following transactions behave accordingly:
!
!
Type 0 Configuration Read/Write induces master abort
Type 1 Configuration Read/Write induces master abort
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!
!
!
I/O Read induces master abort
I/O Write induces master abort
Memory Write induces master abort
When PI7C8154 receives a target abort or a master abort in response to the delayed locked
read transaction, this status is passed back to the initiator, and no locks are established on
either the target or the initiator bus. PI7C8154 resumes forwarding unlocked transactions in
both directions.
6.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C8154 ignores upstream lock and transactions. PI7C8154 will pass these transactions as
normal transactions without lock established.
6.3
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C8154 must maintain
the lock on the target bus for any subsequent locked transactions until the initiator
relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a
locked sequence. On subsequent transactions in the sequence,
the target retry has no effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. PI7C8154
does not know whether the current transaction is the last one in a sequence of locked
transactions until the initiator de-asserts the LOCK_L signal at
end of the transaction.
When the last locked transaction is a delayed transaction, PI7C8154 has already completed
the transaction on the target bus. In this example, as soon as PI7C8154 detects that the
initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state while
FRAME_L is de-asserted, PI7C8154 de-asserts the LOCK_L signal on the target bus as soon
as possible. Because of this behavior, LOCK_L may not be de-asserted until several cycles
after the last locked transaction has been completed on the target bus. As soon as PI7C8154
has de-asserted LOCK_L to indicate the end of a sequence of locked transactions, it resumes
forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C8154 de-asserts LOCK_L
on the target bus at the end of the transaction because the lock was relinquished at the end of
the write transaction on the initiator bus.
When PI7C8154 receives a target abort or a master abort in response to a locked delayed
transaction, PI7C8154 returns a target abort or a master abort when the initiator repeats the
locked transaction. The initiator must then de-assert LOCK_L at the end of the transaction.
PI7C8154 sets the appropriate status bits, flagging the abnormal target termination condition
(see Section 2.11). Normal forwarding of unlocked posted and delayed transactions is
resumed.
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When PI7C8154 receives a target abort or a master abort in response to a locked posted write
transaction, PI7C8154 cannot pass back that status to the initiator. PI7C8154 asserts
SERR_L on the initiator bus when a target abort or a master abort is received during a
locked posted write transaction, if the SERR_L enable bit is set in the command register.
Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set
in the bridge control register (see Section 5.4).
7
PCI BUS ARBITRATION
PI7C8154 must arbitrate for use of the primary bus when forwarding upstream transactions.
Also, it must arbitrate for use of the secondary bus when forwarding downstream
transactions. The arbiter for the primary bus resides external to PI7C8154, typically on the
motherboard. For the secondary PCI bus, PI7C8154 implements an internal arbiter. This
arbiter can be disabled, and an external arbiter can be used instead. This chapter describes
primary and secondary bus arbitration.
7.1
PRIMARY PCI BUS ARBITRATION
PI7C8154 implements a request output pin, P_REQ_L, and a grant input pin, P_GNT_L, for
primary PCI bus arbitration. PI7C8154 asserts P_REQ_L when forwarding transactions
upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending
transaction resides in the queues in the upstream direction, either posted write data or
delayed transaction requests, PI7C8154 keeps P_REQ_L asserted. However, if a target retry,
target disconnect, or a target abort is received in response to a transaction initiated by
PI7C8154 on the primary PCI bus, PI7C8154 de-asserts P_REQ_L for two PCI clock cycles.
For all cycles through the bridge, P_REQ_L is not asserted until the transaction request has
been completely queued. When P_GNT_L is asserted LOW by the primary bus arbiter after
PI7C8154 has asserted P_REQ_L, PI7C8154 initiates a transaction on the primary bus
during the next PCI clock cycle. When P_GNT_L is asserted to PI7C8154 when P_REQ_L
is not asserted, PI7C8154 parks P_AD, P_CBE, and P_PAR by driving them to valid logic
levels. When the primary bus is parked at PI7C8154 and PI7C8154 has a transaction to
initiate on the primary bus, PI7C8154 starts the transaction if P_GNT_L was asserted during
the previous cycle.
7.2
SECONDARY PCI BUS ARBITRATION
PI7C8154 implements an internal secondary PCI bus arbiter. This arbiter supports eight
external masters on the secondary bus in addition to PI7C8154. The internal arbiter can be
disabled, and an external arbiter can be used instead for secondary bus arbitration.
7.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL
ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN_L, must be tied
LOW. PI7C8154 has nine secondary bus request input pins, S_REQ_L[8:0], and has nine
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secondary bus output grant pins, S_GNT_L[8:0], to support external secondary bus masters.
The secondary bus request and grant signals are connected internally to the arbiter and are
not brought out to external pins when S_CFN_L is LOW.
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each
set taking care of 4 requests / grants. Each set of masters can be assigned to a high priority
group and a low priority group. The low priority group as a whole represents one entry in the
high priority group; that is, if the high priority group consists of n masters, then in at least
every n+1 transactions the highest priority is assigned to the low priority group. Priority
rotates evenly among the low priority group. Therefore, members of the high priority group
can be serviced n transactions out of n+1, while one member of the low priority group is
serviced once every n+1 transactions. Figure 7-1shows an example of an internal arbiter
where four masters, including PI7C8154, are in the high priority group, and five masters are
in the low priority group. Using this example, if all requests are always asserted, the highest
priority rotates among the masters in the following fashion (high priority members are given
in italics, low priority members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4,
B, m0, m1, m2, m5, B, m0, m1, m2, m6 and so on.
Figure 7-1 SECONDARY ARBITER EXAMPLE
m2
lpg
m1
lpg:
B:
low priority group
PI7C8154
m4
m6
m3
m7
Mx:
bus master number
m0
B
m8
m5
Each bus master, including PI7C8154, can be configured to be in either the low priority
group or the high priority group by setting the corresponding priority bit in the arbiter-
control register. The arbiter-control register is located at offset 40h. Each master has a
corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the
bit is set to 0, the master is assigned to the low priority group. If all the masters are assigned
to one group, the algorithm defaults to a straight rotating priority among all the masters.
After reset, all external masters are assigned to the low priority group, and PI7C8154 is
assigned to the high priority group. PI7C8154 receives highest priority on the target bus
every other transaction, and priority rotates evenly among the other masters.
Priorities are re-evaluated every time S_FRAME_L is asserted at the start of each new
transaction on the secondary PCI bus. From this point until the time that the next transaction
starts, the arbiter asserts the grant signal corresponding to the highest priority request that is
asserted. If a grant for a particular request is asserted, and a higher priority request
subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant
corresponding to the new higher priority request on the next PCI clock cycle. When
priorities are re-evaluated, the highest priority is assigned to the next highest priority master
relative to the master that initiated the previous transaction. The master that initiated the last
transaction now has the lowest priority in its group.
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If PI7C8154 detects that an initiator has failed to assert S_FRAME_L after 16 cycles of both
grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one
grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and
asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is
busy, that is, S_FRAME_L or S_IRDY_L is asserted, the arbiter can be de-asserted one
grant and asserted another grant during the same PCI clock cycle.
7.2.2
7.2.3
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit
31=0). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0)
clocks. If the current master occupies the bus and other masters are waiting, the current
master will be preempted by removing its grant (GNT_L) after the next master waits for the
time-to-preempt.
SECONDARY BUS ARBITRATION USING AN EXTERNAL
ARBITER
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN_L, is tied HIGH. An external arbiter must then be used.
When S_CFN_L is tied HIGH, PI7C8154 reconfigures two pins to be external request and
grant pins. The S_GNT_L[0] pin is reconfigured to be the external request pin because it’s
an output. The S_REQ_L[0] pin is reconfigured to be the external grant pin because it’s an
input. When an external arbiter is used, PI7C8154 uses the S_GNT_L[0] pin to request the
secondary bus. When the reconfigured S_REQ_L[0] pin is asserted LOW after PI7C8154
has asserted S_GNT_L[0], PI7C8154 initiates a transaction on the secondary bus one cycle
later. If grant is asserted and PI7C8154 has not asserted the request, PI7C8154 parks AD,
CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grant outputs, S_GNT_L[8:1] are driven HIGH. The unused
secondary bus request inputs, S_REQ_L[8:1], should be pulled HIGH.
7.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible for
parking the bus or assigning another device to park the bus. A device parks the bus when the
bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD[31:0]
and CBE[3:0] signals should be driven first, with the PAR signal driven one cycle later. The
AD[63:32] and CBE[7:4] are not driven and need to be pulled up to a valid logic level
through external resistors.
PI7C8154 parks the primary bus only when P_GNT_L is asserted, P_REQ_L is de-asserted,
and the primary PCI bus is idle. When P_GNT_L is de-asserted, PI7C8154 3-states the
P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C8154 is parking the
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primary PCI bus and wants to initiate a transaction on that bus, then PI7C8154 can start the
transaction on the next PCI clock cycle by asserting P_FRAME_L if P_GNT_L is still
asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last
master that used the PCI bus. That is, PI7C8154 keeps the secondary bus grant asserted to a
particular master until a new secondary bus request comes along. After reset, PI7C8154
parks the secondary bus at itself until transactions start occurring on the secondary bus.
Offset 48h, bit 1, can be set to 1 to park the secondary bus at PI7C8154. By default, offset
48h, bit 1, is set to 0. If the internal arbiter is disabled, PI7C8154 parks the secondary bus
only when the reconfigured grant signal, S_REQ_L[0], is asserted and the secondary bus is
idle.
8
GENERAL PURPOSE I/O INTERFACE
The PI7C8154 implements a 4-pin general purpose I/O interface. During normal operation,
device specific configuration registers control the GPIO interface. The GPIO interface can
be used for the following functions:
!
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit
serial stream that serves as a secondary bus clock disable mask.
!
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8154 to a
halt through hardware, permitting live insertion of option cards behind the PI7C8154.
8.1
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the
GPIO interface:
!
!
!
The GPIO output data register
The GPIO output enable control register
The GPIO input data register
These registers consist of five 4-bit fields:
!
!
!
!
!
Write-1-to-set output data field
Write-1-to-clear output data field
Write-1-to-set signal output enable control field
Write-1-to-clear signal output enable control field
Input data field
The bottom four bits of the output enable fields control whether each GPIO signal is input
only or bi-directional. Each signal is controlled independently by a bit in each output enable
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control field. If a 1 is written to the write-1-to-set field, the corresponding pin is activated as
an output. If a 1 is written to the write-1-to-clear field, the output driver is tri-stated, and the
pin is then input only. Writing zeroes to these registers has no effect. The reset for these
signals is input only.
The input data field is read only and reflects the current value of the GPIO pins. A type 0
configuration read operation to this address is used to obtain the values of these pins. All
pins can be read at any time, whether configured as input only or as bi-directional.
The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is written
to the write-1-to-set field and the pin is enabled as an output, the corresponding GPIO output
is driven HIGH. If a 1 is written to the write-1-to-clear field and the pin is enabled as an
output, the corresponding GPIO output is driven LOW. Writing zeros to these registers has
no effect. The value written to the output register will be driven only when the GPIO signal
is configured as bi-directional. A type 0 configuration write operation is used to program
these fields. The rest value for the output is 0.
8.2
SECONDARY CLOCK CONTROL
The PI7C8154 uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data
stream. This data stream is shifted into the secondary clock control register and is used for
selectively disabling secondary clock outputs.
The serial data stream is shifted in as soon as P_RESET_L is detected deasserted and the
secondary reset signal, S_RESET_L, is detected asserted. The deassertion of S_RESET_L is
delayed until the PI7C8154 completes shifting in the clock mask data, which takes 23 clock
cycles. After that, the GPIO pins can be used as general-purpose I/O pins.
An external shift register should be used to load and shift the data. The GPIO pins are used
for shift register control and serial data input. Table 8-1 shows the operation of the GPIO
pins.
Table 8-1 GPIO OPERATION
GPIO Pin
Operation
GPIO[0]
GPIO[1]
GPIO[2]
Shift register clock output at 33MHz max frequency
Not used
Shift register control
0: Load
1: Shift
Not used
GPIO[3]
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8154. The shift
register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock
outputs or tied HIGH to force all secondary clock outputs HIGH. Table 8-2 shows the
format of the serial stream.
Table 8-2 GPIO SERIAL DATA FORMAT
Bit
Description
Slot 0 PRSNT#[1:0] or device 0
Slot 1 PRSNT#[1:0] or device 1
S_CLKOUT
[1:0]
[3:2]
0
1
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Bit
Description
Slot 2 PRSNT#[1:0] or device 2
Slot 3 PRSNT#[1:0] or device 3
Device 4
S_CLKOUT
[5:4]
[7:6]
[8]
2
3
4
[9]
Device 5
5
[10]
[11]
[12]
[13]
[14]
[15]
Device 6
6
Device 7
7
Device 8
8
PI7C8154 S_CLKIN
Reserved
9
NA
NA
Reserved
The first 8 bits contain the PRSNT_L[1:0] signal values for four slots, and these bits control
the S_CLKOUT[3:0] outputs. If one or both of the PRSNT_L[1:0] signals are 0, that
indicates that a card is present in the slot and therefore the secondary clock for that slot is not
masked. If these clocks are connected to devices and not to slots, one or both of the bits
should be tied low to enable the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for one
device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1 disables
the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8154’s
S_CLKIN input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8154’s
S_CLKIN input can be rearranged from the assignment shown here. However, it is important
that the serial data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT_L pins for the slots. The next 5 bits
are tied high to disable their respective secondary clocks because those clocks are not
connected to anything. The next bit is tied LOW because that secondary clock output is
connected to the PI7C8154 S_CLKIN input. When the secondary reset signal, S_RESET_L,
is detected asserted and the primary reset signal, P_RESET_L, is detected deasserted,
PI7C8154 drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift
register. On the next cycle, PI7C8154 drives GPIO[2] HIGH to perform a shift operation.
This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the
least significant bit is shifted in last.
After the shift operation is complete, PI7C8154 tri-states the GPIO signals and deasserts
S_RESET_L. PI7C8154 then ignores MSK_IN. Control of the GPIO signal now reverts to
PI7C8154 GPIO control registers. The clock disable mask can be modified subsequently
through a configuration write command to the secondary clock control register in device-
specific configuration space.
8.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must be
set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO
output enable control register. When live insertion mode is enabled, whenever GPIO[3] is
driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are
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internally masked to 0. This means that, as a target, PI7C8154 no longer accepts any I/O or
memory transactions, on either interface. When read, the register bits still reflect the value
originally written by a configuration write command; when GPIO[3] is deasserted, the
internal enable bits return to their original value (as they appear when read from the
command register). When this mode is enabled, as a master, PI7C8154 completes any posted
write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because
PI7C8154 is not responding to any I/O or memory transactions during this time. PI7C8154
continues to accept Type 0 configuration transactions in live insertion mode. Once live
insertion mode brings PI7C8154 to a halt and queued transactions are completed, the
secondary reset bit in the bridge control register can be used to assert S_RESET_L, if
desired, to reset and tri-state secondary bus devices, and to enable any live insertion
hardware.
9
CLOCKS
This chapter provides information about the clocks.
9.1
PRIMARY AND SECONDARY CLOCK INPUTS
PI7C8154 implements a primary clock input for the PCI interface. The primary interface is
synchronized to the primary clock input, P_CLK, and the secondary interface is
synchronized to the secondary clock. The secondary clock operates at either the same
frequency as the primary clock or at half of the frequency of the primary clock. PI7C8154
operates at a maximum frequency of 66 MHz.
9.2
SECONDARY CLOCK OUTPUTS
PI7C8154 has 10 secondary clock outputs, S_CLKOUT[9:0] that can be used as clock inputs
for up to nine external secondary bus devices. The S_CLKOUT[9:0] outputs are derived
from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of
0ns. These are the rules for using secondary clocks:
!
!
Each secondary clock output is limited to no more than one load.
One of the secondary clocks must be used for the S_CLKIN.
10
PCI POWER MANAGEMENT
PI7C8154 incorporates functionality that meets the requirements of the PCI Power
Management Specification, Revision 1.0. These features include:
!
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
!
Support for D0, D3HOT and D3COLD power management states
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!
!
Support for D0, D1, D2, D3HOT, and D3COLD power management states for devices
behind the bridge
Support of the B2 secondary bus power state when in the D3HOT power management
state
Table 10-1 shows the states and related actions that PI7C8154 performs during power
management transitions. (No other transactions are permitted.)
Table 10-1 POWER MANAGEMENT TRANSITIONS
Current Status
D0
Next State
D3COLD
Action
Power has been removed from PI7C8154. A power-up reset must be
performed to bring PI7C8154 to D0.
D0
D3HOT
D2
If enabled to do so by the BPCCE pin, PI7C8154 will disable the
secondary clocks and drive them LOW.
D0
Unimplemented. PI7C8154 will ignore the write to the power state
bits. Power state will remain at D0.
D0
D1
Unimplemented. PI7C8154 will ignore the write to the power state
bits. Power state will remain at D0.
D3HOT
D0
PI7C8154 enables secondary clock outputs and performs an internal
chip reset. Signal S_RST_L will not be asserted. All registers will
be returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8154. A power-up reset must be
performed to bring PI7C8154 to D0.
D3COLD
D3COLD
D3COLD
D0
Power-up reset. PI7C8154 performs the standard power-up reset
functions as described in Section 11.
PME_L signals are routed from downstream devices around PCI-to-PCI bridges. PME_L
signals do not pass through PCI-to-PCI bridges.
11
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
11.1
PRIMARY INTERFACE RESET
PI7C8154 has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
!
PI7C8154 immediately tri-states all primary PCI interface signals. S_AD[31:0] and
S_CBE[3:0] are driven LOW on the secondary interface and other control signals are
tri-stated.
!
!
!
PI7C8154 performs a chip reset.
Registers that have default values are reset.
PI7C8154 samples P_REQ64_L to determine whether the 64-bit extension is enabled on
the primary.
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P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8154 is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8154 remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
11.2
SECONDARY INTERFACE RESET
PI7C8154 is responsible for driving the secondary bus reset signals, S_RESET_L. PI7C8154
asserts S_RESET_L when any of the following conditions are met:
Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as
P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET_L remains
asserted until a configuration write operation clears the secondary reset bit.
The chip reset bit in the diagnostic control register is set. S_RESET_L remains asserted
until a configuration write operation clears the secondary reset bit. The S_RESET_L in
asserting and de-asserting edges can be asynchronous to P_CLK.
When S_RESET_L is asserted, all secondary PCI interface control signals, including the
secondary grant outputs, are immediately tri-stated. Signals S_AD[31:0], S_CBE[3:0],
S_PAR are driven low for the duration of S_RESET_L assertion. S_REQ64_L is asserted
LOW to indicate 64-bit extension support on the secondary. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers at
the time of secondary reset are discarded.
When S_RESET_L is asserted by means of the secondary reset bit, PI7C8154 remains
accessible during secondary interface reset and continues to respond to accesses to its
configuration space from the primary interface.
11.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8154 and the
secondary bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are tri-
stated. S_RESET_L is asserted and the secondary reset bit is automatically set.
S_RESET_L remains asserted until a configuration write operation clears the secondary reset
bit. Within 20 PCI clock cycles after completion of the configuration write operation,
PI7C8154’s reset bit automatically clears and PI7C8154 is ready for configuration.
During reset, PI7C8154 is inaccessible.
12
CONFIGURATION REGISTERS
PCI configuration defines a 64 DWORD space to define various attributes of PI7C8154 as
shown below.
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12.1
CONFIGURATION REGISTER
Table 12-1 CONFIGURATION SPACE MAP
DWORD
31-24
23-16
15-8
7-0
Address
00h
Device ID
Vendor ID
Primary Status
Primary Command
04h
Class Code
Header Type
Revision ID
Cache Line Size
08h
Reserved
Primary Latency Timer
0Ch
10h
Reserved
Reserved
14h
Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
I/O Limit Address
Primary Bus Number
I/O Base Address
18h
Secondary Status
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
Memory Limit Address
Prefetchable Memory Limit Address
Memory Base Address
Prefetchable Memory Base Address
Prefetchable Memory Base Address Upper 32-bit
Prefetchable Memory Limit Address Upper 32-bit
I/O Limit Address Upper 16-bit
Reserved
I/O Base Address Upper 16-bit
Capability Pointer
Reserved
Reserved
Bridge Control
Arbiter Control
Interrupt
Reserved
Diagnostic / Chip Control
Reserved
Extended Chip Control
Secondary
Bus Arbiter
Preemption
Control
Reserved
Upstream Memory Base Address
4Ch
Upstream Memory Limit Address
50h
54h
58h
Upstream Memory Base Address Upper 32-bits
Upstream Memory Limit Address Upper 32-bit
Reserved
5Ch – 60h
64h
GPIO Data and Control
P_SERR_L Event
Disable
Reserved
P_SERR_L Status
Reserved
Secondary Clock Control
68h
6Ch - 70h
74h
Reserved
Port Option
Retry Counter
Reserved
78h
7Ch
Primary Master Timeout Counter
Secondary Master Timeout Counter
80h
Reserved
Reserved
84h – ACh
B0h
Chassis Number Slot Number
Next Pointer
Capability ID
B4h – D8h
DCh
Power Management Capabilities
Data
Next Item Pointer
Capability ID
PPB Support Extensions
Reserved
Power Management Data
E0h
E4h - EFh
12.1.1
SIGNAL TYPES
Signal Type
R/O
Description
Read Only
R/W
Read / Write
R/WC
R/WR
R/WS
Read / Write 1 to Clear
Read / Write 1 to Reset (about 20 clocks)
Read / Write 1 to Set
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12.1.2
VENDOR ID REGISTER – OFFSET 00h
Bit
15:0
Function
Vendor ID
Type
R/O
Description
Identifies Pericom as vendor of this device. Hardwired as 12D8h.
12.1.3
12.1.4
DEVICE ID REGISTER – OFFSET 00h
Bit
31:16
Function
Device ID
Type
R/O
Description
Identifies this device as the PI7C8154. Hardwired as 8154h.
COMMAND REGISTER – OFFSET 04h
Bit
Function
Type
Description
Controls response to I/O access on the primary interface
0: ignore I/O transactions on the primary interface
0
I/O Space Enable R/W
1: enable response to I/O transactions on the primary interface
Reset to 0
Controls response to memory accesses on the primary interface
0: ignore memory transactions on the primary interface
Memory Space
R/W
1
2
Enable
1: enable response to memory transactions on the primary interface
Reset to 0
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary
interface and disable response to memory and I/O transactions on
the secondary interface
Bus Master
R/W
Enable
1: enables PI7C8154 to operate as a master on the primary
interfaces for memory and I/O transactions forwarded from the
secondary interface
Reset to 0
Special Cycle
R/O
No special cycles defined.
3
4
Enable
Bit is defined as read only and returns 0 when read
PI7C8154 does not generate Memory Write and Invalidate except
forwarding a transaction for another master. Bit is implemented as
read only and returns 0 when read.
Memory Write
And Invalidate
Enable
R/O
Controls response to VGA compatible palette accesses
0: ignore VGA palette accesses on the primary
VGA Palette
Snoop Enable
5
6
R/W
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h,
3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded
and may be any value)
Controls response to parity errors
0: 7C8152 may ignore any parity errors that it detects and continue
normal operation
Parity Error
Response
R/W
1: 7C8152 must take its normal action when a parity error is
detected
Reset to 0
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Bit
Function
Type
Description
Controls the ability to perform address / data stepping
0: disable address/data stepping (affects primary and secondary)
1: enable address/data stepping (affects primary and secondary)
Wait Cycle
Control
7
R/O
Reset to 0
Controls the enable for the P_SERR_L pin
0: disable the P_SERR_L driver
1: enable the P_SERR_L driver
P_SERR_L
enable
8
R/W
Reset to 0
Controls 7C8152’s ability to generate fast back-to-back transactions
to different devices on the primary interface.
Fast Back-to-
Back Enable
0: no fast back-to-back transactions
9
R/W
R/O
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
15:10
Reserved
12.1.5
STATUS REGISTER – OFFSET 04h
Bit
19:16
20
Function
Type
R/O
R/O
Description
Reserved
Reset to 0
Capabilities List
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
21
66MHz Capable
R/O
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
22
23
Reserved
Fast Back-to-
Back Capable
R/O
R/O
Reset to 0
Set to 1 to indicate PI7C8154 is capable of decoding fast back-to-
back transactions on the primary interface to different targets
Reset to 1
24
Data Parity Error
Detected
R/WC
R/O
Set to 1 when P_PERR_L is asserted and bit 6 of
command register is set
Reset to 0
DEVSEL_L timing (medium decoding)
26:25
DEVSEL_L
timing
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
27
28
Signaled Target
Abort
R/WC
R/WC
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Received Target
Abort
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
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Bit
29
Function
Received Master
Abort
Type
R/WC
Description
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
30
31
Signaled System
Error
R/WC
R/WC
Set to 1 when P_SERR_L is asserted
Reset to 0
Detected Parity
Error
Set to 1 when address or data parity error is detected on the primary
interface
Reset to 0
12.1.6
12.1.7
REVISION ID REGISTER – OFFSET 08h
Bit
7:0
Function
Revision
Type
R/O
Description
Indicates revision number of device. Hardwired to 01h
CLASS CODE REGISTER – OFFSET 08h
Bit
Function
Type
Description
15:8
Programming
Interface
R/O
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
23:16
31:24
Sub-Class Code
Base Class Code
R/O
R/O
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
12.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch
Bit
7:0
Function
Cache Line Size
Type
R/W
Description
Designates the cache line size for the system and is used when
terminating memory write and invalidate transactions and when
prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of two
are valid (only one bit can be set in this register; only 00h, 01h, 02h,
04h, 08h, and 10h are valid values).
Reset to 0
12.1.9
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
Bit
15:8
Function
Primary Latency
timer
Type
R/W
Description
This register sets the value for the Master Latency Timer, which
starts counting when the master asserts FRAME_L.
Reset to 0
12.1.10
HEADER TYPE REGISTER – OFFSET 0Ch
Bit
23:16
Function
Header Type
Type
R/O
Description
Read as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
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12.1.11
12.1.12
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h
Bit
7:0
Function
Primary Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus to which the primary interface
is connected. The value is set in software during configuration.
Reset to 0
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
Bit
15:8
Function
Secondary Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus to which the secondary
interface is connected. The value is set in software during
configuration.
Reset to 0
12.1.13
12.1.14
12.1.15
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
Bit
23:16
Function
Subordinate Bus
Number
Type
R/W
Description
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
Bit
31:24
Function
Type
R/W
Description
Secondary
Designated in units of PCI bus clocks. Latency timer checks for
master accesses on the secondary bus interfaces that remain
unclaimed by any target.
Latency Timer
Reset to 0
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
Bit
3:0
7:4
Function
Type
Description
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
I/O Base Address R/W
[15:12]
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
12.1.16
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch
Bit
11:8
Function
32-bit Indicator
Type
R/O
Description
Read as 01h to indicate 32-bit I/O addressing
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Bit
15:12
Function
I/O Limit
Address
[15:12]
Type
R/W
Description
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be FFFh. The upper 16 bits corresponding to
address bits [31:16] are defined in the I/O limit address upper 16
bits address register
Reset to 0
12.1.17
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
20:16
21
Function
Type
R/O
R/O
Description
Reserved
Reset to 0
66MHz Capable
Set to 1 to enable 66MHz operation on the secondary interface
Reset to 1
22
23
Reserved
R/O
R/O
Reset to 0
Set to 1 to indicate PI7C8154 is capable of decoding fast back-to-
back transactions on the secondary interface to different targets
Fast Back-to-
Back Capable
Reset to 1
Set to 1 when S_PERR_L is asserted and bit 6 of command register
is set
Data Parity Error
Detected
24
R/WC
R/O
Reset to 0
DEVSEL_L timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
DEVSEL_L
timing
26:25
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary interface
Signaled Target
Abort
27
28
R/WC
R/WC
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
Received Target
Abort
Reset to 0
Set to 1 (by a master) when transactions on its secondary interface
are terminated with Master Abort
Received Master
Abort
29
30
31
R/WC
R/WC
R/WC
Reset to 0
Set to 1 when S_SERR_L is asserted
Received System
Error
Reset to 0
Set to 1 when address or data parity error is detected on the
secondary interface
Detected Parity
Error
Reset to 0
12.1.18
MEMORY BASE ADDRESS REGISTER – OFFSET 20h
Bit
Function
Type
Description
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Bit
3:0
Function
Reserved
Type
R/O
Description
Lower four bits of register are read only and return 0.
Reset to 0
15:4
Memory Base
Address [15:4]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
12.1.19
12.1.20
MEMORY LIMIT REGISTER – OFFSET 20h
Bit
19:16
Function
Reserved
Type
R/O
Description
Lower four bits of register are read only and return 0.
Reset to 0
31:20
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
PEFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET
24h
Bit
3:0
Function
64-bit addressing
Type
R/O
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
15:4
Prefetchable
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
Memory Base
Address [31:20]
12.1.21
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER –
OFFSET 24h
Bit
19:16
Function
64-bit addressing
Type
R/O
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
31:20
Prefetchable
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be
FFFFFh.
Memory Limit
Address [31:20]
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12.1.22
12.1.23
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
Bit
31:0
Function
Type
R/W
Description
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
Bit
31:0
Function
Type
R/W
Description
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
12.1.24
12.1.25
12.1.26
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
15:0
Function
Type
R/W
Description
I/O Base
Defines the upper 16-bits of a 32-bit bottom address of an address
range for the bridge to determine when to forward I/O transactions
from one interface to the other.
Address, Upper
16-bits [31:16]
Reset to 0
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
31:16
Function
Type
R/W
Description
I/O Limit
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Address, Upper
16-bits [31:16]
Reset to 0
ECP POINTER REGISTER – OFFSET 34h
Bit
7:0
Function
Type
R/O
Description
Enhanced
Capabilities Port
Pointer
Enhanced capabilities port offset pointer. Read as DCh to indicate
that the first item resides at that configuration offset.
Page 84 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.27
INTERRUPT LINE REGISTER – OFFSET 3Ch
Bit
7:0
Function
Interrupt Line
Type
R/W
Description
For POST to program to FFh, indicating that the PI7C8154 does not
implement an interrupt pin.
12.1.28
12.1.29
INTERRUPT PIN REGISTER – OFFSET 3Ch
Bit
15:8
Function
Interrupt Pin
Type
R/O
Description
Interrupt pin not supported on the PI7C8154
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
16
Function
Parity Error
Response
Type
R/W
Description
Controls the bridge’s response to parity errors on the secondary
interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
17
18
S_SERR_L
enable
R/W
R/W
Controls the forwarding of S_SERR_L to the primary interface.
0: disable the forwarding of S_SERR_L to primary interface
1: enable the forwarding of S_SERR_L to primary interface
Reset to 0
ISA enable
Modifies the bridge’s response to ISA I/O addresses, applying only
to those addresses falling within the I/O base and limit address
registers and within the first 64KB of PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the
last 768 bytes in each 1KB block
Reset to 0
19
20
VGA enable
Reserved
R/W
R/O
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses
from primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Page 85 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Bit
21
Function
Master Abort
Mode
Type
R/W
Description
Control’s bridge’s behavior responding to master aborts on
secondary interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible or by the
assertion of P_SERR_L if enabled
Reset to 0
22
23
24
Secondary
R/W
R/W
R/W
Controls the assertion of S_RESET_L signal pin on the secondary
interface
Interface Reset
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
Fast Back-to-
Back Enable
Controls bridge’s ability to generate fast back-to-back transactions on
the secondary interface.
0: does not allow fast back-to-back transactions on the secondary
1: enables fast back-to-back transactions on the secondary
Reset to 0
Primary Master
Timeout
Determines the maximum number of PCI clock cycles the PI7C8154
waits for an initiator on the primary interface to repeat a delayed
transaction request.
0: Primary discard timer counts 215 PCI clock cycles.
1: Primary discard timer counts 210 PCI clock cycles.
Reset to 0
25
Secondary
R/W
Determines the maximum number of PCI clock cycles the PI7C8154
waits for an initiator on the primary interface to repeat a delayed
transaction request.
Master Timeout
0: Primary discard timer counts 215 PCI clock cycles.
1: Primary discard timer counts 210 PCI clock cycles.
Reset to 0
26
27
Master Timeout
Status
R/WC
R/W
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
Discard Timer
P_SERR_L
enable
This bit is set to 1 and P_SERR_L is asserted when either the
primary discard timer or the secondary discard timer expire.
0: P_SERR_L is not asserted on the primary interface as a result of
the expiration of either the Primary Discard Timer or the Secondary
Discard Timer.
1: P_SERR_L is asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary
Discard Timer.
Reset to 0
31-28
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
Page 86 of 110
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PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.30
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Bit
0
1
Function
Type
R/O
R/W
Description
Reserved
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
Memory Write
Disconnect
Control
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
4
Reserved
Secondary Bus
Prefetch Disable
R/O
R/W
Reserved. Returns 0 when read. Reset to 0.
Controls the bridge’s ability to prefetch during upstream memory
read transactions
0: PI7C8154 prefetches and does not forward byte enable bits during
upstream memory read transactions.
1: PI7C8154 requests only 1 DWORD from the target and forwards
read byte enable bits during upstream memory reads.
Reset to 0
5
Live Insertion
Mode
R/W
R/O
Enables control of transaction forwarding
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input only, this bit enables GPIO[3] to mask
the I/O enable, memory enable, and master enable bits to 0. These
bits are masked when GPIO[3] is driven HIGH. As a result,
PI7C8154 stops accepting I/O and memory transactions.
Reset to 0
7:6
8
Reserved
Chip Reset
Reserved. Returns 0 when read. Reset to 0
R/WR Controls the chip and secondary bus reset.
0: PI7C8154 is ready for operation
1: Causes PI7C8154 to perform a chip reset
10:9
Test Mode For
All Counters at
Primary and
Secondary
R/O
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all 32-bits of PMWQ_TIMEOUT_COUNTER,
DTR_TIMEOUT_COUNTER and all 16-bits of DTC_TIMEOUT
are exercised.
01: byte 1 of PMWQ_TIMEOUT_COUNTER,
DTR_TIMEOUT_COUNTER and byte 1 of DTC_TIMEOUT are
exercised.
10: byte 2 of PMWQ_TIMEOUT_COUNTER,
DTR_TIMEOUT_COUNTER is exercised.
11: byte 3 of PMWQ_TIMEOUT_COUNTER,
DTR_TIMEOUT_COUNTER is exercised.
Reset to 00
Reserved. Returns 0 when read. Reset to 0.
15:11
Reserved
R/O
Page 87 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.31
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
24:16
Function
Arbiter Control
Type
R/W
Description
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ[8:0]
0: low priority
1: high priority
Reset to 0
25
Priority of
Secondary
Interface
R/W
R/O
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
31:26
Reserved
Reserved. Returns 0 when read. Reset to 0.
12.1.32
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
Controls ability to do memory read flow through
Memory Read
Flow Through
Disable
0: Enable flow through during a memory read transaction
1: Disables flow through during a memory read transaction
0
R/W
Reset to 0
Controls bus arbiter’s park function
0: Park to last master
1: Park to the bridge
1
Park
R/W
R/O
Reset to 0
15:2
Reserved
Reserved. Returns 0 when read. Reset to 0
Page 88 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.33
SECONDARY BUS ARBITER PREEMPTION CONTROL
REGISTER – OFFSET 4Ch
Bit
Function
Type
Description
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles after FRAME asserted
0001: Preemption enabled after 1 clock cycle after FRAME asserted
0010: Preemption enabled after 2 clock cycles after FRAME asserted
0011: Preemption enabled after 4 clock cycles after FRAME asserted
0100: Preemption enabled after 8 clock cycles after FRAME asserted
Secondary bus
arbiter
31:28
R/W
preemption
contorl
0101: Preemption enabled after 16 clock cycles after FRAME
asserted
0110: Preemption enabled after 32 clock cycles after FRAME
asserted
0111: Preemption enabled after 64 clock cycles after FRAME
asserted
12.1.34
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0
Controls PI7C8154’s ability to assert P_SERR_L when it is unable to
transfer any read data from the target after 224 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
Posted Write
Parity Error
1
2
3
R/W
R/W
R/W
1: P_SERR_L is not asserted if this event occurs.
Reset to 0
Controls PI7C8154’s ability to assert P_SERR_L when it is unable to
transfer delayed write data after 224 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
Posted Write
Non-Delivery
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8154’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
Target Abort
During Posted
Write
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Page 89 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Bit
Function
Type
Description
Controls PI7C8154’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
Master Abort On
Posted Write
4
R/W
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8154’s ability to assert P_SERR_L when it is unable to
transfer delayed write data after 224 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
Delayed Write
Non-Delivery
5
R/W
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8154’s ability to assert P_SERR_L when it is unable to
transfer any read data from the target after 224 attempts.
Delayed Read –
No Data From
Target
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
6
7
R/W
R/O
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Reserved
Reserved. Returns 0 when read. Reset to 0
12.1.35
GPIO DATA REGISTER – OFFSET 64h
Bit
Function
Type
Description
Setting any of these bits to 1 drives the corresponding bits LOW on
the GPIO[3:0] bus if it is programmed as bi-directional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. The bit positions corresponding
GPIO output
11:8
R/WC to the GPIO pins that are programmed as input only are not driven.
Writing 0 to theses bits has no effect and will return the last written
value when read. Bits [11:8] correspond to GPIO [3:0].
write-1-to-clear
Reset to 0
Setting any of these bits to 1 drives the corresponding bits HIGH on
the GPIO[3:0] bus if it is programmed as bi-directional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. The bit positions corresponding
GPIO output
write-1-to-set
15:12
R/WS
to the GPIO pins that are programmed as input only are not driven.
Writing 0 to theses bits has no effect and will return the last written
value when read. Bits [15:12] correspond to GPIO [3:0].
Reset to 0
12.1.36
GPIO CONTROL REGISTER – OFFSET 64h
Bit
Function
Type
Description
Setting any of these bits to 1 configures the corresponding bits on the
GPIO[3:0] bus as input only. As a result, the output driver is tri-
stated. Writing 0 to theses bits has no effect and will return the last
written value when read. Bits [19:16] correspond to GPIO [3:0].
GPIO output
enable write-1-
to-clear
19:16
R/WC
Reset to 0
Page 90 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Bit
Function
Type
Description
Setting any of these bits to 1 configures the corresponding bits on the
GPIO[3:0] bus as bi-directional; the output driver is enabled and
drives the value set in the output data register (offset 65h). Writing 0
to theses bits has no effect and will return the last written value when
read. Bits [23:20] correspond to GPIO [3:0].
GPIO output
enable write-1-
to-set
23:20
R/WS
Reset to 0
12.1.37
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
Function
Type
Description
S_CLKOUT[0] (slot 0) Enable
00: enable S_CLKOUT[0]
S_CLKOUT[0]
disable
01: enable S_CLKOUT[0]
1:0
R/W
10: enable S_CLKOUT[0]
11: disable S_CLKOUT[0] and driven HIGH
Reset to 00
S_CLKOUT[1] (slot 1) Enable
00: enable S_CLKOUT[1]
S_CLKOUT[1]
disable
01: enable S_CLKOUT[1]
3:2
5:4
7:6
R/W
R/W
R/W
10: enable S_CLKOUT[1]
11: disable S_CLKOUT[1] and driven HIGH
Reset to 00
S_CLKOUT[2] (slot 2) Enable
00: enable S_CLKOUT[2]
S_CLKOUT[2]
disable
01: enable S_CLKOUT[2]
10: enable S_CLKOUT[2]
11: disable S_CLKOUT[2] and driven HIGH
Reset to 00
S_CLKOUT[3] (slot 3) Enable
00: enable S_CLKOUT[3]
S_CLKOUT[3]
disable
01: enable S_CLKOUT[3]
10: enable S_CLKOUT[3]
11: disable S_CLKOUT[3] and driven HIGH
Reset to 00
S_CLKOUT[4] (device 1) Enable
S_CLKOUT[4]
disable
0: enable S_CLKOUT[4]
8
R/W
R/W
R/W
1: disable S_CLKOUT[4] and driven HIGH
Reset to 0
S_CLKOUT[5] (device 2) Enable
S_CLKOUT[5]
disable
0: enable S_CLKOUT[5]
9
1: disable S_CLKOUT[5] and driven HIGH
Reset to 0
S_CLKOUT[6] (device 3) Enable
S_CLKOUT[6]
disable
0: enable S_CLKOUT[6]
10
1: disable S_CLKOUT[6] and driven HIGH
Reset to 0
Page 91 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Bit
Function
Type
Description
S_CLKOUT[7] (device 4) Enable
S_CLKOUT[7]
disable
0: enable S_CLKOUT[7]
11
R/W
1: disable S_CLKOUT[7] and driven HIGH
Reset to 0
S_CLKOUT[8] (device 5) Enable
S_CLKOUT[8]
disable
0: enable S_CLKOUT[8]
12
R/W
1: disable S_CLKOUT[8] and driven HIGH
Reset to 0
S_CLKOUT[9] (PI7C8154) Enable
0: enable S_CLKOUT[4]
1: disable S_CLKOUT[4] and driven HIGH
S_CLKOUT[9]
disable
13
R/W
RO
This bit is initialized upon secondary reset by shifting in a serial data
stream. The bit is assigned to correspond to the PI7C8154 secondary
clock input (S_CLKIN).
Reset to 0
Reserved. Reset to 1
15:14
Reserved
12.1.38
P_SERR_L STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
Address Parity
Error
16
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
Posted Write
17
18
19
20
21
22
23
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
Data Parity Error
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
Posted Write
Non-delivery
deliver post memory write data to the target after 224 attempts.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Target Abort
during Posted
Write
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Master Abort
during Posted
Write
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
Delayed Write
Non-delivery
deliver delayed write data after 224 attempts.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
Delayed Read –
No Data from
Target
read any data from the target after 224 attempts.
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Delayed
Transaction
Master Timeout
Reset to 0.
Page 92 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.39
PORT OPTION REGISTER – OFFSET 74h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8154’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
Primary Memory
Read Command
Alias Enable
1
R/W
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Reserved
Primary Memory
Write Command
Alias Enable
2
3
R/W
R/W
Reset to 0
Controls PI7C8154’s detection mechanism for matching memory
read retry cycles from the initiator on the secondary
Secondary
0: exact matching for memory read retry cycles from initiator on the
secondary interface
Memory Read
Command Alias
Enable
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the secondary interface
Reset to 0
Reserved
Secondary
Memory Write
Command Alias
Enable
4
R/W
R/O
Reset to 0
8:5
Reserved
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8154’s ability to enable long requests for lock cycles
0: normal lock operation
Enable Long
Request
9
R/W
1: enable long request for lock cycle
Reset to 0
Control’s PI7C8154’s ability to enable the secondary bus to hold
requests longer.
Enable
0: internal secondary master will release REQ_L after FRAME_L
assertion
Secondary To
Hold Request
Longer
10
R/W
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Control’s PI7C8154’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
Enable Primary
To Hold Request
Longer
11
R/W
R/O
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
15:12
Reserved
Reserved. Returns 0 when read. Reset to 0.
Page 93 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.40
12.1.41
12.1.42
RETRY COUNTER REGISTER – OFFSET 78h
Bit
Function
Type
Description
Holds the maximum number of attempts that PI7C8154 will try
before reporting retry timeout. Retry count set at 224 PCI clocks.
Default is 0100 0000h.
31:0
Retry Counter
R/W
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h
Bit
Function
Type
Description
Primary timeout occurs after 215 PCI clocks.
15:0
Primary Timeout
R/W
Reset to 8000h.
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 82h
Bit
Function
Type
Description
Secondary timeout occurs after 215 PCI clocks.
Secondary
Timeout
31:16
R/W
Reset to 8000h.
12.1.43
12.1.44
12.1.45
CAPABILITY ID REGISTER – OFFSET DCh
Bit
Function
Type
Description
Enhanced
Read as 01h to indicate that these are power management enhanced
capability registers.
7:0
R/O
Capabilities ID
NEXT ITEM POINTER REGISTER – OFFSET DDh
Bit
Function
Next Item
Pointer
Type
Description
Read as B0h. Points to slot number register.
15:8
R/O
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET
DEh
Bit
Function
Power
Type
Description
Read as 001 to indicate the device is compliant to Revision 1.0 of
PCI Power Management Interface Specifications.
18:16
Management
Revision
R/O
19
20
PME_L Clock
R/O
R/O
Read as 0 to indicate PI7C8154 does not support the PME_L pin.
Read as 0 to indicate PI7C8154 does not support the PME_L pin or
an auxiliary power source.
Auxiliary Power
Device Specific
Initialization
Reserved
Read as 0 to indicate PI7C8154 does not have device specific
initialization requirements.
21
R/O
R/O
R/O
24:22
25
Read as 0
D1 Power State
Support
Read as 0 to indicate PI7C8154 does not support the D1 power
management state.
D2 Power State
Support
Read as 0 to indicate PI7C8154 does not support the D2 power
management state.
26
R/O
R/O
31:27
PME_L Support
Read as 0 to indicate PI7C8154 does not support the PME_L pin.
Page 94 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
12.1.46
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
Bit
Function
Type
Description
Indicates the current power state of PI7C8154. If an unimplemented
power state is written to this register, PI7C8154 completes the write
transaction, ignores the write data, and does not change the value of
the field. Writing a value of D0 when the previous state was D3
cause a chip reset without asserting S_RESET_L
00: D0 state
1:0
Power State
R/W
01: D1 state (not implemented)
10: D2 state (not implemented)
11: D3 state
Reset to 0
7:2
8
12:9
14:13
15
Reserved
R/O
R/O
R/O
R/O
R/O
Read as 0
PME_L Enable
Data Select
Data Scale
PME status
Read as 0 as PI7C8154 does not support the PME_L pin.
Read as 0 as the data register is not implemented.
Read as 0 as the data register is not implemented.
Read as 0 as the PME_L pin is not implemented.
12.1.47
PPB SUPPORT EXTENSIONS REGISTER – OFFSET E2h
Bit
21:16
Function
Reserved
Type
R/O
Description
Reserved. Reset to 0
B2_B3 Support for D3HOT: When BPCCE is read as 1, this bit is
driven as a logic level 1 to indicate that the secondary bus clock
outputs will be stopped and driven LOW when the device is placed in
D3HOT. This bit is undefined when BPCCE is read as 0.
Bus Power / Clock Control Enable: When the BPCCE pin is tied
HIGH, this bit is read as a 1 to indicate that the bus power/clock
control mechanism is enabled. When the BPCCE pin is tied LOW,
this bit is read as a 0 to indicate that the bus power / clock control
mechanism is disabled.
22
23
B2_B3
R/O
R/O
Bus Power/Clock
Control Enable
12.1.48
DATA REGISTER – OFFSET E3h
Bit
Function
Type
Description
Data Register: Register is not implemented and is read as 00h.
31:24
Data
R/O
Reset to 0.
13
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number of
possibilities. Those possibilities are summarized in the table below:
Page 95 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
13.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator
Target
Response
Master on Primary
Target on Primary
PI7C8154 does not respond. It detects
this situation by decoding the address as
well as monitoring the P_DEVSEL_L for
other fast and medium devices on the
Primary Port.
Master on Primary
Target on Secondary
PI7C8154 asserts P_DEVSEL_L,
terminates the cycle normally if it is able
to be posted, otherwise return with a retry.
It then passes the cycle to the appropriate
port. When the cycle is complete on the
target port, it will wait for the initiator to
repeat the same cycle and end with normal
termination.
PI7C8154 does not respond and the cycle
will terminate as master abort.
PI7C8154 does not respond.
Master on Primary
Master on Secondary
Master on Secondary
Target not on Primary nor
Secondary Port
Target on the same
Secondary Port
Target on Primary or the
other Secondary Port
PI7C8154 asserts S_DEVSEL_L,
terminates the cycle normally if it is able
to be posted, otherwise returns with a
retry. It then passes the cycle to the
appropriate port. When cycle is complete
on the target port, it will wait for the
initiator to repeat the same cycle and end
with normal termination.
Master on Secondary
Target not on Primary nor
the other Secondary Port
PI7C8154 does not respond.
13.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
13.2.1
MASTER ABORT
Master abort indicates that when PI7C8154 acts as a master and receives no response (i.e.,
no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge deasserts
FRAME_L and then de-asserts IRDY_L.
13.2.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
P_PAR64, S_PAR, and S_PAR64 signals. Parity should be even (i. e. an even number
of‘1’s) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD
and CBE are valid. For reads, even parity must be generated using the initiators CBE signals
combined with the read data. Again, the PAR signal corresponds to read data from the
previous data phase cycle.
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13.2.3
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR_L signal by asserting P_SERR_L for one cycle and then tri-stating two cycles after
the bad address. P_SERR_L can only be asserted if bit 6 and 8 in the Command Register are
both set to 1. For write data phases, a parity error should be reported by asserting the
P_PERR_L signal two cycles after the data phase and should remain asserted for one cycle
when bit 6 in the Command register is set to a 1. The target reports any type of data parity
errors during write cycles, while the master reports data parity errors during read cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the
bus (P_DEVSEL_L remains inactive) and the cycle will then terminate with a Master Abort.
When the bridge is acting as master, a data parity error during a read cycle results in the
bridge master initiating a Master Abort.
13.2.4
SECONDARY IDSEL MAPPING
When PI7C8154 detects a Type 1 configuration transaction for a device connected to
the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream
interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number.
This is translated to S_AD[31:16] by PI7C8154.
14
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are
provided to support boundary scan in PI7C8154 for board-level continuity test and
diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital
input, output, input/output pins are tested except TAP pins.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and
a group of test data registers including Bypass and Boundary Scan registers. The TAP
controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test
Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the
machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not
active when the PCI resource is operating PCI bus cycles.
PI7C8154 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST.
14.1
BOUNDARY SCAN ARCHITECTURE
Boundary-scan test logic consists of a boundary-scan register and support logic. These are
accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that
allows all processor signal pins to be driven and/or sampled, thereby providing direct control
and monitoring of processor pins at the system level.
This mode of operation is valuable for design debugging and fault diagnosis since it permits
examination of connections not normally accessible to the test system. The following
subsections describe the boundary-scan test logic elements: TAP pins, instruction register,
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test data registers and TAP controller. Figure 14-1 illustrates how these pieces fit together to
form the JTAG unit.
Figure 14-1 TEST ACCESS PORT BLOCK DIAGRAM
14.1.1
14.1.2
TAP PINS
The PI7C8154’s TAP pins form a serial port composed of four input connections (TMS,
TCK, TRST_L and TDI) and one output connection (TDO). These pins are described in
Table 14-1. The TAP pins provide access to the instruction register and the test data
registers.
INSTRUCTION REGISTER
The Instruction Register (IR) holds instruction codes. These codes are shifted in through the
Test Data Input (TDI) pin. The instruction codes are used to select the specific test operation
to be performed and the test data register to be accessed.
The instruction register is a parallel-loadable, master/slave-configured 5-bit wide, serial-shift
register with latched outputs. Data is shifted into and out of the IR serially through the TDI
pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon
latching from the master stage to the slave stage. At that time the IR outputs along with the
TAP finite state machine outputs are decoded to select and control the test data register
selected by that instruction. Upon latching, all actions caused by any previous instructions
terminate.
The instruction determines the test to be performed, the test data register to be accessed, or
both. The IR is two bits wide. When the IR is selected, the most significant bit is connected
to TDI, and the least significant bit is connected to TDO. The value presented on the TDI pin
is shifted into the IR on each rising edge of TCK. The TAP controller captures fixed parallel
data (1101 binary). When a new instruction is shifted in through TDI, the value 1101(binary)
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is always shifted out through TDO, least significant bit first. This helps identify instructions
in a long chain of serial data from several devices.
Upon activation of the TRST_L reset pin, the latched instruction asynchronously changes to
the id code instruction. When the TAP controller moves into the test state other than by reset
activation, the opcode changes as TDI shifts, and becomes active on the falling edge of TCK.
14.2
BOUNDARY SCAN INSTRUCTION SET
The PI7C8154 supports three mandatory boundary-scan instructions (BYPASS, SAMPLE
and EXTEST). Table 14-1 shown below lists the PI7C8154’s boundary-scan instruction
codes.
Table 14-1 TAP PINS
Instruction
Requisite
EXTEST
/
Opcode (binary)
Description
00000
EXTEST initiates testing of external circuitry, typically board-
level interconnects and off chip circuitry. EXTEST connects the
boundary-scan register between TDI and TDO. When EXTEST
is selected, all output signal pin values are driven by values
shifted into the boundary-scan register and may change only of
the falling edge of TCK. Also, when EXTEST is selected, all
system input pin states must be loaded into the boundary-scan
register on the rising-edge of TCK.
IEEE 1149.1
Required
SAMPLE
IEEE 1149.1
Required
0001
SAMPLE performs two functions:
!
A snapshot of the sample instruction is captured on the
rising edge of TCK without interfering with normal
operation. The instruction causes boundary-scan register
cells associated with outputs to sample the value being
driven.
!
On the falling edge of TCK, the data held in the boundary-
scan cells is transferred to the slave register cells.
Typically, the slave latched data is applied to the system
outputs via the EXTEST instruction.
INTSCAN
CLAMP
00010
00100
Enable internal SCAN test
CLAMP instruction allows the state of the signals driven from
component pins to be determined from the boundary-scan
register while the bypass register is selected as the serial path
between TDI and TDO. The signal driven from the component
pins will not change while the CLAMP instruction is selected.
BYPASS instruction selects the one-bit bypass register between
TDI and TDO pins. 0 (binary) is the only instruction that
accesses the bypass register. While this instruction is in effect,
all other test data registers have no effect on system operation.
Test data registers with both test and system functionality
performs their system functions when this instruction is selected.
BYPASS
11111
14.3
TAP TEST DATA REGISTERS
The PI7C8154 contains two test data registers (bypass and boundary-scan). Each test data
register selected by the TAP controller is connected serially between TDI and TDO. TDI is
connected to the test data register’s most significant bit. TDO is connected to the least
significant bit. Data is shifted one bit position within the register towards TDO on each
rising edge of TCK. While any register is selected, data is transferred from TDI to TDO
without inversion. The following sections describe each of the test data registers.
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14.4
14.5
BYPASS REGISTER
The required bypass register, a one-bit shift register, provides the shortest path between TDI
and TDO when a bypass instruction is in effect. This allows rapid movement of test data to
and from other components on the board. This path can be selected when no test operation is
being performed on the PI7C8154.
BOUNDARY-SCAN REGISTER
The boundary-scan register contains a cell for each pin as well as control cells for I/O and
the high-impedance pin.
Table 14-2 shows the bit order of the PI7C8154 boundary-scan register. All table cells that
contain “Control” select the direction of bi-directional pins or high-impedance output pins.
When a “1” is loaded into the control cell, the associated pin(s) are high-impedance or
selected as output.
The boundary-scan register is a required set of serial-shiftable register cells, configured in
master/slave stages and connected between each of the PI7C8154’s pins and on-chip system
logic. The VDD, GND, and JTAG pins are NOT in the boundary-scan chain.
The boundary-scan register cells are dedicated logic and do not have any system function.
Data may be loaded into the boundary-scan register master cells from the device input pins
and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions.
Parallel loading takes place on the rising edge of TCK.
Data may be scanned into the boundary-scan register serially via the TDI serial input pin,
clocked by the rising edge of TCK. When the required data has been loaded into the master-
cell stages, it can be driven into the system logic at input pins or onto the output pins on the
falling edge of TCK state. Data may also be shifted out of the boundary-scan register by
means of the TDO serial output pin at the falling edge of TCK.
14.6
TAP CONTROLLER
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that
controls the sequence of test logic operations. The TAP can be controlled via a bus master.
The bus master can be either automatic test equipment or a component (i.e., PLD) that
interfaces to the TAP. The TAP controller changes state only in response to a rising edge of
TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls
the sequence of state changes. The TAP controller is initialized after power-up by applying a
low to the TRST_L pin. In addition, the TAP controller can be initialized by applying a high
signal level on the TMS input for a minimum of five TCK periods.
For greater detail on the behavior of the TAP controller, test logic in each controller state and
the state machine and public instructions, refer to the IEEE 1149.1 Standard Test Access
Port and Boundary-Scan Architecture document (available from the IEEE).
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2-PORT PCI-TO-PCI BRIDGE
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Table 14-2 JTAG BOUNDARY REGISTER ORDER
Boundary-Scan
Pin Name
Ball Location
Type
Register Number
0
S_PAR64
S_AD[32]
S_AD[33]
S_AD[34]
S_AD[35]
S_AD[36]
S_AD[37]
S_AD[38]
S_AD[39]
S_AD[40]
S_AD[41]
S_AD[42]
S_AD[43]
S_AD[44]
S_AD[45]
S_AD[46]
S_AD[47]
S_AD[48]
S_AD[49]
S_AD[50]
S_AD[51]
S_AD[52]
S_AD[53]
S_AD[54]
S_AD[55]
S_AD[56]
S_AD[57]
S_AD[58]
S_AD[59]
S_AD[60]
S_AD[61]
S_AD[62]
S_AD[63]
S_CBE[4]
S_CBE[5]
S_CBE[6]
S_CBE[7]
S_REQ64_L
S_ACK64_L
S_AD[0]
N21
M21
M23
M22
L22
L21
L23
K21
K22
K23
J22
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
CONTROL
BIDIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
J20
J23
H21
H22
H23
G21
G22
G20
F22
F23
F21
E23
E21
D22
E20
D21
C22
C23
C21
D20
A21
C20
D19
A20
C19
A19
B19
C18
A18
B18
A17
D17
B17
C17
B16
C16
A15
B15
C15
A14
B14
C14
D13
A13
B13
C13
C12
S_AD[1]
S_AD[2]
S_AD[3]
S_AD[4]
S_AD[5]
S_AD[6]
S_AD[7]
S_CBE[0]
S_AD[8]
S_AD[9]
S_M66EN
S_AD[10]
S_AD[11]
S_AD[12]
S_AD[13]
S_AD[14]
S_AD[15]
S_CBE[1]
*
S_PAR
B12
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Boundary-Scan
Pin Name
Ball Location
Type
Register Number
60
S_SERR_L
S_PERR_L
S_LOCK_L
S_STOP_L
S_DEVSEL_L
S_TRDY_L
S_IRDY_L
*
B11
C11
A11
C10
B10
A10
C9
INPUT
BIDIR
61
62
BIDIR
63
BIDIR
64
BIDIR
65
BIDIR
66
BIDIR
67
CONTROL
BIDIR
68
S_FRAME_L
S_CBE[2]
B9
D9
A9
C8
B8
A8
B7
D7
A7
A6
C6
B5
C5
B4
A4
C4
B3
A3
69
BIDIR
70
S_AD[16]
BIDIR
71
S_AD[17]
BIDIR
72
S_AD[18]
BIDIR
73
S_AD[19]
BIDIR
74
S_AD[20]
BIDIR
75
S_AD[21]
BIDIR
76
S_AD[22]
BIDIR
77
S_AD[23]
BIDIR
78
S_CBE[3]
BIDIR
79
S_AD[24]
BIDIR
80
S_AD[25]
BIDIR
81
S_AD[26]
BIDIR
82
S_AD[27]
BIDIR
83
S_AD[28]
BIDIR
84
S_AD[29]
BIDIR
85
S_AD[30]
BIDIR
86
*
CONTROL
BIDIR
87
S_AD[31]
C3
D4
C1
C2
D3
E4
D1
D2
E3
E1
E2
F3
F1
F2
88
S_REQ_L[0]
S_REQ_L[1]
S_REQ_L[2]
S_REQ_L[3]
S_REQ_L[4]
S_REQ_L[5]
S_REQ_L[6]
S_REQ_L[7]
S_REQ_L[8]
S_GNT_L[0]
S_GNT_L[1]
S_GNT_L[2]
S_GNT_L[3]
*
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
BIDIR
89
90
91
92
93
94
95
96
97
98
BIDIR
99
BIDIR
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
BIDIR
CONTROL
BIDIR
S_GNT_L[4]
S_GNT_L[5]
S_GNT_L[6]
S_GNT_L[7]
S_GNT_L[8]
S_RESET_L
S_CLKIN
G1
G4
G2
G3
H1
H2
J4
K1
K2
K3
L4
L1
L2
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
INPUT
INPUT
BIDIR
S_CFN_L
GPIO[3]
GPIO[2]
BIDIR
GPIO[1]
BIDIR
GPIO[0]
BIDIR
S_CLKOUT[0]
*
OUTPUT
CONTROL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
S_CLKOUT[1]
S_CLKOUT[2]
S_CLKOUT[3]
S_CLKOUT[4]
S_CLKOUT[5]
S_CLKOUT[6]
L3
M3
M1
M2
N3
N1
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Boundary-Scan
Register Number
122
Pin Name
Ball Location
Type
S_CLKOUT[7]
S_CLKOUT[8]
S_CLKOUT[9]
P_RESET_L
P_GNT_L
BPCCE
P3
P2
P1
R3
R2
R4
T3
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
CONTROL
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
INPUT
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
CONTROL
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
INPUT
CONTROL
BIDIR
OUTPUT
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
INPUT
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
123
124
125
126
127
128
P_CLK
129
*
130
P_REQ_L
P_AD[31]
P_AD[30]
P_AD[29]
P_AD[28]
P_AD[27]
P_AD[26]
P_AD[25]
P_AD[24]
P_CBE[3]
P_IDSEL]
P_AD[23]
P_AD[22]
P_AD[21]
P_AD[20]
P_AD[19]
P_AD[18]
P_AD[17]
P_AD[16]
*
U3
U2
131
132
U4
133
U1
134
V2
135
V1
136
V3
137
W2
W1
Y2
138
139
140
Y1
141
W4
Y3
142
143
AA1
AA3
Y4
144
145
146
AB3
AA4
Y5
147
148
149
150
P_CBE[2]
P_FRAME_L
P_IRDY_L
P_TRDY_L
P_DEVSEL_L
P_STOP_L
P_LOCK_L
*
AB4
AA5
AC5
AB5
AA6
AC6
AB6
151
152
153
154
155
156
157
158
P_PERR_L
P_SERR_L
P_PAR
AC7
Y7
159
160
AB7
161
P_CBE[1]
P_AD[15]
P_AD[14]
P_AD[13]
P_AD[12]
P_AD[11]
P_AD[10]
P_M66EN
P_AD[9]
AA7
162
AB8
163
AA8
164
AC9
165
AB9
166
AA9
167
AC10
AB10
AA10
Y11
168
169
170
P_AD[8]
171
P_CBE[0]
P_AD[7]
AC11
AB11
AA11
AA12
AB12
AB13
AA13
Y13
AA14
AB14
AC14
AA15
AB15
172
173
P_AD[6]
174
P_AD[5]
175
P_AD[4]
176
P_AD[3]
177
P_AD[2]
178
P_AD[1]
179
P_AD[0]
180
P_ACK64_L
P_REQ64_L
P_CBE[7]
P_CBE[6]
181
182
183
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Boundary-Scan
Pin Name
Ball Location
Type
Register Number
184
185
186
P_CBE[5]
P_CBE[4]
P_AD[63]
P_AD[62]
P_AD[61]
P_AD[60]
P_AD[59]
P_AD[58]
P_AD[57]
P_AD[56]
P_AD[55]
P_AD[54]
P_AD[53]
P_AD[52]
P_AD[51]
P_AD[50]
P_AD[49]
P_AD[48]
P_AD[47]
P_AD[46]
P_AD[45]
P_AD[44]
P_AD[43]
P_AD[42]
P_AD[41]
P_AD[40]
P_AD[39]
P_AD[38]
P_AD[37]
P_AD[36]
P_AD[35]
P_AD[34]
*
Y15
AC15
AA16
AB16
AA17
AB17
Y17
AB18
AC18
AA18
AC19
AA19
AB20
Y19
AA20
AB21
AC21
AA21
Y20
AA23
Y21
W20
Y23
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
CONTROL
BIDIR
BIDIR
BIDIR
INPUT
INPUT
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
W21
W23
W22
V21
V23
V22
U23
U20
U22
P_AD[33]
P_AD[32]
P_PAR64
CONFIG66
MSK_IN
T23
T22
T21
R22
R21
15
ELECTRICALAND TIMING SPECIFICATIONS
15.1
MAXIMUM RATINGS
(Above which the useful life may be impaired. For user guidelines, not tested).
Storage Temperature
-65°C to 150°C
0°C to 85°C
-0.3V to 3.6V
-0.5V to 5.5V
125°C
Ambient Temperature with Power Applied
Supply Voltage to Ground Potentials (AVCC and VDD only]
Voltage at Input Pins
Junction Temperature, TJ
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
Page 104 of 110
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PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
15.2
DC SPECIFICATIONS
Symbol
VDD
Parameter
Condition
Min.
3
Max.
Units
V
Notes
Supply Voltage
3.6
VIH
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
5V Signaling Output HIGH
Voltage
5V Signaling Output LOW
Voltage
Input Leakage Current
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
0.5 VDD
-0.5
VDD + 0.5
0.3 VDD
V
1
1
VIL
V
VOH
0.9VDD
V
Iout = -500µA
Iout = 1500µA
Iout = -2 mA
VOL
0.1 VDD
V
VOH5V
2.4
V
VOL5V
Iout = 6 mA
0.5
V
IIL
CIN
CCLK
CIDSEL
LPIN
0 < Vin < VDD
±10
10
12
8
µA
pF
pF
pF
nH
5
20
Notes:
1. VDD is in reference to the VDD of the input device.
15.3
AC SPECIFICATIONS
Figure 15-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS
66 MHz
33 MHz
Symbol
Tsu
Parameter
Min.
Max.
Min.
Max.
Units
Input setup time to CLK – bused signals 1,2,3
Input setup time to CLK – point-to-point 1,2,3
Input signal hold time from CLK 1,2
CLK to signal valid delay – bused signals 1,2,3
CLK to signal valid delay – point-to-point 1,2,3
Float to active delay 1,2
3
5
0
2
2
2
-
-
7
-
Tsu(ptp)
Th
-
10, 124
-
-
0
2
2
2
-
-
ns
Tval
6
6
-
11
12
-
Tval(ptp)
Ton
Toff
Active to float delay 1,2
14
28
1. See Figure 15-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
signals are synchronized to S_CLKOUT.
3. Point-to-point signals are P_REQ_L, S_REQ_L[7:0], P_GNT_L, S_GNT_L[7:0],
HSLED, HS_SW_L, HS_EN, and ENUM_L. Bused signals are P_AD, P_BDE_L, P_PAR,
Page 105 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
P_PERR_L, P_SERR_L, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_LOCK_L,
P_DEVSEL_L, P_STOP_L, P_IDSEL, P_PAR64, P_REQ64_L, P_ACK64_L, S_AD,
S_CBE_L, S_PAR, S_PERR_L, S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L,
S_LOCK_L, S_DEVSEL_L, S_STOP_L, S_PA64, S_REQ64_L, and S_ACK64_L.
4. REQ_L signals have a setup of 10 and GNT_L signals have a setup of 12.
15.4
15.5
15.6
66MHZ PCI SIGNALING TIMING
Symbol
TSKEW
TDELAY
TCYCLE
THIGH
Parameter
Condition
Min.
0
Max.
0.250
5.0
Units
SKEW among S_CLKOUT[9:0]
DELAY between PCLK and S_CLKOUT[9:0]
P_CLK, S_CLKOUT[9:0] cycle time
P_CLK, S_CLKOUT[9:0] HIGH time
P_CLK, S_CLKOUT[9:0] LOW time
20pF load
3.3
15
6
ns
30
TLOW
6
33MHZ PCI SIGNALING TIMING
Symbol
TSKEW
TDELAY
TCYCLE
THIGH
Parameter
Condition
Min.
0
Max.
0.250
5.0
Units
SKEW among S_CLKOUT[9:0]
DELAY between PCLK and S_CLKOUT[9:0]
P_CLK, S_CLKOUT[9:0] cycle time
P_CLK, S_CLKOUT[9:0] HIGH time
P_CLK, S_CLKOUT[9:0] LOW time
20pF load
3.3
30
ns
11
TLOW
11
RESET TIMING
Symbol
TRST
Parameter
Min.
1
Max.
Units
us
P_RESET_L active time after power stable
P_RESET_L active time after P_CLK stable
P_RESET_L active-to-output float delay
S_RESET_L active after P_RESET_L assertion
S_RESET_L active time after S_CLKIN stable
-
TRST-CLK
TRST-OFF
TSRST
100
-
-
us
40
40
-
ns
-
ns
TSRST-ON
TDRST
100
20
us
S_RESET_L deassertion after P_RESET_L deassertion
25
cycles
15.7
GPIO TIMING (66MHZ AND 33MHZ)
Symbol
TVGPIO
TGON
Parameter
Min.
Max.
Units
ns
S_CLKIN to GPIO output valid
GPIO float to output valid
2
2
12
-
ns
TGOF
TGSU
TGH
F
GPIO active to float delay
-
28
ns
GPIO-to-S_CLKIN setup time
GPIO hold time after S_CLKIN
S_CLKIN-to-GPIO shift clock output valid
GPIO[0] cycle time
7
-
ns
0
-
nx
ns
TGCVAL
TGCYC
TGSVAL
TMSU
-
13.5
30
-
∞
8
-
ns
GPIO[0] to GPIO[2] shift control output valid
MSK_IN setup time to GPIO[0]
MSK_IN hold time after GPIO[0]
ns
15
0
ns
TMH
-
ns
Page 106 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
15.8
JTAG TIMING
Symbol
TIF
Parameter
Min.
0
Max.
10
∞
Units
MHz
ns
TCK frequency
TJP
TCK period
100
45
45
-
TJHT
TJLT
TJRT
TJFT
TJE
TCK HIGH time
-
ns
TCK LOW time
-
ns
TCK rise time1
10
10
-
ns
TCK fall time2
-
ns
TDI, TMS setup time to TCK rising edge
TDI, TMS hold time from TCK rising edge
TDO valid delay from TCK falling edge3
TDO float delay from TCK falling edge
10
25
-
ns
TJH
-
ns
TJD
30
30
ns
TJFD
-
ns
1. Measured between 0.8V and 2.0V.
2. Measured between 2.0V and 0.8V.
3. C1 = 50pF
15.9
POWER CONSUMPTION
Parameter
Typical
1.6
440
Units
W
mA
Power Consumption at 66MHz
Supply Current, ICC
Page 107 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
16
PACKAGE INFORMATION
16.1
304-BALL PBGA PACKAGE DIAGRAM
Figure 16-1 304-BALL PBGA PACKAGE OUTLINE
Thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php
16.2
ORDERING INFORMATION
Part Number
PI7C8154NA
PI7C8154NA-33
Speed
Pin – Package
304 – PBGA
304 – PBGA
Temperature
0°C to 85°C
0°C to 85°C
66MHz
33MHz
Page 108 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
NOTES:
Page 109 of 110
May 29, 2003 – Revision 1.02
PI7C8154
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
NOTES:
Page 110 of 110
May 29, 2003 – Revision 1.02
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