PT7C4502WE [PERICOM]

Clock Generator,;
PT7C4502WE
型号: PT7C4502WE
厂家: PERICOM SEMICONDUCTOR CORPORATION    PERICOM SEMICONDUCTOR CORPORATION
描述:

Clock Generator,

文件: 总5页 (文件大小:184K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Data Sheet  
PT7C4502  
PLL Clock Multiplier  
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Features  
Description  
The PT7C4502 is a high performance frequency  
Low cost frequency multiplier  
multiplier, which integrates Analog Phase Lock Loop  
techniques.  
Zero ppm multiplication error  
Input crystal frequency of 5 - 30 MHz  
Input clock frequency of 4 - 50 MHz  
Output clock frequencies up to 180 MHz  
Period jitter 50ps (100~180MHz)  
Duty cycle of 45/55%  
The PT7C4502 is the most cost effective way to  
generate a high quality, high frequency clock output  
from a lower frequency crystal or clock input. It is  
designed to replace crystal oscillators in most electronic  
systems, clock multiplier and frequency translation.  
Using Phase-Locked-Loop (PLL) techniques, the  
device uses a standard fundamental mode, inexpensive  
crystal to produce output clocks up to 180 MHz.  
The complex Logic divider is the ability to generate  
nine different popular multiplication factors, allowing  
one chip to output many common frequencies.  
The device also has an Output Enable pin that tri-  
states the clock output when the OE pin is taken low.  
This product is intended for clock generation and  
frequency translation with low output jitter (variation in  
the output period)  
Operating voltages of 3.0 to 5.5V  
Tri-state output for board level testing  
Die and Lead free and Green SOIC-8 package  
Application  
Ceramic heating controller  
Ordering Information  
Part No.  
PT7C4502-1GDE  
Package  
Die from  
PT7C4502WE  
Lead free and Green 8-pin SOIC  
Block Diagram  
S0  
S1  
PLL Clock Synthesis  
and  
Output  
CLK  
Buffer  
Control Circuit  
X1/ICLK  
X2  
Crystal  
Oscillator  
VCC  
GND  
PT0140(11/09)  
Ver:3  
1
Data Sheet  
PT7C4502  
PLL Clock Multiplier  
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Pin/Pad Configuration  
1520um  
OE  
AVDD DVDD  
X1 -ICLK  
X2  
PT7C4502W  
Part No.  
1
8
OE  
Vcc  
2
3
X1/ICLK  
X2  
7
6
S1  
S0  
S1  
DGND  
CLK S0  
AGND  
GND  
4
5
CLK  
SOIC-8 package  
Pin/Pad Description  
Pin Name  
Pad Name  
Type  
Description  
X1/ICLK  
X1-ICLK  
I
O
I
Crystal connection or clock input.  
X2  
S0  
Crystal connection. Leave unconnected for clock input.  
Multiplier select pin 0. Connect to Vcc or float.  
S1  
I
Multiplier select pin 1. Connect to GND or float. Internally pulled up.  
OE  
CLK  
I
Output Enable. Tri-states CLK output when low.  
Clock output.  
Analog Power.  
Digital power.  
Analog Ground  
O
P
P
P
AVDD  
DVDD  
AGND  
VCC  
GND  
DGND  
P
Digital ground.  
Pad Coordinate File  
Pad Name  
X Coordinate  
Y Coordinate  
Pad Name  
X Coordinate  
Y Coordinate  
X1-ICLK  
X2  
S1  
AGND  
DGND  
120.90  
120.90  
117.70  
111.50  
698.40  
892.90  
641.50  
401.10  
225.80  
118.60  
CLK  
S0  
DVDD  
AVDD  
OE  
1098.90  
1322.10  
1303.50  
1063.10  
470.70  
118.60  
118.60  
973.30  
973.30  
981.70  
Note: Substrate is connected to GND.  
Die Size: 1520µm*1100µm (Including scribe line size.)  
Die Thickness: 265±25µm without coating.  
Pad Size: 100µm*100µm  
PT0140(11/09)  
Ver:3  
2
Data Sheet  
PT7C4502  
PLL Clock Multiplier  
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Maximum Ratings  
Note:  
o
o
Stresses greater than those listed under MAXIMUM  
RATINGS may cause permanent damage to the  
device. This is a stress rating only and functional  
operation of the device at these or any other condi-  
tions above those indicated in the operational sec-  
tions of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended  
periods may affect reliability.  
Storage Temperature......................................................................................-65 C to +150 C  
Supply Voltage to Ground Potential (VCC) ..................................................-0.3V to + 7.0V  
Inputs(Reference to GND)...............................................-0.5V to Vcc + 0.5V  
Clock Output (Reference to GND).........................-0.5V to Vcc + 0.5V  
Soldering Temperature (Max of 10 seconds)..............................260OC  
Recommended operation conditions  
Symbol  
Description  
Min  
Type  
Max  
Unit  
TA  
Operation Temperature  
Supply voltage  
-40  
3.0  
-
-
+85  
5.5  
°C  
VDD  
V
DC Electrical Characteristics (VCC = 3.3V± 0.3V, TA = 0 ~ 70ºC, unless otherwise noted)  
Sym.  
Parameter  
Supply Voltage  
Test Condition  
Pin  
Min.  
Typ.  
Max.  
Unit  
Vcc  
-
Vcc  
3
5.5  
20  
V
no load, 20MHz crystal,  
OE = Vcc  
Vcc  
Vcc  
-
-
12  
mA  
mA  
Icc  
Supply Current  
no load, 20MHz crystal,  
OE = GND  
0.7  
2
VIH  
VIL  
VIH  
VIM  
VIL  
VOH  
VOL  
IS  
Input Logic High  
-
ICLK, OE  
ICLK, OE  
S0, S1  
S0, S1  
S0, S1  
CLK  
2
-
V
V
Input Logic Low  
-
-
-
0.8  
-
Input Logic High  
-
Vcc-0.5  
-
V
Input mid-level  
-
-
-
Vcc/2  
-
V
Input Logic Low  
-
-
-
0.5  
-
V
High-level output voltage  
Low-level output voltage  
Short Circuit Current  
IOH = -12mA  
2.4  
-
V
IOL = 12mA  
CLK  
-
0.4  
-
V
-
-
-
CLK  
-
mA  
µA  
µA  
±70  
OE  
-
1
II  
Input Leakage Current  
S1  
-
-7.5  
-20  
PT0140(11/09)  
Ver:3  
3
Data Sheet  
PT7C4502  
PLL Clock Multiplier  
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AC Electrical Characteristics (VCC = 3.3V± 0.3V, TA = 0 ~ 70ºC, unless otherwise noted)  
Sym.  
Parameter  
Input Frequency  
Test Condition  
Crystal  
Pin  
Min.  
Typ.  
Max.  
Unit  
fIN  
ICLK  
5
30  
MHz  
Vcc: 4.5 to 5.5V  
Vcc: 3.0 to 3.6V  
CLK  
CLK  
-
-
12  
20  
2
MHz  
MHz  
fOUT  
Output frequency  
0.7  
tr  
tf  
Output clock rise time  
Output clock fall time  
Output clock duty cycle  
PLL bandwidth  
0.8 to 2.0V  
CLK  
CLK  
CLK  
-
-
1
1
-
-
ns  
ns  
2.0 to 0.8V  
Duty  
At Vcc/2  
45  
10  
-
50  
-
55  
-
%
-
kHz  
ns  
Output enable time  
Output disable time  
Period Jitter  
OE high to output on  
OE low to tri-state  
100MHz~180MHz  
-
50  
50  
100  
-
-
ns  
CLK  
-
50  
ps  
Mechanical Information  
WE (SOIC-8)  
8
.149  
.157  
3.78  
3.99  
.0099  
.0196  
x 45o  
0.25  
0.50  
1
.189  
.196  
4.80  
5.00  
0-8o  
0.19  
0.25  
.0075  
.0098  
.016  
.050  
0.40  
1.27  
.016  
.026  
0.406  
0.660  
REF  
1.35  
1.75  
.053  
.068  
.2284  
.2440  
5.80  
6.20  
SEATING PLANE  
.050  
BSC  
1.27  
.0040  
.0098  
0.10  
0.25  
X.XX DENOTES DIMENSIONS  
X.XX IN MILLIMETERS  
.013  
.020  
0.330  
0.508  
Note:  
1) Controlling dimensions in millimeters.  
2) Ref: JEDEC MS-012 AA  
PT0140(11/09)  
Ver:3  
4
Data Sheet  
PT7C4502  
PLL Clock Multiplier  
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Notes  
Email: support@pti.com.cn Web Site: www.pti.com.cn, www.pti-ic.com  
China:  
No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China  
Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181  
Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong  
Tel: (852)-2243 3660 Fax: (852)- 2243 3667  
U.S.A.:  
3545 North First Street, San Jose, California 95134, USA  
Tel: (1)-408-435 0800 Fax: (1)-408-435 1100  
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or  
performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the  
circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other  
rights, of Pericom Technology Incorporation.  
PT0140(11/09)  
Ver:3  
5

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