74ABTH16373B [NXP]
16-bit transparent latch 3-State; 16位透明锁存器三态
| 型号： | 74ABTH16373B |
| 厂家： | 
NXP |
| 描述： | 16-bit transparent latch 3-State |
| 文件： | 总10页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
Product specification
1998 Feb 27
Supersedes data of 1995 Aug 03
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
When nOE is Low, the latched or transparent data appears at the
outputs. When nOE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
FEATURES
• 16-bit transparent latch
• Multiple V and GND pins minimize switching noise
CC
Two options are available, 74ABT16373B which does not have the
bus-hold feature and 74ABTH16373B which incorporates the
bus-hold feature.
• Power-up 3-State
• Live insertion/extraction permitted
• Power-up reset
PIN CONFIGURATION
• 3-State output buffers
1
2
48
47
1OE
1Q0
1Q1
GND
1Q2
1Q3
1E
• 74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
1D0
3
46 1D1
GND
1D2
4
45
44
• Output capability: +64mA/–32mA
5
• I
–19 mA maximum
CCL
6
43 1D3
• Latch-up protection exceeds 500mA per JEDEC Std 17
V
7
42
41
40
39
38
37
36
35
34
33
32
31
30
V
CC
CC
8
1Q4
1Q5
1D4
1D5
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
9
and 200V per Machine Model
GND
GND
10
11
12
13
14
15
16
17
18
19
1Q6
1Q7
2Q0
2Q1
GND
1D6
1D7
2D0
2D1
GND
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
2Q2
2Q3
2D2
2D3
V
V
CC
CC
The data on each set of D inputs are transferred to the latch outputs
when the Latch Enable (nE) input is High. The latch remains
transparent to the data inputs while nE is High, and stores the data
that is present one setup time before the High-to-Low enable
transition.
2Q4
2D4
29 2D5
2Q5 20
21
22
23
24
28
27
26
25
GND
2Q6
GND
2D6
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE) controls eight 3-State buffers
independent of the latch operation.
2Q7
2OE
2D7
2E
SA00379
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
2.5
2.0
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
C
Input capacitance
Output capacitance
V = 0V or V
CC
4
7
pF
pF
IN
I
C
V
= 0V or V ; 3-State
O CC
OUT
CCZ
I
Outputs disabled; V = 5.5V
500
8
µA
mA
CC
Quiescent supply current
I
Outputs low; V = 5.5V
CC
CCL
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
SOT370-1
48-Pin SSOP type III
–40°C to +85°C
–40°C to +85°C
74ABT16373B DL
BT16373B DL
48-Pin TSSOP type II
48-Pin SSOP type III
48-Pin TSSOP type II
74ABT16373B DGG
BT16373B DGG
SOT362-1
–40°C to +85°C
–40°C to +85°C
74ABTH16373B DL
BH16373B DL
SOT370-1
SOT362-1
74ABTH16373B DGG
BH16373B DGG
2
1998 Feb 27
853-1751 19027
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
PIN NUMBER
SYMBOL
FUNCTION
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
1
1EN
C3
1OE
1E
1D0 – 1D7
2D0 – 2D7
Data inputs
48
24
25
2EN
C4
2OE
2E
2, 3, 5, 6, 8, 9, 11, 12,
13, 14, 16, 17, 19, 20,
22, 23
1Q0 – 1Q7
2Q0 – 2Q7
Data outputs
47
46
44
43
41
40
38
37
36
2
3D
1
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
Output enable inputs
(active-Low)
3
5
1, 24
1OE, 2OE
1E, 2E
GND
Enable inputs
(active-High)
48, 25
6
8
4, 10, 15, 21, 28, 34,
39, 45
Ground (0V)
9
11
12
13
14
16
17
19
20
22
23
Positive supply
voltage
7, 18, 31, 42
V
CC
4D
2
LOGIC SYMBOL
35
33
32
30
29
27
26
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
47 46 44 43 41 40 38 37
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1LE
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
SA00380
2
3
5
6
8
9
11 12
36 35 33 32 30 29 27 26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13 14 16 17 19 20 22 23
SA00044
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
Q
Q
Q
Q
Q
Q
Q
E
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
3
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
FUNCTION TABLE
INPUTS
OUTPUTS
nQ0 – nQ7
INTERNAL
REGISTER
OPERATING MODE
nOE
nE
nDx
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
i
h
L
H
L
H
Latch and read register
Hold
L
L
X
NC
NC
H
H
L
H
X
Dn
NC
Dn
Z
Z
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low E transition
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–18
UNIT
V
V
CC
I
IK
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
I
DC output current
mA
OUT
output in High state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
0
MAX
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
–40
+85
4
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
= +25°C
T
= –40°C
to +85°C
amb
T
amb
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
V
IK
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
IH
V
OH
High-level output voltage
Low-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output voltage
= 5.5V; I = 1mA; V = GND or V
O I CC
Input leakage current
74ABT16373B
I
I
V
CC
= 5.5V; V = V or GND
±0.01
±1
±1
µA
I
CC
V
V
V
V
V
V
V
= 5.5V; V = V or GND Control pins
±0.01
0.01
–1
±1
1
±1
1
µA
µA
µA
CC
CC
CC
CC
CC
CC
CC
I
CC
Input leakage current
74ABTH16373B
I
= 5.5V; V = V
I
I
CC
5
Data pins
= 5.5V; V = 0
–3
–5
I
= 4.5V; V = 0.8V
50
50
I
6
Bus Hold current A inputs
74ABTH16373B
I
µA
= 4.5V; V = 2.0V
–75
–75
HOLD
I
= 5.5V; V = 0 to 5.5V
±800
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V 4.5V
±5.0
±5.0
±100
±50
±100
±50
µA
µA
≤
I
OFF
O
V
CC
V
OE
= 2.1V; V = 0.5V; V = GND or V
;
CC
O
I
I
/I
PU PD
4
output current
= GND
I
3-State output High current
3-State output Low current
V
CC
V
CC
V
CC
= 5.5V; V = 5.5V; V = V or V
0.5
–0.5
–70
10
10
µA
µA
OZH
O
I
IL
IH
IH
I
= 5.5V; V = 0.0V; V = V or V
–10
–10
OZL
O
I
IL
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–180
–50
–180
mA
O
Output High leakage
current
I
V
= 5.5V; V = 5.5V; V = GND or V
CC
0.1
50
50
µA
CEX
CCH
CC
O
I
I
V
CC
V
CC
V
CC
= 5.5V; Outputs High, V = GND or V
0.5
8
2
2
mA
mA
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
19
19
CCL
I
CC
= 5.5V; Outputs 3-State;
I
0.5
5
2
2
mA
CCZ
V = GND or V
I
CC
Additional supply current
V
CC
= 5.5V; one input at 3.4V, other inputs
CC
2
per input pin
∆I
∆I
100
100
µA
CC
at V or GND
74ABT16373B
Additional supply current
V
CC
= 5.5V; one input at 3.4V, other inputs
CC
2
per input pin
0.5
1.5
1.5
mA
CC
at V or GND
74ABTH16373B
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V, with a transition time of up to 10msec. From V = 2.1 to V = 5V ± 10% a
CC
CC
CC
transition time of up to 100µsec is permitted.
5. Unused pins at V or GND.
CC
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
5
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
MAX
T
V
= +25°C
= +5.0V
T
V
= –40 to +85°C
UNIT
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
= +5.0V ±0.5V
MIN
TYP
MIN
MAX
t
t
Propagation delay
nDx to nQx
1.5
1.1
2.5
2.0
3.8
3.1
1.5
1.1
4.4
3.8
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
nE to nQx
1.6
1.3
2.5
2.1
3.8
3.1
1.6
1.3
4.4
3.6
PLH
PHL
t
t
Output enable time
to High and Low level
4
5
1.2
1.3
2.3
2.3
3.5
3.5
1.2
1.3
4.6
4.5
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
1.9
1.7
3.1
2.6
4.5
3.8
1.9
1.7
5.3
4.2
PHZ
PLZ
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
T
V
= +25°C
= +5.0V
T
V
= –40 to +85°C
= +5.0V ±0.5V
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
MIN
TYP
MIN
t (H)
t (L)
s
Setup time, High or Low
nDx to nE
1.0
1.0
0.0
0.3
1.0
1.0
s
3
3
1
ns
ns
ns
t (H)
Hold time, High or Low
nDx to nE
0.5
0.5
–0.2
0.0
0.5
0.5
h
t (L)
h
Enable pulse width
High
t (H)
w
2.5
1.0
2.5
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
V
V
V
V
V
M
nE
M
M
M
M
t
nDx
t
t
w
(H)
PLH
PHL
t
t
PLH
PHL
nQx
V
M
V
M
V
V
M
nQx
M
SA00047
SA00048
Waveform 1. Propagation Delay, Enable to Output, and
Enable Pulse Width
Waveform 2. Propagation Delay for Data to Outputs
6
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
V
V
V
V
M
nDx
nE
M
M
M
nOE
nQx
V
V
M
M
t (H)
s
t (L)
s
t (H)
h
t (L)
h
t
t
PLZ
PZL
V
V
M
M
V
M
V
V
+ 0.3V
OL
OL
NOTE: The shaded areas indicate when the input is per-
mitted to change for predictable output performance.
SA00051
SA00049
Waveform 3. Data Setup and Hold Times
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
V
V
M
nOE
nQx
M
t
t
PHZ
PZH
V
V
OH
OH
– 0.3V
0V
V
M
SA00050
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORM
t
W
V
AMP (V)
CC
90%
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
L
0V
(t
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
TLH
)
THL
F
R
)
t
(t )
R
R
L
C
TLH
R
THL F
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Input Pulse Definition
t
t
closed
PLZ
closed
open
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT/H16
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00018
7
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
8
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
9
1998 Feb 27
Philips Semiconductors
Product specification
74ABT16373B
74ABTH16373B
16-bit transparent latch (3-State)
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03491
Document order number:
Philips
Semiconductors
相关型号：
74ABTH16374BDGG-T
IC ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, SOT-362-1, TSSOP2-48, Bus Driver/Transceiver
NXP
74ABTH16374BDL-T
IC ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 7.50 MM, PLASTIC, SOT-370-1, SSOP3-48, Bus Driver/Transceiver
NXP
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