74LV573PW [NXP]
Octal D-type transparent latch 3-State; 八D型透明锁存器3 -STATE
| 型号： | 74LV573PW |
| 厂家： | 
NXP |
| 描述： | Octal D-type transparent latch 3-State |
| 文件： | 总14页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV573
Octal D-type transparent latch (3-State)
Product specification
1998 Jun 10
Supersedes data of 1997 Jun 06
IC24 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
FEATURES
• Wide operating voltage: 1.0 to 5.5V
DESCRIPTION
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT573.
• Optimized for Low Voltage applications: 1.0V to 3.6V
The 74LV573 is an octal D-type transparent latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches.
• Accepts TTL input levels between V = 2.7V and V = 3.6V
CC
CC
• Typical V
(output ground bounce) < 0.8V at V = 3.3V,
OLP
= 25°C
CC
T
amb
The ‘573’ consists of eight D-type transparent latches with 3-State
• Typical V
(output V undershoot) > 2V at V = 3.3V,
OHV
= 25°C
OH
CC
true outputs. When LE is HIGH, data at the D inputs enters the
n
T
amb
latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes.
• Inputs and outputs on opposite sides of package allowing easy
interface with microprocessors
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
• Useful as input or output port for microprocessors/microcomputer
• Common 3-State output enable input
• Output capability: bus driver
• I category: MSI
CC
The ‘573’ is functionally identical to the ‘563’ and the ‘373’, but the
‘563’ has inverted outputs and the ‘373’ has a different pin
arrangement.
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t = t v2.5 ns
amb
r f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
Dn to Qn
LE to Qn
C = 15pF
L
V
CC
= 3.3V
12
13
t
/t
ns
PHL PLH
C
C
Input capacitance
3.5
26
pF
pF
I
Power dissipation capacitance per latch
Notes 1, 2
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C V
x f )ȍ (C V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
ȍ (C V
f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC.
ORDERING AND PACKAGE INFORMATION
OUTSIDE NORTH
AMERICA
PACKAGES
TEMPERATURE RANGE
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
74LV573 N
74LV573 D
74LV573 N
74LV573 D
SOT146-1
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
74LV573 DB
74LV573 PW
74LV573 DB
74LV573PW DH
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1
OE
Output enabled input (active LOW)
Data inputs
2, 3, 4, 5,
6, 7, 8, 9
D0–D7
19, 18, 17, 16,
15, 14, 13, 12
Q0–Q7
Data outputs
10
11
20
GND
LE
Ground (0V)
Latch enable input (active HIGH)
Positive supply voltage
VCC
2
1998 Jun 10
853-1989 19545
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
FUNCTION TABLE
INPUTS
OUTPUTS
INTERNAL
LATCHES
OPERATING MODES
OE
LE
Dn
Q0 to Q7
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
L
L
L
L
I
h
L
H
L
H
Latch and read register
H
H
L
L
I
h
L
H
Z
Z
Latch register and disable outputs
= HIGH voltage level
H
h
L
I
= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
= High impedance OFF-state
Z
PIN CONFIGURATION
LOGIC SYMBOL
1
OE
1
20
VCC
Q0
OE
D0
D1
2
19
18
17
16
19
D0
2
3
4
5
6
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q1
Q2
Q3
Q4
3
4
5
6
18
17
D1
D2
D3
D4
D2
D3
16
15
D4
D5
15
14
13
12
11
D5
D6
D7
14
13
12
7
8
9
7
8
Q5
Q6
D6
D7
9
Q7
LE
LE
11
10
GND
SV00701
SV00702
3
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
LOGIC SYMBOL (IEEE/IEC)
FUNCTIONAL DIAGRAM
11
C1
2
3
4
5
D0
D1
D2
D3
19
18
17
16
15
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
EN1
2
19
1D
3
4
5
6
7
8
9
18
17
16
15
3-STATE
OUTPUTS
LATCH
1 TO 8
6
7
8
9
D4
D5
D6
D7
14
13
12
14
13
12
11
1
LE
OE
SV00703
SV00704
LOGIC DIAGRAM
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00661
4
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
–0.5 to +7.0
±I
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
20
50
mA
mA
IK
I
I
CC
±I
OK
V
O
< –0.5 or V > V + 0.5V
O
CC
DC output source or sink current
– bus driver outputs
±I
O
–0.5V < V < V + 0.5V
35
mA
O
CC
DC V or GND current for types with
–bus driver outputs
CC
±I
±I
,
70
mA
GND
CC
T
Storage temperature range
Power dissipation per package
–plastic DIL
–65 to +150
°C
stg
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
mW
tot
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP.
3.3
–
MAX
UNIT
V
CC
DC supply voltage
See Note 1
5.5
V
V
V
V
I
Input voltage
V
CC
V
CC
V
O
Output voltage
0
–
Operating ambient temperature range in free
air
See DC and AC
characteristics
–40
–40
+85
+125
T
amb
°C
V
CC
V
CC
V
CC
V
CC
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
= 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50
t , t
r
Input rise and fall times
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
5
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
MAX
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
= 1.2V
UNIT
1
MIN
0.9
1.4
2.0
TYP
MIN
0.9
1.4
2.0
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.0V
HIGH level Input
voltage
V
IH
V
= 2.7 to 3.6V
= 4.5 to 5.5V
= 1.2V
0.7*V
0.7*V
CC
CC
0.3
0.6
0.8
0.3
0.6
0.8
= 2.0V
LOW level Input
voltage
V
IL
V
V
= 2.7 to 3.6V
= 4.5 to 5.5
0.3*V
0.3*V
CC
CC
= 1.2V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
4.5
I
IH
IL;
O
= 2.0V; V = V or V –I = 100µA
1.8
2.5
2.8
4.3
1.8
2.5
2.8
4.3
I
IH
IL;
O
HIGH level output
voltage; all outputs
= 2.7V; V = V or V –I = 100µA
I
IH
IL;
O
= 3.0V; V = V or V –I = 100µA
I
IH
IL;
O
V
OH
= 4.5V;V = V or V –I = 100µA
I
IH
IL;
O
HIGH level output
voltage; BUS driver
outputs
V
CC
V
CC
= 3.0V;V = V or V –I = 8mA
2.40
3.60
2.82
4.20
2.20
3.50
I
IH
IL;
O
= 4.5V;V = V or V –I = 16mA
I
IH
IL;
O
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
0
0
0
0
0
I
IH
= 2.0V; V = V or V I
IL; O
0.2
0.2
0.2
0.2
0.2
I
IH
LOW level output
voltage; all outputs
= 2.7V; V = V or V I
IL; O
0.2
0.2
0.2
I
IH
= 3.0V;V = V or V I
= 100µA
I = 100µA
I
IH
IL; O
V
OL
V
= 4.5V;V = V or V
IL; O
I
IH
LOW level output
voltage; BUS driver
outputs
V
= 3.0V;V = V or V
I
= 8mA
0.20
0.35
0.40
0.55
0.50
0.65
CC
CC
I
IH
IL; O
V
= 4.5V;V = V or V
I
= 16mA
I
IH
IL; O
Input leakage
current
I
V
= 5.5V; V = V or GND
1.0
5
1.0
10
µA
µA
µA
I
CC
I
CC
3-State output
OFF-state current
V
V
= 5.5V; V = V or V
I IH IL;
CC
O
I
OZ
CC
= V or GND
CC
Quiescent supply
current; MSI
I
V
CC
= 5.5V; V = V or GND; I = 0
20.0
160
I
CC
O
Additional
quiescent supply
current per input
∆I
CC
V
CC
= 2.7V to 3.6V; V = V –0.6V
500
850
µA
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
6
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
AC CHARACTERISTICS
GND = 0V; t = t ≤ 2.5ns; C = 50pF; R = 1KΩ
r
f
L
L
LIMITS
–40 to +85 °C
LIMITS
–40 to +125 °C
CONDITION
(V)
SYMBOL
PARAMETER
WAVEFORM
UNIT
V
CC
MIN
–
TYP
75
MAX
–
MIN
–
MAX
–
1.2
2.0
2.7
–
26
39
29
23
19
–
–
49
36
29
24
–
Propagation delay
Dn to Qn
–
19
–
t
t
Figures 1, 5
Figures 2, 5
Figures 3, 5
Figures 3, 5
ns
PHL/ PLH
2
3.0 to 3.6
4.5 to 5.5
1.2
–
14
–
–
_
–
–
80
27
20
–
2.0
–
43
31
25
21
–
–
53
34
31
26
–
Propagation delay
LE to Qn
2.7
–
–
t
t
ns
ns
ns
PHL/ PLH
2
3.0 to 3.6
4.5 to 5.5
1.2
–
15
–
–
–
–
–
70
24
18
–
2.0
–
37
28
22
18
–
–
48
35
28
23
–
3-State output
enable time
OE to Qn
2.7
–
–
t
t
t
PZH/ PZL
2
3.0 to 3.6
4.5 to 5.5
1.2
–
13
–
–
–
–
–
80
29
22
–
2.0
–
39
29
24
20
–
–
48
36
29
24
–
3-State output
disable time
OE to Qn
2.7
–
–
t
PHZ/ PLZ
2
3.0 to 3.6
4.5 to 5.5
2.0
–
17
–
–
–
9
6
–
34
25
20
–
41
30
24
–
2.7
–
–
t
LE pulse width HIGH
Setup time Dn to LE
Figure 2
Figure 4
ns
ns
W
2
3.0 to 3.6
1.2
5
–
–
25
9
–
–
2.0
17
13
10
–
–
20
15
12
–
–
t
su
2.7
6
–
–
2
3.0 to 3.6
1.2
5
–
–
5
2
2
–
–
2.0
8
–
8
–
t
h
Hold time Dn to LE
Figure 4
ns
2.7
8
–
8
–
2
3.0 to 3.6
8
1
–
8
–
NOTES:
All typical values are measured at T
= 25°C
amb
1. Typical values are measured at V = 3.3V
CC
7
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
AC WAVEFORMS
V
V
V
= 1.5V at V w 2.7V and v 3.6V
M
CC
V
I
= 0.5 * V at V t 2.7V and w 4.5V
M
CC
CC
and V are the typical output voltage drop that occur with the
OL
OH
D
INPUT
V
n
M
output load.
V
X
V
X
V
Y
V
Y
= V + 0.3V at V w 2.7V and v 3.6V
GND
OL CC
t
h
t
h
= V + 0.1V at V < 2.7V and w 4.5V
OL
CC
CC
= V – 0.3V at V w 2.7V and v 3.6V
OH
CC
t
su
t
su
= V – 0.1V at V < 2.7V and w 4.5V
OH
CC
CC
V
I
V
I
LE INPUT
GND
V
M
D
INPUT
GND
V
n
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SV00665
t
t
PLH
PHL
V
Figure 4. Data set-up and hold times for the D input to the LE
OH
n
input
Q
n
OUTPUT
V
M
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
V
OL
SV00705
Figure 1. Data input (D ) to output (Q ) propagation delays and
n
n
the output transition times
TEST CIRCUIT
V
I
V
CC
LE INPUT
GND
V
2 * V
CC
Open
GND
M
t
W
R
R
= 1k
L
L
V
V
O
I
t
t
PLH
PHL
PULSE
GENERATOR
D.U.T.
V
OH
Q
n
OUTPUT
V
M
= 1k
R
T
50 pF
C
L
V
OL
SV00706
Test Circuit for Outputs
Figure 2. Latch enable input (LE) pulse width, the latch enable
input to output (Q ) propagation delays and the output
n
DEFINITIONS
transition times.
R
C
R
= Load resistor
L
L
T
= Load capacitance includes jig and probe capacitiance.
= Termination resistance should be equal to Z
of pulse generators.
OUT
SWITCH POSITION
V
I
S
TEST
V
V
I
1
CC
V
OE INPUT
GND
M
t
t
Open
2 * V
< 2.7V
V
CC
PLH/ PHL
t
t
t
t
t
2.7V
PLZ
PZL
PLZ/ PZL
CC
2.7–3.6V
V
CC
V
w 4.5V
CC
t
GND
PHZ/ PZH
Q
OUTPUT
n
V
LOW-to-OFF
OFF-to-LOW
M
V
SV00896
X
V
OL
Figure 5. Load circuitry for switching times
t
PZH
t
PHZ
V
OH
V
Y
Q
n
OUTPUT
V
M
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
disabled
outputs
enabled
outputs
enabled
SV00664
Figure 3. 3-State enable and disable times
8
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
9
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
10
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
11
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
12
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
NOTES
13
1998 Jun 10
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74LV573
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
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Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
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Philips Semiconductors
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P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04453
Document order number:
Philips
Semiconductors
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