74LVC1G86GW [PHILIPS]
XOR Gate, CMOS, PDSO5,;
| 型号： | 74LVC1G86GW |
| 厂家： | 
PHILIPS SEMICONDUCTORS |
| 描述： | XOR Gate, CMOS, PDSO5, 栅 光电二极管 逻辑集成电路 石英晶振 |
| 文件： | 总16页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G86
2-input EXCLUSIVE-OR gate
Product specification
2002 Nov 15
Supersedes data of 2001 Apr 06
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 to 5.5 V
• High noise immunity
The 74LVC1G86 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
• Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
Inputs can be driven from either 3.3 or 5 V devices. These
features allow the use of these devices in a mixed
3.3 and 5 V environment.
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
This device is fully specified for partial Power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G86 provides the 2-input EXCLUSIVE-OR
function.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
3.7
UNIT
t
PHL/tPLH
propagation delay inputs A and B to VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
ns
ns
ns
ns
ns
pF
pF
output Y
V
CC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.5
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.8
CC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.3
V
VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 1.9
CI
input capacitance
5
CPD
power dissipation capacitance per
buffer
VCC = 3.3 V; notes 1 and 2
25
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
2002 Nov 15
2
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
A
B
Y
L
L
L
H
L
L
H
H
L
H
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
PINS
PACKAGE
MATERIAL
CODE
MARKING
RANGE
74LVC1G86GW
74LVC1G86GV
−40 to +125 °C
−40 to +125 °C
5
5
SC-88A
SC-74A
plastic
plastic
SOT353
SOT753
VH
V86
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
3
4
5
B
A
data input B
data input A
ground (0 V)
data output Y
supply voltage
GND
Y
VCC
2002 Nov 15
3
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
handbook, halfpage
B
A
1
2
3
5
4
V
Y
CC
handbook, halfpage
B
A
1
2
Y
4
86
GND
MNA038
MNA037
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
B
handbook, halfpage
1
2
= 1
4
Y
MNA039
A
MNA040
Fig.3 IEE/IEC logic symbol.
Fig.4 Logic diagram.
2002 Nov 15
4
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
V
VI
input voltage
0
5.5
VCC
5.5
+125
20
V
VO
output voltage
active mode
CC = 0 V; Power-down mode
0
V
V
0
V
Tamb
tr, tf
operating ambient temperature
input rise and fall times
−40
0
°C
VCC = 1.65 to 2.7 V
CC = 2.7 to 5.5 V
ns/V
ns/V
V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5
V
IIK
input diode current
input voltage
VI < 0
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
±50
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0
mA
V
active mode; notes 1 and 2
−0.5
VCC + 0.5
+6.5
±50
Power-down mode; notes 1 and 2 −0.5
V
IO
output source or sink current
VCC or GND current
VO = 0 to VCC
−
mA
mA
°C
mW
ICC, IGND
−
±100
+150
250
Tstg
PD
storage temperature
−65
−
power dissipation per package
for temperature range from
−40 to +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
2002 Nov 15
5
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.45
0.3
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
2.7
0.4
3.0
0.55
0.55
4.5
VOH
HIGH-level output
voltage
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
V
1.2
1.9
2.2
2.3
3.8
−
−
V
−
V
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
VI or VO = 5.5 V
±0.1
±0.1
±5
±10
µA
µA
Ioff
power OFF leakage
current
0
−
ICC
quiescent supply current VI = VCC or GND; 5.5
IO = 0
−
−
0.1
5
10
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0
2.3 to 5.5
500
2002 Nov 15
6
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +125 °C
VIH HIGH-level input voltage
1.65 to 1.95 0.65 × VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
V
V
V
V
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
2.0
0.7 × VCC
VIL
LOW-level input voltage
−
−
−
−
0.35 × VCC
0.7
0.8
0.3 × VCC
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
2.3
−
−
−
−
−
−
−
−
−
−
−
−
0.1
V
V
V
V
V
V
0.70
0.45
0.60
0.80
0.80
IO = 8 mA
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = VIH or VIL
IO = −100 µA
IO = −4 mA
IO = −8 mA
IO = −12 mA
IO = −24 mA
IO = −32 mA
2.7
3.0
4.5
VOH
HIGH-level output
voltage
1.65 to 5.5
1.65
2.3
V
CC − 0.1
−
−
−
−
−
−
−
−
−
V
0.95
1.7
1.9
2.0
3.4
−
−
V
−
V
2.7
−
V
3.0
−
V
4.5
−
V
ILI
input leakage current
VI = 5.5 V or GND 5.5
VI or VO = 5.5 V
±100
±200
µA
µA
Ioff
power OFF leakage
current
0
−
ICC
quiescent supply current VI = VCC or GND; 5.5
IO = 0
−
−
−
−
200
µA
µA
∆ICC
additional quiescent
supply current per pin
VI = VCC − 0.6 V;
IO = 0
2.3 to 5.5
5000
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2002 Nov 15
7
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns.
TEST CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Tamb = −40 to +85 °C
tPHL/tPLH propagation delay
inputs A and B to
output Y
see Figs 5 and 6 1.65 to 1.95 1.0
3.7
2.5
2.8
2.3
1.9
9.9
V
V
V
V
V
2.3 to 2.7
2.7
0.5
0.5
0.5
0.5
5.5
5.8
5.0
4.0
3.0 to 3.6
4.5 to 5.5
Tamb = −40 to +125 °C
tPHL/tPLH propagation delay
inputs A and B to
output Y
see Figs 5 and 6 1.65 to 1.95 1.0
−
−
−
−
−
13.0
7.0
7.5
6.5
5.5
V
V
V
V
V
2.3 to 2.7
2.7
0.5
0.5
0.5
0.5
3.0 to 3.6
4.5 to 5.5
AC WAVEFORMS
handbook, halfpage
A, B input
V
M
t
t
PHL
PLH
V
Y output
M
MNA041
INPUT
VCC
VM
VI
tr = tf
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
0.5 × VCC VCC
0.5 × VCC VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
1.5 V
1.5 V
2.7 V
2.7 V
3.0 to 3.6 V
4.5 to 5.5 V
0.5 × VCC VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 The inputs A and B to output Y propagation delay times.
8
2002 Nov 15
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
VCC
CL
RL
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
open
GND
GND
GND
GND
GND
2 × VCC
2 × VCC
6 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
open
open
open
open
2.7 V
2.7 V
VCC
3.0 to 3.6 V
4.5 to 5.5 V
6 V
2 × VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2002 Nov 15
9
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
PACKAGE OUTLINES
Plastic surface mounted package; 5 leads
SOT353
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
(2)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-88A
97-02-28
SOT353
2002 Nov 15
10
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
Plastic surface mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
p
1
2
3
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
SOT753
SC-74A
02-04-16
2002 Nov 15
11
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Nov 15
12
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
suitable
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Nov 15
13
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Nov 15
14
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74LVC1G86
NOTES
2002 Nov 15
15
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© Koninklijke Philips Electronics N.V. 2002
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Printed in The Netherlands
613508/03/pp16
Date of release: 2002 Nov 15
Document order number: 9397 750 10077
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