935314795557 [NXP]
RISC Microcontroller;
| 型号： | 935314795557 |
| 厂家： | 
NXP |
| 描述： | RISC Microcontroller 微控制器 外围集成电路 |
| 文件： | 总59页 (文件大小：2011K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: K12P64M50SF4
Rev. 4, 08/2013
Freescale Semiconductor
Data Sheet: Technical Data
K12P64M50SF4
K12 Sub-Family
Supports the following:
MK12DX128VLH5, MK12DX256VLH5,
MK12DN512VLH5
Features
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
Operating Characteristics
•
•
•
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– 128-bit unique identification (ID) number per chip
Human-machine interface
– General-purpose input/output
•
•
Performance
– Up to 50 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Analog modules
– 16-bit SAR ADC
– 12-bit DAC
– Two analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Memories and memory interfaces
– Up to 512 KB of program flash for devices without
FlexNVM.
– Up to 256 KB program flash for devices with
FlexNVM.
– 64 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 64 KB RAM
Timers
•
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel general purpose timers, one with
quadrature decoder functionality
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
– Serial programming interface (EzPort)
Clocks
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
Communication interfaces
– USB Device Charger detect
– SPI module
– Two I2C modules
– Four UART modules
– I2S module
•
– Multiple low-power modes to provide power
optimization based on application requirements
– 16-channel DMA controller, supporting up to 63
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2013 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
5.4 Thermal specifications.......................................................20
5.4.1 Thermal operating requirements...........................21
5.4.2 Thermal attributes.................................................21
6 Peripheral operating requirements and behaviors....................22
6.1 Core modules....................................................................22
6.1.1 JTAG electricals....................................................22
6.2 System modules................................................................25
6.3 Clock modules...................................................................25
6.3.1 MCG specifications...............................................25
6.3.2 Oscillator electrical specifications.........................27
6.3.3 32 kHz oscillator electrical characteristics.............29
6.4 Memories and memory interfaces.....................................30
6.4.1 Flash electrical specifications................................30
6.4.2 EzPort switching specifications.............................33
6.5 Security and integrity modules..........................................34
6.6 Analog...............................................................................34
6.6.1 ADC electrical specifications.................................34
6.6.2 CMP and 6-bit DAC electrical specifications.........38
6.6.3 12-bit DAC electrical characteristics.....................41
6.6.4 Voltage reference electrical specifications............44
6.7 Timers................................................................................45
6.8 Communication interfaces.................................................45
6.8.1 DSPI switching specifications (limited voltage
1.1 Determining valid orderable parts......................................3
2 Part identification......................................................................3
2.1 Description.........................................................................3
2.2 Format...............................................................................3
2.3 Fields.................................................................................3
2.4 Example............................................................................4
2.5 Small package marking.....................................................4
3 Terminology and guidelines......................................................5
3.1 Definition: Operating requirement......................................5
3.2 Definition: Operating behavior...........................................5
3.3 Definition: Attribute............................................................6
3.4 Definition: Rating...............................................................6
3.5 Result of exceeding a rating..............................................7
3.6 Relationship between ratings and operating
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
3.9 Typical value conditions....................................................9
4 Ratings......................................................................................9
4.1 Thermal handling ratings...................................................9
4.2 Moisture handling ratings..................................................10
4.3 ESD handling ratings.........................................................10
4.4 Voltage and current operating ratings...............................10
5 General.....................................................................................10
5.1 AC electrical characteristics..............................................11
5.2 Nonswitching electrical specifications...............................11
5.2.1 Voltage and current operating requirements.........11
5.2.2 LVD and POR operating requirements.................12
5.2.3 Voltage and current operating behaviors..............13
5.2.4 Power mode transition operating behaviors..........13
5.2.5 Power consumption operating behaviors..............14
5.2.6 EMC radiated emissions operating behaviors.......18
5.2.7 Designing with radiated emissions in mind...........19
5.2.8 Capacitance attributes..........................................19
5.3 Switching specifications.....................................................19
5.3.1 Device clock specifications...................................19
5.3.2 General switching specifications...........................20
range)....................................................................45
6.8.2 DSPI switching specifications (full voltage range).47
6.8.3 I2C switching specifications..................................49
6.8.4 UART switching specifications..............................49
6.8.5 Normal Run, Wait and Stop mode performance
over the full operating voltage range.....................49
6.8.6 VLPR, VLPW, and VLPS mode performance
over the full operating voltage range.....................51
7 Dimensions...............................................................................53
7.1 Obtaining package dimensions.........................................53
8 Pinout........................................................................................53
8.1 K12 Signal Multiplexing and Pin Assignments..................53
8.2 K12 Pinouts.......................................................................56
9 Revision History........................................................................57
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
2
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK12 and MK12 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K12
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
3
Part identification
Field
Description
Program flash memory size
Values
FFF
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK12DN512VLH5
2.5 Small package marking
In an effort to save space, small package devices use special marking on the chip. These
markings have the following format:
Q ## C F T PP
This table lists the possible values for each field in the part number for small packages
(not all combinations are valid):
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
Values
Field
Description
Q
Qualification status
Speed
• M = Fully qualified, general market flow
• P = Prequalification
C
F
• G = 50 MHz
Flash memory configuration
• G = 128 KB + Flex
• H = 256 KB + Flex
• 9 = 512 KB
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• MC = 121 MAPBGA
This tables lists some examples of small package marking along with the original part
numbers:
Original part number
Alternate part number
MK12DX256VLF5
MK12DN512VLH5
M12GHVLF
M12G9VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
8
Freescale Semiconductor, Inc.
Ratings
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
9
General
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
1
2
3
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
Max.
3.8
Unit
V
Digital supply voltage
IDD
Digital supply current
—
155
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog1, RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–0.3
VAIO
–0.3
VDD + 0.3
25
V
ID
–25
mA
V
VDDA
VREGIN
VBAT
VDD – 0.3
–0.3
VDD + 0.3
6.0
USB regulator input
V
RTC battery supply voltage
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
10
Freescale Semiconductor, Inc.
General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
1.71
Max.
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
—
V
I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
1
mA
-3
—
—
+3
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
11
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
12
Freescale Semiconductor, Inc.
General
Notes
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = - 9 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
100
mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
• @ full temperature range
• @ 25 °C
—
100
mA
—
—
1.0
0.1
μA
μA
1
IOZ
IOZ
Hi-Z (off-state) leakage current (per pin)
Total Hi-Z (off-state) leakage current (all input pins)
Internal pullup resistors
—
—
22
22
1
4
μA
μA
kΩ
kΩ
RPU
RPD
50
50
2
3
Internal pulldown resistors
1. Tested by ganged leakage method
2. Measured at Vinput = VSS
3. Measured at Vinput = VDD
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
13
General
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
μs
1
—
—
300
• 1.71 V/(VDD slew rate) ≤ 300 μs
1.7 V / (VDD
slew rate)
• 1.71 V/(VDD slew rate) > 300 μs
—
—
—
—
—
—
—
135
135
85
μs
μs
μs
μs
μs
μs
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
85
6
5.2
5.2
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8 V
• @ 3.0 V
—
—
12.98
12.93
14
mA
mA
13.8
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
14
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
• @ 1.8 V
• @ 3.0 V
• @ 25°C
• @ 125°C
—
17.04
19.3
mA
—
—
—
17.01
19.8
7.95
18.9
21.3
9.5
mA
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
2
5
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
—
—
5.88
7.4
mA
μA
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 50°C
320
360
410
610
754
436
489
620
1100
—
• @ 70°C
• @ 105°C
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
—
μA
6
7
8
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
1.1
—
—
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V
—
—
437
μA
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
7.33
14
24.2
32
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
28
48
110
280
IDD_LLS Low leakage stop mode current at 3.0 V
—
μA
μA
μA
3.14
6.48
4.8
• @ –40 to 25°C
• @ 50°C
• @ 70°C
28.3
44.6
71.3
13.85
55.53
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
2.19
4.35
3.4
• @ –40 to 25°C
• @ 50°C
• @ 70°C
4.35
24.6
45.3
8.92
• @ 105°C
35.33
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
1.77
2.81
3.1
• @ –40 to 25°C
• @ 50°C
• @ 70°C
13.8
22.3
34.2
5.20
• @ 105°C
19.88
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
15
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
μA
1.03
1.92
1.8
7.5
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
4.03
15.9
28.7
17.43
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
—
—
—
μA
μA
μA
0.543
1.36
1.1
with POR detect circuit enabled
• @ –40 to 25°C
• @ 50°C
7.58
14.3
24.1
3.39
• @ 70°C
• @ 105°C
16.52
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
0.359
1.03
0.95
6.8
with POR detect circuit disabled
• @ –40 to 25°C
• @ 50°C
2.87
15.4
25.3
• @ 70°C
• @ 105°C
15.20
IDD_VBAT Average current when CPU is not accessing RTC
9
0.91
1.1
1.5
4.3
1.1
1.35
1.85
5.7
registers at 3.0 V
• @ –40 to 25°C
• @ 50°C
• @ 70°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
4. Max values are measured with CPU executing DSP instructions
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode.
6. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash.
7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
9. Includes 32 kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
16
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
17
General
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors 1
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
19
21
19
11
L
dBμV
dBμV
dBμV
dBμV
—
2, 3
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
3, 4
1. This data was collected on a MK20DN128VLH5 64pin LQFP device.
2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
18
Freescale Semiconductor, Inc.
General
3. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 48 MHz, fBUS = 48MHz
4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
50
50
25
25
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fERCLK
fLPTMR_pin
Flash clock
1
External reference clock
LPTMR clock
16
25
16
12.5
4
fLPTMR_ERCLK LPTMR external reference clock
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
19
General
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
50
—
—
—
ns
ns
ns
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Port rise and fall time (high drive strength)
• Slew disabled
100
3
4
• 1.71 ≤ VDD ≤ 2.7V
—
—
13
7
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
—
—
36
24
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (low drive strength)
• Slew disabled
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
20
Freescale Semiconductor, Inc.
General
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
Die junction temperature
Ambient temperature
°C
°C
TA
105
5.4.2 Thermal attributes
Board type
Symbol
Description
64 LQFP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
65
°C/W
1, 2
resistance, junction
to ambient (natural
convection)
Four-layer (2s2p)
Single-layer (1s)
Four-layer (2s2p)
RθJA
Thermal
46
53
40
°C/W
°C/W
°C/W
1, 3
1,3
1,3
resistance, junction
to ambient (natural
convection)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
RθJMA
Thermal
resistance, junction
to ambient (200 ft./
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance, junction
to board
28
15
3
°C/W
°C/W
°C/W
4
5
6
Thermal
resistance, junction
to case
Thermal
characterization
parameter, junction
to package top
outside center
(natural
convection)
1.
2.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
3.
4.
5.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
6.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
0
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
—
—
8
25
25
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
22.1
22.1
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 4. Test clock input timing
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 5. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 6. Test Access Port timing
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 7. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.3
2
1
%fdco
%fdco
1, 2
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
fintf_ft
fintf_t
floc_low
floc_high
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
kHz
kHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
—
—
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20.97
MHz
3, 4
frequency range
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
5, 6
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
8
8
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
9
9
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
1.49
4.47
—
—
2.98
5.97
%
%
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol Description
tpll_lock Lock detector detection time
Min.
Typ.
Max.
Unit
Notes
—
—
150 × 10-6
+ 1075(1/
s
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
6.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDOSC
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
32
Typ.
Max.
40
Unit
Notes
—
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that—it remains within the limits of
DCO input clock frequency when divided by FRDIV.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between oscillator being enabled and OSCINIT bit in the MCG_S register being
set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz oscillator electrical characteristics
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
Parasitical capacitance of EXTAL32 and XTAL32
100
5
MΩ
pF
Cpara
—
7
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 17. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2 32 kHz oscillator frequency specifications
Table 18. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
vec_extal32 Externally provided input clock amplitude
700
VBAT
mV
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk256k Erase Block high-voltage time for 256 KB
—
13
113
904
ms
ms
1
1
—
104
1. Maximum time based on expectations at cycling end-of-life.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.2 Flash timing specifications — commands
Table 20. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk64k
• 64 KB data flash
—
—
—
—
0.9
1.7
ms
ms
trd1blk256k
• 256 KB program flash
trd1sec2k Read 1s Section execution time (flash sector)
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 64 KB data flash
30
tpgm4
145
2
tersblk64k
—
—
58
580
985
ms
ms
tersblk256k
• 256 KB program flash
122
tersscr
Erase Flash Sector execution time
Program Section execution time
• 512 bytes flash
—
14
114
ms
2
tpgmsec512
tpgmsec1k
tpgmsec2k
—
—
—
2.4
4.7
9.3
—
—
—
ms
ms
ms
• 1 KB flash
• 2 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
65
250
—
—
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
2000
30
2
1
tvfykey
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
• control code 0x02
• control code 0x04
• control code 0x08
Program Partition for EEPROM execution time
• 64 KB FlexNVM
tpgmpart64k
—
138
—
ms
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram64k
—
—
—
70
0.8
1.3
—
μs
ms
ms
• 32 KB EEPROM backup
• 64 KB EEPROM backup
1.2
1.9
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol Description
Byte-write to FlexRAM execution time:
Min.
Typ.
Max.
Unit
Notes
teewr8b32k
teewr8b64k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
—
385
475
1800
2000
μs
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b32k
teewr16b64k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
—
—
385
475
1800
2000
μs
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b32k
teewr32b64k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
—
—
630
810
2050
2250
μs
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 22. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. NVM reliability specifications (continued)
Symbol Description
Min.
Typ.1
Max.
—
Unit
years
cycles
Notes
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
20
10 K
100
50 K
—
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
Write endurance
5
50
—
—
years
years
20
100
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
writes
writes
writes
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ °C.
3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ °C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.2 EzPort switching specifications
Table 23. EzPort switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
—
ns
—
12
ns
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 8. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 24. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
Supply voltage
Supply voltage
Ground voltage
Absolute
—
0
Delta to VDD (VDD – VDDA
)
+100
+100
mV
mV
2
2
Delta to VSS (VSS – VSSA
)
0
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VREFH
VREFL
VADIN
ADC reference
voltage high
1.13
VDDA
VDDA
V
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
VREFL
VREFL
—
—
31/32 *
VREFH
• All other modes
• 16-bit mode
VREFH
CADIN
Input capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 9. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1.
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
2.4
clock source
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
—
0.7
-1.1 to +1.9
-0.3 to 0.5
• <12-bit modes
• 12-bit modes
—
—
0.2
1.0
INL
EFS
Integral non-
linearity
-2.7 to +1.9
-0.7 to +0.5
LSB4
LSB4
5
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
0.5
-4
Full-scale error
-5.4
-1.8
VADIN =
VDDA
-1.4
5
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1.
Min.
—
Typ.2
-1 to 0
—
Max.
—
Unit
Notes
EQ
Quantization
error
• 16-bit modes
• ≤13-bit modes
LSB4
—
0.5
ENOB
Effective number 16-bit differential mode
6
of bits
• Avg = 32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
—
—
–94
-85
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
82
78
95
—
—
dB
16-bit single-ended mode
• Avg = 32
90
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
8. ADC conversion clock < 3 MHz
Figure 10. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 27. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
TA
Desciption
Min.
1.71
1.13
Max.
3.6
Unit
V
Notes
Supply voltage
Reference voltage
Temperature
3.6
V
1
Operating temperature
range of the device
°C
CL
IL
Output load capacitance
Output load current
—
—
100
1
pF
2
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 28. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
330
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
—
100
15
0.7
—
1200
200
30
μA
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
1
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
100
VDACR
8
mV
mV
LSB
LSB
LSB
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
—
2
3
4
Differential non-linearity error — VDACR > 2
V
—
1
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 14. Typical INL error vs. digital code
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Figure 15. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 29. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
1.71
3.6
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 30. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Bandgap only current
—
—
80
µA
µV
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 31. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 32. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
6.8.1 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 33. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
15
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 16. DSPI classic SPI timing — master mode
Table 34. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 34. Slave mode DSPI timing (limited voltage range) (continued)
Num
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK input high/low time
Min.
Max.
Unit
ns
(tSCK/2) − 2
(tSCK/2) + 2
DSPI_SCK to DSPI_SOUT valid
—
0
10
—
—
—
14
14
ns
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
ns
2
ns
7
ns
—
—
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 17. DSPI classic SPI timing — slave mode
6.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 35. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
Table 35. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
20.5
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 18. DSPI classic SPI timing — master mode
Table 36. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
6.25
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
19
19
ns
ns
2
ns
7
ns
—
—
ns
ns
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
Last data
DSPI_SOUT
Data
Data
DS13
First data
DSPI_SIN
Figure 19. DSPI classic SPI timing — slave mode
6.8.3 I2C switching specifications
See General switching specifications.
6.8.4 UART switching specifications
See General switching specifications.
6.8.5 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 37. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
80
55%
—
MCLK period
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
S7
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
ns
I2S_TX_BCLK to I2S_TXD valid
—
15
Table continues on the next page...
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
Table 37. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S8
S9
I2S_TX_BCLK to I2S_TXD invalid
0
—
—
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 20. I2S/SAI timing — master modes
Table 38. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
2
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
29
—
—
—
21
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 21. I2S/SAI timing — slave modes
6.8.6 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 39. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
45%
—
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
75
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 22. I2S/SAI timing — master modes
Table 40. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
2
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
87
—
—
—
72
ns
ns
ns
ns
ns
30
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
52
Freescale Semiconductor, Inc.
Dimensions
S11
S12
I2S_TX_BCLK/
S12
I2S_RX_BCLK (input)
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S19
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 23. I2S/SAI timing — slave modes
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
64-pin LQFP
Then use this document number
98ASS23234W
8 Pinout
8.1 K12 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
• The analog input signals ADC0_SE10, ADC0_SE11,
ADC0_DP1, and ADC0_DM1 are available only for K11,
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
53
Pinout
K12, K21, and K22 devices and are not present on K10 and
K20 devices.
• The TRACE signals on PTE0, PTE1, PTE2, PTE3, and
PTE4 are available only for K11, K12, K21, and K22
devices and are not present on K10 and K20 devices.
• If the VBAT pin is not used, the VBAT pin should be left
floating. Do not connect VBAT pin to VSS.
• The FTM_CLKIN signals on PTB16 and PTB17 are
available only for K11, K12, K21, and K22 devices and is
not present on K10 and K20 devices. For K22D devices
this signal is on ALT4, and for K22F devices, this signal is
on ALT7.
• The FTM0_CH2 signal on PTC5/LLWU_P9 is available
only for K11, K12, K21, and K22 devices and is not
present on K10 and K20 devices.
• The I2C0_SCL signal on PTD2/LLWU_P13 and
I2C0_SDA signal on PTD3 are available only for K11,
K12, K21, and K22 devices and are not present on K10 and
K20 devices.
64
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
1
2
ADC0_SE10
ADC0_SE11
ADC0_SE10
ADC0_SE11
PTE0
UART1_TX
UART1_RX
TRACE_CLKOUT I2C1_SDA
RTC_CLKOUT
PTE1/
TRACE_D3
I2C1_SCL
LLWU_P0
3
4
VDD
VDD
VSS
VSS
5
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
PTE16
PTE17
PTE18
PTE19
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_TX
FTM_CLKIN0
FTM_CLKIN1
I2C0_SDA
FTM0_FLT3
6
UART2_RX
LPTMR0_ALT3
7
UART2_CTS_b
UART2_RTS_b
8
I2C0_SCL
9
10
11
12
13
14
15
16
17
VREFH
VREFH
VREFL
VREFL
VSSA
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
54
Freescale Semiconductor, Inc.
Pinout
64
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
19
20
21
22
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_CTS_b/
UART0_COL_b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
23
24
JTAG_TDI/
EZP_DI
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
JTAG_TDO/
TRACE_SWO/
EZP_DO
JTAG_TDO/
TRACE_SWO
EZP_DO
25
26
JTAG_TMS/
SWD_DIO
PTA3
UART0_RTS_b
FTM0_CH0
FTM0_CH1
JTAG_TMS/
SWD_DIO
NMI_b/
PTA4/
NMI_b
EZP_CS_b
EZP_CS_b
LLWU_P3
27
28
29
DISABLED
DISABLED
DISABLED
PTA5
FTM0_CH2
FTM1_CH0
FTM1_CH1
I2S0_TX_BCLK
I2S0_TXD0
JTAG_TRST_b
FTM1_QD_PHA
FTM1_QD_PHB
PTA12
PTA13/
I2S0_TX_FS
LLWU_P4
30
31
32
33
34
35
VDD
VDD
VSS
VSS
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
LPTMR0_ALT1
FTM1_QD_PHA
RESET_b
ADC0_SE8
RESET_b
ADC0_SE8
PTB0/
I2C0_SCL
FTM1_CH0
LLWU_P5
36
37
38
ADC0_SE9
ADC0_SE12
ADC0_SE13
ADC0_SE9
ADC0_SE12
ADC0_SE13
PTB1
PTB2
PTB3
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH1
FTM1_QD_PHB
FTM0_FLT3
UART0_RTS_b
UART0_CTS_b/
UART0_COL_b
FTM0_FLT0
39
40
41
42
43
44
DISABLED
DISABLED
DISABLED
DISABLED
ADC0_SE14
ADC0_SE15
PTB16
PTB17
PTB18
PTB19
PTC0
UART0_RX
UART0_TX
EWM_IN
FTM_CLKIN0
FTM_CLKIN1
EWM_OUT_b
FTM2_CH0
I2S0_TX_BCLK
I2S0_TX_FS
FTM2_CH1
ADC0_SE14
ADC0_SE15
SPI0_PCS4
SPI0_PCS3
PDB0_EXTRG
UART1_RTS_b
I2S0_TXD1
I2S0_TXD0
PTC1/
LLWU_P6
FTM0_CH0
FTM0_CH1
FTM0_CH2
45
46
47
ADC0_SE4b/
CMP1_IN0
ADC0_SE4b/
CMP1_IN0
PTC2
SPI0_PCS2
SPI0_PCS1
UART1_CTS_b
UART1_RX
I2S0_TX_FS
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
CLKOUT
I2S0_TX_BCLK
VSS
VSS
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
55
Pinout
64
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
48
49
VDD
VDD
DISABLED
DISABLED
CMP0_IN0
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
CMP1_OUT
CMP0_OUT
I2S0_MCLK
50
51
PTC5/
LLWU_P9
LPTMR0_ALT2
PDB0_EXTRG
I2S0_RXD0
FTM0_CH2
CMP0_IN0
PTC6/
LLWU_P10
I2S0_RX_BCLK
52
53
54
55
56
CMP0_IN1
CMP0_IN2
CMP0_IN3
DISABLED
DISABLED
CMP0_IN1
CMP0_IN2
CMP0_IN3
PTC7
PTC8
PTC9
PTC10
I2S0_RX_FS
I2S0_MCLK
I2S0_RX_BCLK
I2S0_RX_FS
I2S0_RXD1
FTM2_FLT0
I2C1_SCL
I2C1_SDA
PTC11/
LLWU_P11
57
DISABLED
PTD0/
SPI0_PCS0
UART2_RTS_b
LLWU_P12
58
59
ADC0_SE5b
DISABLED
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_b
UART2_RX
PTD2/
SPI0_SOUT
I2C0_SCL
LLWU_P13
60
61
DISABLED
PTD3
SPI0_SIN
UART2_TX
I2C0_SDA
FTM0_CH4
ADC0_SE21
ADC0_SE21
ADC0_SE6b
ADC0_SE7b
ADC0_SE22
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_b
EWM_IN
62
63
64
ADC0_SE6b
ADC0_SE7b
ADC0_SE22
PTD5
SPI0_PCS2
SPI0_PCS3
CMT_IRO
UART0_CTS_b/
UART0_COL_b
FTM0_CH5
FTM0_CH6
FTM0_CH7
EWM_OUT_b
FTM0_FLT0
FTM0_FLT1
PTD6/
LLWU_P15
UART0_RX
PTD7
UART0_TX
8.2 K12 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
56
Freescale Semiconductor, Inc.
Revision History
PTE0
PTE1/LLWU_P0
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
VSS
2
3
PTC3/LLWU_P7
PTC2
VSS
4
PTE16
5
PTC1/LLWU_P6
PTC0
PTE17
6
PTE18
7
PTB19
PTE19
8
PTB18
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
9
PTB17
10
11
12
13
14
15
16
PTB16
PTB3
PTB2
PTB1
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
VREFL
VSSA
Figure 24. K12 64 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
Freescale Semiconductor, Inc.
57
Revision History
Table 41. Revision History
Rev. No.
Date
6/2012
6/2012
Substantial Changes
1
Alpha customer release.
1.1
In Table 6, "Power consumption operating behaviors", changed the units of IDD_VLLS2
IDD_VLLS1, IDD_VLLS0, and IDD_VBAT from nA to μA.
,
2
7/2012
• Updated section "Power consumption operating behaviors".
• Updated section "Flash timing specifications — program and erase".
• Updated section "Flash timing specifications — commands".
• Removed the 32K ratio from "Write endurance" in section "Reliability specifications".
• Updated IDDstby maximum value in section "VREG electrical specifications".
• Added the charts in section "Diagram: Typical IDD_RUN operating behavior".
3
4
8/2012
8/2013
• Updated section "Power consumption operating behaviors".
• Updated section "EMC radiated emissions operating behaviors".
• Updated section "MCG specifications".
• Added applicable notes in section "Signal Multiplexing and Pin Assignments".
• Updated section "Power consumption operating behaviors"
• Updated section "MCG specifications"
• Updated section "16-bit ADC operating conditions"
• Added section "Small package marking"
K12 Sub-Family Data Sheet, Rev. 4, 08/2013.
58
Freescale Semiconductor, Inc.
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© 2012-2013 Freescale Semiconductor, Inc.
Document Number: K12P64M50SF4
Rev. 4
08/2013
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