BF1102,115 [NXP]
N-channel dual-gate MOSFET TSSOP 6-Pin;
| 型号： | BF1102,115 |
| 厂家： | 
NXP |
| 描述： | N-channel dual-gate MOSFET TSSOP 6-Pin |
| 文件： | 总14页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
BF1102; BF1102R
Dual N-channel dual gate
MOS-FETs
Product specification
2000 Apr 11
Supersedes data of 1999 Jul 01
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
FEATURES
PINNING - SOT363
PIN
Two low noise gain controlled amplifiers in a single
package
DESCRIPTION
BF1102
BF1102R
Specially designed for 5 V applications
Superior cross-modulation performance during AGC
High forward transfer admittance
1
2
3
4
5
6
gate 1 (1)
gate 1 (1)
gate 2 (1 and 2) source (1 and 2)
drain (1)
drain (2)
drain (1)
drain (2)
High forward transfer admittance to input capacitance
ratio.
source (1 and 2) gate 2 (1 and 2)
gate 1 (2)
gate 1 (2)
APPLICATIONS
Gain controlled low noise amplifier for VHF and UHF
applications such as television tuners and professional
communications equipment.
g
(1, 2)
handbook, halfpage
2
6
5
4
DESCRIPTION
g
(1)
(2)
AMP1
d (1)
d (2)
1
The BF1102 and BF1102R are both two equal dual gate
MOS-FETs which have a shared source pin and a shared
gate 2 pin. Both devices have interconnected source and
substrate; an internal bias circuit enables DC stabilization
and a very good cross-modulation performance at 5 V
supply voltage; integrated diodes between the gates and
source protect against excessive input voltage surges.
Both devices have a SOT363 micro-miniature plastic
package.
g
AMP2
1
1
BF1102 marking code: W1.
BF1102R marking code: W2-.
2
3
s (1, 2)
MBL029
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Per MOS-FET unless otherwise specified
VDS
ID
drain-source voltage
7
V
drain current (DC)
40
200
mA
mW
mS
pF
Ptot
yfs
Cig1-s
Crss
F
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
Ts 102 C; note 1
ID = 15 mA
36
43
2.8
30
2
ID = 15 mA
3.6
50
2.8
f = 1 MHz
fF
f = 800 MHz
dB
Xmod
Tj
cross-modulation
input level for k = 1% at 40 dB AGC
100
dBV
C
operating junction temperature
150
Note
1. Ts is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2000 Apr 11
2
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET unless otherwise specified
VDS
ID
drain-source voltage
drain current (DC)
7
V
40
mA
mA
mA
mW
C
IG1
IG2
Ptot
Tstg
Tj
gate 1 current
10
10
200
+150
150
gate 2 current
total power dissipation
storage temperature
operating junction temperature
Ts 102 C
65
C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-s
thermal resistance from junction to soldering point
240
K/W
MGS359
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
50
100
150
200
T
(°C)
s
Fig.2 Power derating curve.
2000 Apr 11
3
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
STATIC CHARACTERISTICS
Tj = 25 C unless otherwise specified.
SYMBOL
Per MOS-FET unless otherwise specified
V(BR)DSS drain-source breakdown voltage
PARAMETER
CONDITIONS
MIN. MAX. UNIT
VG1-S = VG2-S = 0; ID = 10 A
7
V
V(BR)G1-SS gate 1-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA
V(BR)G2-SS gate 2-source breakdown voltage VGS = VDS = 0; IG2-S = 5 mA
6
15
15
1.5
1.5
1
V
6
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VDS = 5 V; VG2-S = 4 V; ID = 100 A
VDS = 5 V; VG1-S = 4 V; ID = 100 A
0.5
0.5
0.3
0.3
V
V
V
1.2
20
50
20
V
VG2-S = 4 V; VDS = 5 V; RG = 120 k; note 1 12
mA
nA
nA
IG1-S
gate 1 cut-off current
VG1-S = 5 V; VG2-S = VDS = 0
VG2-S = 5 V; VG1-S = VDS = 0
IG2-S
gate 2 cut-off current
Note
1. RG1 connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Per MOS-FET unless otherwise specified (note 1)
yfs
Cig1-ss
Cig2-ss
Coss
Crss
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
Tj = 25 C
36
2
43
2.8
50
3.6
7
mS
pF
pF
pF
fF
f = 1 MHz
f = 1 MHz; (note 2)
f = 1 MHz
1.6
30
2
2.5
50
2.8
reverse transfer capacitance
noise figure
f = 1 MHz
F
f = 800 MHz; YS = YS opt
fw = 50 MHz; funw = 60 MHz; (note 3)
input level for k = 1% at 0 dB AGC
input level for k = 1% at 40 dB AGC
dB
Xmod
cross-modulation
85
dBV
dBV
100
Notes
1. Not used MOS-FET: VG1-S = 0; VDS = 0.
2. Gate 2 capacitance of both MOS-FETs.
3. Measured in test circuit of Fig.20.
2000 Apr 11
4
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
ALL GRAPHS FOR ONE MOS-FET
MGS361
MGS360
30
30
handbook, halfpage
handbook, halfpage
V
= 4 V
3.5 V
G2-S
2.5 V
I
V
= 1.5 V
I
D
G1-S
D
(mA)
(mA)
3 V
2 V
1.4 V
20
20
1.3 V
1.2 V
1.5 V
10
10
1.1 V
1 V
1 V
2.0
0
0
0
2
4
6
8
10
(V)
0
0.4
0.8
1.2
1.6
2.4
V
V
(V)
DS
G1-S
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 C.
Tj = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MGS362
MGS363
160
handbook, halfpage
50
handbook, halfpage
V
= 4 V
V
= 4 V
G2-S
G2-S
I
|y
|
G1
(μA)
fs
(mS)
40
3.5 V
3 V
3 V
3.5 V
120
30
20
10
0
80
40
2.5 V
2 V
2.5 V
2 V
0
0
0.5
1
1.5
2
2.5
(V)
0
10
20
30
I
(mA)
V
D
G1-S
VDS = 5 V.
VDS = 5 V.
Tj = 25 C.
Tj = 25 C.
Fig.5 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.6 Forward transfer admittance as a function
of drain current; typical values.
2000 Apr 11
5
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MGS364
MGS365
25
15
handbook, halfpage
handbook, halfpage
I
D
(mA)
I
D
(mA)
20
10
15
10
5
5
0
0
0
0
20
40
60
1
2
3
4
5
(V)
I
(μA)
G1
V
GG
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.20.
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
Fig.7 Drain current as a function of gate 1 current;
typical values.
Fig.8 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MGS366
MGS367
30
20
handbook, halfpage
68 kΩ
82 kΩ
R
= 47 kΩ
handbook, halfpage
G1
I
D
(mA)
V
= 5 V
4.5 V
4 V
I
G1-S
D
(mA)
100 kΩ
120 kΩ
16
20
3.5 V
3 V
150 kΩ
180 kΩ
220 kΩ
12
8
10
4
0
0
0
2
4
6
8
10
0
2
4
6
V
(V)
G2-S
V
= V
(V)
DS
GG
VG2-S = 4 V; Tj = 25 C.
G1 connected to VGG; see Fig.20.
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.20.
R
Fig.9 Drain current as a function of gate 1 (= VGG
)
Fig.10 Drain current as a function of gate 2
voltage; typical values.
and drain supply voltage; typical values.
2000 Apr 11
6
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MGS368
MCD968
40
0
handbook, halfpage
handbook, halfpage
gain
I
reduction
(dB)
G1
(μA)
V
= 5 V
4.5 V
G1-S
−10
30
20
10
0
−20
−30
4 V
3.5 V
3 V
−40
−50
0
2
4
6
0
1
2
3
4
V
(V)
G2-S
V
(V)
AGC
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.20.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C;
RG1 = 120 k (connected to VGG); see Fig.20.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.12 Typical gain reduction as a function of the
AGC voltage; see Fig.20.
MGS369
MCD969
120
20
handbook, halfpage
handbook, halfpage
I
V
D
(mA)
16
unw
(dBμV)
110
12
8
100
90
4
0
80
0
20
40
60
0
10
20
30
40
50
gain reduction (dB)
gain reduction (dB)
VDS = 5 V; VGG = 5 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C;
RG1 = 120 k (connected to VGG); see Fig.20.
VDS = 5 V; VGG = 5 V; f = 50 MHz; Tamb = 25 C;
RG1 = 120 k (connected to VGG); see Fig.20.
Fig.13 Unwanted voltage for 1% cross-modulation
as a function of gain reduction;
typical values.
Fig.14 Drain current as a function of gain
reduction; typical values.
2000 Apr 11
7
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MGS370
MCD970
3
2
3
10
10
−10
handbook, halfpage
handbook, halfpage
y
ϕ
(deg)
y
is
rs
rs
(mS)
(mS)
ϕ
rs
2
2
10
−10
10
y
rs
b
is
1
−10
−1
10
g
is
−1
10
10
1
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
ID = 15 mA; Tamb = 25 C.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MGS372
MCD971
2
2
10
10
10
handbook, halfpage
handbook, halfpage
y
|y
|
os
−ϕ
|y
|
fs
(mS)
fs
(deg)
fs
(mS)
b
os
ϕ
fs
10
10
1
g
os
−1
1
3
10
1
10
2
3
2
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
ID = 15 mA; Tamb = 25 C.
ID = 15 mA; Tamb = 25 C.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2000 Apr 11
8
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
MCD972
0
handbook, halfpage
crosstalk
level
(dB)
−20
−40
−60
−80
0
200
400
600
800
1000
f (MHz)
Active amplifier: VDS = 5 V; VG2 = 4 V; ID = 15 mA.
Non-active amplifier: VDS = VG1-S = 0 V.
Source and load impedances: 50 (both amplifiers).
amb = 25 C.
T
Fig.19 Crosstalk as a function of frequency:
Output level of non-active amplifier related
to output level of active amplifier; typical
values.
V
AGC
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
R
50 Ω
L1
≈2.2 μH
L
C2
DUT
C4
4.7 nF
R
GEN
50 Ω
R2
50 Ω
R
G1
4.7 nF
V
V
V
I
GG
DS
MGS315
Fig.20 Cross-modulation test set-up (for one MOS-FET).
9
2000 Apr 11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.987
0.981
0.961
0.933
0.899
0.867
0.834
0.805
0.779
0.758
0.740
5.6
4.069
4.042
3.926
3.778
3.593
3.412
3.216
3.010
2.804
2.656
2.509
173.5
167.0
154.4
142.4
130.6
119.6
109.2
99.0
0.001
0.002
0.005
0.006
0.007
0.007
0.007
0.006
0.007
0.007
0.009
95.4
81.3
75.8
69.6
65.6
64.4
67.5
78.7
92.7
120.7
125.5
0.986
0.983
0.976
0.960
0.945
0.928
0.914
0.901
0.886
0.889
0.890
3.0
6.0
11.1
21.9
32.1
42.0
51.1
59.9
67.9
75.7
82.1
89.0
12.0
17.7
23.2
29.1
34.1
39.8
45.1
49.7
55.7
89.2
80.3
69.9
Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C
opt
f
Fmin
(dB)
Rn
()
(MHz)
(ratio)
(deg)
61.61
800
2
0.621
25.85
2000 Apr 11
10
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
PACKAGE OUTLINE
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
2000 Apr 11
11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DEFINITIONS
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reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Product specification The information and data
provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
agreement be valid in which the NXP Semiconductors
product is deemed to offer functions and qualities beyond
those described in the Product data sheet.
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not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
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accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
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document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
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the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
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Applications Applications that are described herein for
any of these products are for illustrative purposes only.
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warranty that such applications will be suitable for the
specified use without further testing or modification.
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Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
2000 Apr 11
12
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FETs
BF1102; BF1102R
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
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Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
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sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
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applications.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
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Semiconductors’ standard warranty and NXP
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that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
2000 Apr 11
13
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/03/pp14
Date of release: 2000 Apr 11
相关型号：
BF1102RT/R
TRANSISTOR 2 CHANNEL, UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, MICRO MINIATURE, PLASTIC, SC-88, 6 PIN, FET RF Small Signal
NXP
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