BUK9775-55 [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | BUK9775-55 |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总8页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
55
11.7
19
150
75
V
A
W
˚C
mΩ
RDS(ON)
resistance
VGS = 5 V
general
purpose
switching
applications.
PINNING - SOT186A
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
case
gate
2
drain
g
3
source
case isolated
s
1
2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
-
-
-
-
-
-
-
-
55
55
10
11.7
7.4
47
V
V
V
A
A
A
W
˚C
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Ptot
Tstg, Tj
19
150
- 55
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
-
2
kV
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction to
heatsink
with heatsink compound
-
6.5
K/W
Rth j-a
Thermal resistance junction to
ambient
in free air
55
-
K/W
April 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
55
50
1
0.6
-
-
-
-
-
10
-
-
-
2
V
V
V
V
V
µA
µA
µA
µA
V
Tj = -55˚C
-
1.5
-
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
-
-
2.3
10
100
1
5
-
IDSS
Zero gate voltage drain current VDS = 55 V; VGS = 0 V;
0.05
-
0.02
Tj = 150˚C
Tj = 150˚C
IGSS
Gate source leakage current
VGS = ±5 V; VDS = 0 V
IG = ±1 mA;
±V(BR)GSS
RDS(ON)
Gate-source breakdown
voltage
Drain-source on-state
resistance
-
VGS = 5 V; ID = 7 A
-
-
58
-
75
139
mΩ
mΩ
Tj = 150˚C
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 10 A
5
10
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
500
110
60
650
135
85
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 10 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
-
-
-
10
47
28
33
15
70
40
45
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
4.5
7.5
-
-
nH
nH
ISOLATION LIMITING VALUE AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VISOL R.M.S isolation voltage from all f = 50-60Hz; sinusoidal waveform;
-
-
2500
V
three terminals to external
heatsink
R.H.≤65% clean & dustfree
CISOL
Capacitance from T2 to
external heatsink
f = 1 MHZ
-
10
-
pF
April 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
11.7
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
47
1.2
A
V
IF = 11.7 A; VGS = 0 V
0.95
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 11.7 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
-
32
0.12
-
-
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 10 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
-
-
30
mJ
April 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
Normalised Power Derating
Zth/ (K/W)
PD%
10
1
120
110
100
90
80
70
60
50
40
30
20
10
0
0.5
0.2
0.1
0.05
p
t
0.02
0
p
t
P
D
D =
T
0.1
0.01
t
T
0
20
40
60
80
Tmb /
100
120
140
1.0E-06
0.0001
0.01
t/s
1
100
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
50
ID/A
40
10.0
8.0
120
110
100
90
80
70
60
50
40
30
20
10
0
VGS/V =
6.0
5.4
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
30
20
10
0
2.4
2.2
2.0
0
20
40
60
80
Tmb /
100
120
140
0
2
4
6
8
10
C
VDS/V
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
100
RDS(ON)/mOhm
90
tp =
VGS/V =
85
ID/A
RDS(ON) = VDS/ID
4.2
4.4
4
1 uS
80
75
70
65
60
55
10
5
4.6
4.8
10 uS
100uS
DC
1
1 mS
10 mS
100 mS
0.1
1
10
100
5
10
15
20
25
VDS/V
ID/A
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
April 1998
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
25
VGS(TO) / V
max.
B
2.5
2
ID/A
20
typ.
15
10
5
1.5
1
min.
0.5
Tj/C =
150
25
0
0
-100
-50
0
50
Tj / C
100
150
200
0
1
2
3
4
5
VGS/V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Transconductance, gfs (S)
15
Sub-Threshold Conduction
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
14
13
12
11
10
9
2%
typ
98%
8
7
6
5
0
5
10
15
20
25
Drain current, ID (A)
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
1
.9
.8
.7
.6
.5
.4
.3
.2
.1
0
Rds(on) normalised to 25degC
a
2.5
2
1.5
1
Ciss
hTounsadFp
Coss
Crss
0.5
-100
-50
0
50
100
150
200
0.01
0.1
1
10
100
VDS/V
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
April 1998
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
6
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
VGS/V
5
VDS = 14V
4
3
2
1
0
VDS = 44V
20
40
60
80
100
120
140
0
2
4
6
8
10
12
QG/nC
Tmb / C
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 20 A; parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 17 A
100
VDD
IF/A
80
+
L
VDS
60
-
Tj/C =
150
25
VGS
-ID/100
40
20
0
T.U.T.
0
R 01
RGS
shunt
0
0.5
1
1.5
VSDS/V
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
VDD
+
-
RD
VDS
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
April 1998
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
2.5
6.4
0.8 max. depth
15.8
max
seating
plane
15.8
max.
19
max.
3 max.
not tinned
3
2.5
13.5
min.
1
2
3
M
0.4
1.0 (2x)
0.6
2.5
0.9
0.7
2.54
0.5
5.08
1.3
Fig.18. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
April 1998
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
April 1998
8
Rev 1.000
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