MC33393YFTB [NXP]
IC,MOTOR CONTROLLER,QFP,52PIN;
| 型号： | MC33393YFTB |
| 厂家： | 
NXP |
| 描述： | IC,MOTOR CONTROLLER,QFP,52PIN 电动机控制 |
| 文件： | 总16页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Order this document from Analog Marketing: MC33393/D
Rev 0, 08/2002
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33393
MUX Stepper Motor Controller
The 33393 is a single-chip stepper motor controller with single-wire bus
interface for automotive and industrial applications. It is a member of
Motorola’s 68HC05 system chip family and combines a compact CPU core
with a shell of 40 V peripherals. The 33393 offers a highly flexible and cost-
effective solution for application control and protocol handling.
MUX STEPPER MOTOR
CONTROLLER
The digital core of the device includes the HC05 8-bit CPU with RAM, ROM,
EEPROM, and an on-chip oscillator. The 40 V analog peripheries include an
integrated voltage regulator with power-on reset, a dual H-bridge with stall
detection to control a stepper motor, and a single-wire bus interface.
Features
• HC05 8-Bit CPU
• 1008 Bytes Program EEPROM
• 64 Bytes RAM
FTB SUFFIX
PLASTIC PACKAGE
• 240 Bytes Monitor ROM
CASE 1336-01
• 16-Bit Timer with Capture and Compare
• Multipurpose Core Timer
(52-LEAD LQFP EXPOSED PAD)
• On-Chip Internal Voltage Regulator
• Low-Power Mode
ORDERING INFORMATION
Temperature
• Low-Voltage Reset (LVR) on VDD
• Overvoltage Shutdown for Half-Bridges
• On-Chip Oscillator, Software Trimmable
• Single-Wire Bus Interface (ISO9141or MI-BUS)
• Four Universal 6.0 Ω Push-Pull Outputs with Current Control
• Diagnostic Functions
Device
MC33393YFTB
Package
LQFP52 EP
Range (TJ)
-40 to 125°C
• -40°C to 125°C Junction Temperature
33393 Simplified Application Diagram
VSUP
C
33393
D
VSUP
R1
Stepper
Coil1
R
Motor
L1
Single-Wire Interface
SIO
L2
Coil2
C1
R2
GND
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© Motorola, Inc. 2002
Freescale Semiconductor, Inc.
PROGRAM EEPROM — 1.0 K BYTES
USER VECTORS — 16 BYTES
MONITOR ROM — 240 BYTES
TDAT
TCLK
USER RAM — 64 BYTES
ARITHMETIC/LOGIC
CPU CONTROL
UNIT
ACCUMULATOR
M68HC05
MCU
INDEX REGISTER
RESET
STACK POINTER
0 0 0 0 0 0 0 1 1
0
PROGRAM COUNTER
SIO/TIMER
CONDITION CODE REGISTER
1 1 1 H I N C Z
OSCILLATOR
CLOCK
DIVIDE
V
SUP
CORE TIMER
BY 2
GENERATION
R2
L2
L1
R1
16-BIT
TIMER
CALIBRATION
GND
V
SUP
BILBO
POR
VSUP
GND
VOLTAGE
GND
REGULATOR
V
SUP
LVR
GND
V
SUP
GND
Figure 1. 33393 Simplified Block Diagram
33393
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1
2
3
4
5
6
7
8
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
GND
GND
9
R1
L1
L2
10
11
12
13
GND
R2
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
1, 2, 4, 6, 7, 8, 12, 13,
14, 15, 17, 19, 20,
21, 22, 25, 26, 27,
28, 30, 32, 33, 34,
35, 37, 38, 39, 40,
41, 42, 44, 45, 46,
47, 48, 50, 51, 52
NC
No connect
3, 5, 11, 16, 24, 36
GND
R1
Ground. All GND pins must be connected together.
Half-bridge output1
9
10
18
23
29
31
43
49
L1
Half-bridge output2
SIO
Single-wire bus input/output
Supply voltage
V
SUP
R2
L2
Half-bridge output3
Half-bridge output4
TDAT
TCLK
Testport communication. Used for factory test only.
Testport clock. Used for factory test only.
33393
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MAXIMUM RATINGS
Voltages are referenced to GND.
Rating
Symbol
Min
Typ
Max
Unit
ELECTRICAL RATINGS
Power Supply Voltage
V
V
SUP
Static Destruction Proof
Dynamic Destruction Proof t < 0.5 s
-0.3
-0.3
–
–
26
40
Static Half-Bridges Output Current
@ -40°C
mA
V
–
–
–
–
–
–
(Note 1)
175
@ 85°C (Ambient Temperature)
SIO Bus Line
Static
V
V
-16
–
–
–
28
40
BUS
BUS
Dynamic t < 0.5 s
Testport
TDAT
V
V
V
V
-0.3
-0.3
–
–
V
+0.3
TDAT
DD
(Note 2)
11
TCLK
TCLK
ESD Voltage Capability (HBM: C=100 pF, R=1500 Ω)
Application Pins (R1, L1, R2, L2, SIO, V
Test Pins (TDAT, TCLK)
, GND)
V
±4000
±2000
–
–
–
–
SUP
ESD
ESD
V
THERMAL RATINGS
Storage Temperature
T
-55
-40
-40
–
–
–
125
125
85
–
°C
°C
S
Operating Junction Temperature
Operating Ambient Temperature (Note 3)
Junction to Board (Note 4)
T
J
T
–
°C
A
R
8.5
0.6
3
°C/W
°C/W
°C/W
θJ-B
θJ-C
Junction to Case (Note 5)
R
–
–
Junction to Package Top (Natural convection) (Note 6)
R
–
–
θJ-C(top)
Notes
1. Maximum current is limited by the low-side current limitation (see Power Stages table, page 8).
2. is an internal voltage (typically 5.3 V).
3. For convenience only, temperature range is limited by the junction temperature.
V
DD
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board near the package.
5. Thermal resistance between the die and the exposed pad on the bottom of the package.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC
JESD51-2.
33393
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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ELECTRICAL CHARACTERISTICS
TJ from -40°C to 125°C, VSUP from 9.0 V to 16 V, bus frequency @ 2.6 MHz, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Operating Range
Static
V
V
SUP
9.0
-0.3
12
–
16
40
Dynamic t < 0.5 s
Supply Current
mA
RUN (HBON bit set [System Control Register], Timer on, COP on, ISO
transmitter on)
I
–
–
–
10
2.5
SUP-RUN
STOP (HBON bit set [System Control Register], Timer off, COP off, ISO
transmitter off)
I
1.9
SUP-STOP
High-Voltage Half-Bridge Switch Off Threshold
V
18.7
19.7
20.7
V
V
HHOFFT
(Note 7)
High-Voltage Half-Bridge Switch On Hysteresis
V
–
6.2
–
0.6
7.0
0.6
5.3
100
1.1
7.6
1.1
6.3
–
HHONH
(Note 7)
Low-Voltage Half-Bridge Switch Off Threshold
Low-Voltage Half-Bridge Switch On Hysteresis
V
V
V
LHOFFT
(Note 7)
V
LHONT
(Note 7)
Low-Voltage Reset Low Threshold (V
) (Note 8)
V
4.6
–
V
SUP
LVRON
(Note 7)
Low-Voltage Reset Hysteresis (Note 8)
V
mV
LVRH
(Note 7)
Notes
7. See Figure 2, page 10.
8. Low-Voltage Reset depends on the internal V voltage.
DD
33393
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SINGLE-WIRE BUS I/O (SIO)
TJ from -40°C to 125°C, VSUP from 9.0 V to 16 V, bus frequency @ 2.6 MHz, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
ISO9141 APPLICATION
Bus Input Voltage Range
V
-16
–
–
25
V
BI
Input Current
V
V
= -0.3 V to V
= -16 V to -0.3 V
I
I
-20
-10
20
0.02
µA
mA
BUS
BUS
SUP
BIL
V
/5 kΩ
BUS
BIN
Input High Level
Input Low Level
V
0.6*V
–
–
–
V
V
BIH
SUP
V
–
–
–
0.4*V
SUP
BIL
Input Hysteresis
Output Low Voltage (I
V
50
–
–
mV
V
BHYS
=25 mA)
V
1.3
LOAD
BOL
Output Current Limit (V
=1.2 V to 16 V)
I
40
–
110
-1.5
-1.5
3.0
mA
BUS
BLIM
Output Falling Edge Slew Rate @ T from -40°C to 100°C (Note 9)
SR
-3.0
-3.5
1.5
-2.25
-2.75
2.25
2.75
V/µs
V/µs
V/µs
V/µs
J
F
Output Falling Edge Slew Rate @ T from 100°C to 125°C (Note 9)
SR
J
FH
Output Rising Edge Slew Rate @ T from -40°C to 100°C (Note 9)
SR
J
R
Output Rising Edge Slew Rate @ T from 100°C to 125°C (Note 9)
SR
1.5
3.5
J
RH
Rise Fall Slew Rate Symmetry (Note 9)
Debounce Time (Note 10)
DSR
–
–
–
0
–
–
–
V/µs
µs
t
1.5
20
DB
Input Capacitance (Note 10)
C
pF
I
MI-BUS APPLICATION (Note 11)
Bus Input Voltage Range
V
-0.3
-0.3
2.4
8.5
–
–
–
25
1.3
6.0
V
V
BI
Input Low Level (for both data transfer and programming)
Input High Level 5.0 V Operation (for data transfer)
Input High Level 12 V Operation (for programming)
Input Hysteresis
V
BIL
V
–
V
BIH
V
–
V
V
BIHP
BHYS
BPUP
SUP
V
R
50
11
–
mV
kΩ
Output Pull-Up Resistor (connected to internal V
)
6.0
20
1.3
110
DD
Output Low Voltage @ I
=25 mA
V
–
–
–
V
LOAD
BOL
Output Current Limit @ V
=0 V to 5.5 V
I
40
mA
BUS
BLIM
Output Slew Rate (Note 12)
Debounce Time (Note 13)
Notes
SR
–
–
2.25
650
–
–
V/µs
ns
t
DB
9. Tested with R
10. Not tested.
=510 Ω.
PULLUP
11. Only physical layer. All other MI-BUS features (e.g., programming procedure) are software related.
12. Tested with R
13. Not tested.
=510 Ω.
PULLUP
33393
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INTERNAL RC-OSCILLATOR
TJ from -40°C to 125°C and VSUP = 10 V, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Oscillator Period (trimmed oscillator)
t
192 - 1.5 LSB
192
192 + 1.5 LSB
ns
OSC
Oscillator Deviation (full temperature trimmed range)
–
–
6.5
–
ns
EEPROM CHARACTERISTICS (Note 14)
TJ from -40°C to 125°C, VSUP from 9.0 V to 16 V, bus frequency @ 2.6 MHz, unless otherwise noted.
Characteristic
Symbol
Min
Max
Unit
–
–
100
Cycles
Write/Erase Cycles EEPROM @ 10 ms Write Time, T = +125°C
J
Data Retention EEPROMs
–
10
5.0
5.0
5.0
100
$00
–
Years
ms
ms
ms
ms
–
Data EEPROM Programming Time per Byte
EEPROM Erase Time per Byte
EEPROM Erase Time per Block
Data EEPROM Bulk Erase Time
t
10
EEPGM
t
10
EBYT
t
10
EBLOCK
t
200
$3F
EBULK
EEPROM Cell $401 Content (value to trim RC-Oscillator tot
=192 ns)
EE
EE
OSC
401
403
EEPROM Cell $403 Content (value to trim RC-Oscillator ot
=202 ns)
$00
–
$3F
5.0
–
OSC
RC Oscillators Stabilization Time
Notes
t
t
CYC
RCON
14. For timing definitions and programming procedure, refer to MC33393YTM specification.
33393
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POWER STAGES
TJ from -40°C to 125°C, VSUP from 9.0 V to 16 V, bus frequency @ 2.6 MHz, unless otherwise noted.
Characteristic
Switch On Resistances (I = 100 mA)
L1/L2/R1/R2 to V
Symbol
Min
Typ
Max
Unit
Ω
R
–
–
3.6
2.0
6.5
5.0
SUP
ONH
L1/L2/R1/R2 to GND
R
ONL
Rise Time @ I=00 mA, 16 V
Fall Time @ I=100 mA, 16 V
t
–
–
–
385
275
420
–
–
–
ns
ns
HBR
t
HBF
High-Side Current Detection @T =25°C
I
mA
J
HSD
(Note 15)
High-Side Overcurrent Total Period (fast PWM function) (Note 16)
t
1.75
0.35
4.0
7.5
µs
V
HSf
(Note 15)
High-Side Free-Wheel Diode Forward Voltage @ I=150 mA,
V
HFD
Referenced to V
0.78
1.35
SUP
Low-Side Current Control (CS0=1, CS1=1)
Low-Side Current Control (CS0=0, CS1=1)
I
I
65
85
115
170
mA
mA
–
LSC(11)
LSC(01)
105
135
Low-Side Overcurrent Switch-Off Time (PWM function)
(Note 17), (Note 18)
t
PWM
–
64/2048
–
Low-Side Free-Wheel Diode Forward Voltage @ I=150 mA,
Referenced to GND
V
V
LFD
0.35
0.76
1.35
o
Overtemperature Detection (Note 19)
T
125
–
150
–
–
OFF
C
L1/L2/R1/R2 Leakage Current When Off (V[A1-B2]=0 V to 16 V)
Half-Bridge Output High Threshold for BEMF Detection (Note 20)
I
20
25
µA
HBleak
V
–
0
mV
BHT
(Note 21)
Half-Bridge Output Low Threshold for BEMF Detection (Note 20)
Hysteresis for BEMF Detection (Note 20)
V
–
–
-60
60
-10
–
mV
mV
BLT
(Note 21)
V
BH
Notes
15. See Figure 3, page 10.
16. Not programmable.
17. The switch-off time of oscillator frequency/64 can only be used with the current limit mode CS0=1 and CS1=1. Due to power dissipation, it is
not allowed to use other current limits.
18. Times oscillator-cycle, programmable.
19. Bridges are switched off. Only functionality is tested.
20. Used to count steps, detect open load, and detect stall.
21. See Figure 4, page 10.
33393
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TESTPORT
TJ from -40°C to 125°C, VSUP from 9.0 V to 16 V, bus frequency @ 2.6 MHz, unless otherwise noted.
Characteristic
Output Low Level @ 0.8 mA
Symbol
Min
Typ
Max
Unit
V
–
25
–
mV
TOH
Output High Level @ 0.8 mA
Input High Level
V
–
–
5.15
–
–
V
V
TOL
V
>0.7*V
(Note 22)
TIH
DD
Input Low Level
V
–
<0.3*V
(Note 22)
–
V
TIL
DD
Notes
22.
V
is an internal voltage (typically 5.3 V) used by factory test only
DD
CONTROL TIMING
TJ from -40°C to 125°C, VSUP from 9.0 V to 16 V, bus frequency @ 2.6 MHz, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Cycle Time (2/f
)
t
334
–
–
ns
OSC
CYC
Stop Recovery Start-Up Time
POR Start-Up Time
t
–
0.1
–
ms
ILCH
(Note 23)
t
POS
–
1.0
–
ms
(Note 24)
16-Bit Timer
t
Resolution (Note 25), (Note 26)
Input Capture Pulse Width (Note 26)
Input Capture Period (Note 26)
RESL
4.0
85
(Note 27)
–
–
–
–
–
–
t
t
CYC
t
, t
TH TL
ns
t
TLTL
CYC
Notes
23. See the Figure 5, page 10.
24. See the Figure 6, page 10.
25. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
26. Not tested.
27. The minimum period t
should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 t
.
TLTL
CYC
ELECTRICAL CHARACTERISTICS DEVIATION IN CASE OF VSUP FROM 8.0 V TO 9.0 V
TJ from -40°C to 125°C and VSUP from 8.0 V to 9.0 V.
Characteristic
Half-Bridge Path Resistance
Symbol
Min
Typ
Max
Unit
R
–
–
12
Ω
PATH
Input High Level (SIO BUS Level)
Input Low Level (SIO BUS Level)
V
0.7
–
–
–
–
V
V
BIH
SUP
SUP
V
0.3
BIL
33393
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VHHOFFT
WAKE-UP
VHHOFFT - VHHOFFH
VSUP
VLHOFFT + VLHOFFH
OSC
VLHOFFT
VLVRON + VLVRH
*
VLVRON
*
OSC On Time 32 Cycles
tILCH
Over-/Undervoltage
Shutdown
Reset
Figure 5. Start-Up Time STOP Recovery
*
Measured at internal supply.
Figure 2. VSUP-Related Reset and Half-Bridge Switch
On/Off Waveforms
VSUP
OSC
IHSD
LVR
HS current
OSC On Time 32 Cycles
tPOS
tHSf
Figure 3. High-Side Overcurrent Limitation Schematic
Figure 6. Start-Up Time POR
V
VOUT
SUP
VBHT
VBLT
BEMF
L1, R1,
R2, L2
BEMF
BEMFC
0xXX
GND
Figure 4. BEMF Signal Generation
33393
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33393 offers a highly flexible, cost-effective solution for
The half-bridges are current limited by means of a low-side
application control and protocol handling.
PWM function.
To reduce external components and cost, the device
includes an internal RC-oscillator, which offers minor changes
in frequency over temperature and voltage.
The EEPROM is byte erasable and programmable. To allow
erasing and programming (for storing parameters, etc.), there
are two support routines in the internal ROM.
Four independent half-bridges can be used to control a
bipolar stepper motor. The output voltage levels are related to
VSUP and GND respectively.
FUNCTIONAL PIN DESCRIPTION
GND
L1, R1, L2, R2
Device’s ground pins. All GND pins should be connected
These pins are half-bridge outputs with integrated free-
wheeling diodes. Outputs are switched off (high-impedance
state) in the case of overtemperature or over-/undervoltage.
The short-circuit protection prevents damage of driver devices
and bond wires. Current limitation on low-side switches and
open-load detection.
together with a very low-impedance connection.
VSUP
Power supply input to the device. The bypass capacitor
should be connected to prevent noise problems. VSUP is input
voltage for the internal voltage regulator. Any loss of VSUP
sufficient to trigger Low-Voltage Reset (LVR) will cause the
device to be reset. The device will remain in the reset state for
the duration of the LVR condition. Note that LVR depends on
the internal voltage regulator output.
SIO
Single-wire physical bus serial interface ISO9141 or MI-Bus.
Output current limitation. See application data for other
information.
TCLK, TDAT
Pins for factory testing and accessing the device in
Bootloader or Testmode.
APPLICATIONS
Power Supply Pins
33393
The VSUP and GND are the power supply and ground pins,
respectively. The 33393 operates from a single power supply.
Fast signal transitions on 33393 pins place high, short-duration
current demands on the power supply. To prevent noise
problems, take special care to provide power supply bypassing
at the 33393 as Figure 7 shows. Place the C bypass capacitor
as close to the 33393 as possible. Use a high-frequency-
response ceramic capacitor (X7R).
VSUP
GND
C
0.33 µF (X7R)
VSUP
Figure 7. Power Supply Bypassing
33393
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High-Side Overcurrent Protection
Physical Layer
In case an output of the half-bridge is short-circuited to GND,
the high-side FETs limit the current with a fast PWM.
The interface is suited for automotive and industrial
applications and features bus monitoring and slew rate control
(see Figure 8 for schematic of the bus transceiver). The
interface is protected against positive as well as negative
voltages associated with the automotive environment.
VSUP
The single-wire interface is capable of dealing with voltages
Current
Limit
Half-Bridge
Output
radiometric to VSUP or VDD
.
It also includes an debounce circuit to filter transients less
than 1 µs/500 ns.The interface is shared with the 16-bit timer
channels. All functions are software programmable.
EXPM
L1, L2,
R1, R2
System
Current
Limit
HBON
Control
TCAP
V
SUP
MIHV
SI
Level
Filter
Shifter
GND
Comm.
Reg.
Figure 9. Half-Bridge Push-Pull Output Driver
MIM
SO
100 pF
SI/SO
Single-Wire Bus
Stall Detection
OCS
The half-bridge stall detection for stepper motors is based on
a new principle taking advantage of the instability of the
electrical/mechanical behavior of the stepper motor when
blocked.
TCMP
Transceiver
Figure 8. Principle Schematic of the Bus Transceiver
For implementation of this new stall detection principle, the
half-bridge generates a recirculation phase signal called BEMF.
This signal is integrated by an 8-bit counter. Whenever this
signal is active, the counter is incremented. See Figure 10 for
the principal of BEMF generation.
On-Chip Oscillator
The system clock is generated with an on-chip oscillator. The
frequency can be tuned by a 6-bit register.
The BEMFC register reflects the time of the recirculation
phase. This value can be used to implement a stall detection
algorithm by software.
The accuracy of the oscillator is suitable for self-
synchronization on standard SCI/UART-based protocols.
Stall detection can be adjusted by software, which features
flexibility for different motors and environments.
Half-Bridges
The I/O levels are related to VSUP and GND. The port
provides four low-resistive push-pull output stages with an
maximum Path RDS(ON) of 12 Ω. See Figure 9 for one half-
bridge push-pull output driver.
L
[V]
1
R
[V]
[V]
1
The outputs are protected against short circuit,
overtemperature, and overvoltage/undervoltage.
I
S
Overtemperature
The outputs are automatically turned off if the power stages
become overheated. If the temperature falls below a threshold
level, the outputs return to their previous state.
BEMF [V]
Overvoltage/Undervoltage
The outputs are automatically turned off if the VSUP is not in
a proper range. If the voltage reaches a proper range, the
outputs return to their previous state.
Figure 10. BEMF Generation
IMPORTANT: For information on HC05 CPU and testport
(TDAT, TCLK), refer to the MC33393YTM specification.
Current Limitation
The current limitation is done on the low-side switches. The
limits can be selected with two bits in the System Control
Register.
33393
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
12
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Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
FTB SUFFIX
(52-LEAD LQFP EXPOSED PAD)
PLASTIC PACKAGE
CASE 1336-01
ISSUE O
4X
AB
X=A, B OR D
X
4X 13 TIPS
0.20 H A-B D
0.20 C A-B D
D
AB
C
L
52
40
1
39
e
48X
VIEW Y
B
VIEW Y
E1
E
b1
8
BASE METAL
A
PLATING
E1/2
E/2
13
27
c
c1
8
8
14
26
b
8
D1/2
D/2
SECTION AB-AB
ο
ROTATED 90 CLOCKWISE
D1
D
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE
C.
52X
4X Z2
4X Z3
A
0.08 C
5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE
LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY
MORE THAN 0.08 mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION ANDADJACENT LEAD ORPROTRUSION 0.07 mm.
6. DIMENSIONSD ANDE1 DO NOT INCLUDEMOLDPROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1
ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
52X
b
J
SEATING
PLANE
M
0.08
C A-B D
VIEW AA
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.1 mm AND 0.25 mm FROM THE LEAD TIP.
S
Z1
R1
Z
MILLIMETERS
DIM MIN
MAX
1.70
0.20
1.50
G
A
---
A1 0.05
A2 1.30
b
0.271 0.334
R2
L
b1 0.27
0.33
A1
c
0.123 0.136
L1
c1 0.122 0.132
D
D1
e
12.00 BSC
10.00 BSC
0.65 BSC
VIEW AA
F
E
12.00 BSC
10.00 BSC
E1
L
0.45
0.75
L1
1.00 REF
R1 0.08
R2 0.08
---
0.20
---
S
F
0.20
6.50
6.50
7.50
G
7.50
EXPOSED PAD
Z
0
7
×
×
VIEW J-J
---
Z1
Z2
Z3
0
×
11
13
×
×
11
13
×
×
33393
13
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfoTArmation On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
NOTES
33393
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
NOTES
33393
15
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfoTArmation On This Product,
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Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
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or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do
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