N74F224D [NXP]
16 】 4 Synchronous FIFO 3-State; 16 】 4同步FIFO三态
| 型号： | N74F224D |
| 厂家： | 
NXP |
| 描述： | 16 】 4 Synchronous FIFO 3-State |
| 文件： | 总1页 (文件大小：21K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Preliminary specification
16 × 4 Synchronous FIFO (3-State)
74F224
However, an external gating is required (see
Figure 1). For longer words using 74F224,
the IR signals of the first-rank packages and
OR signals of the last-rank packages must be
ANDed for proper synchronization.The
3-State outputs controlled by a single input
(OE) make bus connection and multiplexing
easy.
FEATURES
DESCRIPTION
This 64-bit active element First-In-First-Out
(FIFO) is a monolithic Schottky-clamped
transistor-transistor logic (STLL) array
organized as 16 words of 4-bits each. A
memory system using the 74F224 can be
easily expanded in multiples of 15m+1 words
or of 4n bits, or both (where n is the number
of packages in the horizontal array).
• Independent synchronous inputs and
outputs
• Organized as 16 words of 4 bits
• DC to 50MHz data rate
• 3-State outputs
• Cascadable in word–width and depth
direction
TYPICAL
TYPE
TYPICAL
SUPPLY
CURRENT
(TOTAL)
f
max
74F224
50MHz
90mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
DRAWING NUMBER
V
CC
= 5V ±10%, T = 0°C to +70°C
amb
16-pin plastic Dual In-line Package
16-pin plastic Small Outline Large
N74F224N
N74F224D
0406C
0171B
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
LDCP
D0 – D3
OE
Load clock input
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
Output enable input (active high)
Unload clock input
UNCP
MR
Master reset input (active low)
Input ready output
IR
Q0 – Q3
OR
Data outputs
50/33
Output ready output
50/33
NOTE TO INPUT AND OUTPUT LOADING AND FAN OUT TABLE
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
LOGIC SYMBOL
IED/IEEE SYMBOL
4
5
6 7
FIFO 16 X 4
CTR
1
9
EN5
1
2
3
4
5
16
15
14
13
OE
IR
V
CC
CT=0
CT<0
D0 D1 D2 D3
2
2
UNCP
OR
+/C1
&
OE
1
13
3
3
14
LDCP
Z2
3
UNCP
LDCP
MR
&
D0
D1
Q0
&
CT=0
2
CT>0
1D
–
15
V4
9
12 Q1
Z3
Q0 Q1 Q2 Q3 IR OR
4
13
12
13
10
6
7
8
11
10
9
D2
D3
Q2
4,5
5
6
7
Q3
13 12 11 10 2 14
GND
MR
V
= Pin 16
CC
GND = Pin 8
1
September 7, 1990
相关型号：
©2020 ICPDF网 联系我们和版权申明