概述
规格参数
数据手册PCK2011DL 概述
Direct RAMbus Clock Generator 直接RAMBUS时钟发生器 时钟发生器
PCK2011DL 规格参数
| 生命周期： | Obsolete | 零件包装代码： | SSOP |
| 包装说明： | SSOP, | 针数： | 24 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.84 |
| Is Samacsys： | N | JESD-30 代码： | R-PDSO-G24 |
| 长度： | 8.2 mm | 端子数量： | 24 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 最大输出时钟频率： | 400 MHz | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SSOP | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, SHRINK PITCH | 主时钟/晶体标称频率： | 400 MHz |
| 认证状态： | Not Qualified | 座面最大高度： | 2 mm |
| 最大供电电压： | 3.465 V | 最小供电电压： | 3.135 V |
| 标称供电电压： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子形式： | GULL WING | 端子节距： | 0.65 mm |
| 端子位置： | DUAL | 宽度： | 5.3 mm |
| uPs/uCs/外围集成电路类型： | CLOCK GENERATOR, PROCESSOR SPECIFIC | Base Number Matches： | 1 |
PCK2011DL 数据手册
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PCK2011
Direct RAMbus Clock Generator
Preliminary specification
1999 Jan 19
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
Overview
PIN CONFIGURATION
The Direct Rambus Clock Generator (DRCG) provides the Channel
clock signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock. Contained in a 24-pin SSOP package, the
DRCG provides an off-the-shelf solution for a broad range of Direct
Rambus memory applications.
S0
24
1
2
VDDLR
REFCLK
VDDP
23
22
21
20
19
18
17
16
15
14
13
S1
3
VDDO
GNDO
CLK
4
GNDP
5
GNDl
Features
6
PCLKM
SYNCLKN
GNDC
N/C
• High Speed Clock Support
7
CLKB
GNDO
Provides a 400MHz differential clock source for Direct Rambus
memory systems for an 800MHz data transfer rate.
8
9
VDDC
VDDO
• Synchronization Flexibility
10
11
VDDIPD
STOPB
MULT0
The DRCG includes signals to synchronize the clock domains of
the RambusR Channel with an external system or processor
clock.
MULT1
S2
PWRDNB 12
• Power Management Support
SW00289
The DRCG is able to turn off the Rambus Channel clock to
minimize power for mobile and other power-sensitive applications:
Related Documentation
- In the “clock off” mode, the DRCG remains on while the output
is disabled, allowing fast transitions between the clock-off and
clock-on states. This mode could be used in conjunction with
the Nap mode of the RDRAMs and Rambus ASIC Cell (RAC).
Direct Rambus RAC Overview
Direct Rambus Memory Controller Guide
- In the “power down” mode, the DRCG is completely powered
down for minimum power dissipation. This mode is used in
conjunction with the power down modes of the RDRAMs and
RAC.
Pin-outs
The DRCG is packaged in a 24-pin 150 mil SSOP. The pin
configuration shows the preliminary pin-out. Table 1 describes the
function and connection of each pin.
• Supports Independent Channel Clocking
The DRCG supports systems that do not require synchronization
of the Rambus clock to another system clock.
Example System Clock Configuration
Figure 2 shows the clocking configuration for an example Direct
Rambus subsystem. The configuration shows the interconnection of
the system clock source, the Direct Rambus Clock Generator
(DRCG), and the clock signals of a memory controller ASIC. The
ASIC contains the RAC, the Rambus Memory Controller protocol
engine (RMC), and logic to support synchronizing the Channel clock
with the controller clock. (This diagram represents the differential
clocks as a single Busclk wire.)
• Works with Philips PCK2010 to support Intel CK98 Clock
Synthesizer/Driver specification.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA NORTH AMERICA
PCK2011 DL PCK2011 DL
DRAWING NUMBER
24-Pin Plastic SSOP
0°C to +70°C
SOT340-1
2
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
Table 1. PIN DESCRIPTION
Pin
#
Name
Type
Function
Notes
1
VDDLR
REFCLK
VDDP
RefV
Reference for REFCLK
Connect to CK133
Connect to CK133
3.3V Supply
2
In
Reference clock
3
Pwr
GND
GND
In
VDD for PLL
4
GNDP
GNDl
GND for PLL
Ground
5
GND for control inputs
Phase Detector Input
Phase Detector Input
GND for Phase Aligner
VDD for Phase Aligner
Reference for P.D. Inputs
Active Low Output Disable
Active Low power down
Mode control input
PLL multiplier select
PLL multiplier select
VDD for clock outputs
GND for clock outputs
Output Clock (complement)
Not used
Ground
6
PCLKM
Connect to Controller
Connect to Controller
Ground
7
SYNCLKN In
8
GNDC
VDDC
VDDLPD
STOPB
PWRDnB
S2
GND
9
Pwr
RefV
In
3.3V Supply
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Connect to Controller
Connect to Controller
3.3V CMOS
In
In
3.3V CMOS
MULT1
MULT0
VDDO
GNDO
CLKB
N/C
In
3.3V CMOS
In
3.3V CMOS
Pwr
GND
Out
N/C
Out
GND
Pwr
In
3.3V Supply
Ground
Connect to Rambus Channel
Not connected (floating)
Connect to Rambus Channel
Ground
CLK
Output Clock
GNDO
VDDO
S1
GND for clock outputs
VDD for clock outputs
Mode Control
3.3V Supply
3.3V CMOS
S0
In
Mode Control
3.3V CMOS
3
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
This configuration achieves frequency-lock between the controller
and Rambus Channel clocks (PCLK and SYNCLK). These clock
signals are matched and phase-aligned at the RMC/RAC boundary
in order to allow data transfers to occur across this boundary without
additional latency.
Pclk is the clock used in the Rambus memory controller (RMC) in
the ASIC. SYNCLK is the clock used at the ASIC interface of the
RAC. The DRCG together with the Gear Ratio Logic enables the
controller to exchange data directly from the PCLK domain to the
SYNCLK domain without incurring additional latency for
synchronization. In general, PCLK and SYNCLK can run at different
frequencies, so the Gear Ratio Logic must select the appropriate M
and N dividers such that the frequencies of PCLK/M and SYNCLK/N
are equal. In one example, PCLK=133MHz and SYNCLK=100MHz,
and M=4 while N=3, giving PCLK/M = SYNCLK/N = 33MHz. Figure
4 shows an example of the clock waveforms generated with the
Gear Ratio Logic.
The main clock source drives the system clock (PCLK) to the ASIC,
and also drives the reference clock (REFCLK) to the DRCG.
REFCLK may or may not be the same frequency as PCLK. A PLL
inside the DRCG multiplies REFCLK to generate the desired
frequency for BUSCLK. BUSCLK is driven on the Rambus Channel
through a terminated transmission line. At the mid-point of the
Channel, the RAC senses BUSCLK using its own DLL for clock
alignment, followed by a fixed divide-by- 4 circuit that generates
SYNCLK.
REFCLK
Direct Rambus
Clock Generator
(DRCG)
PCK2010
BUSCLK
RDRAMs
RAC
RMC
M
N
/4
DLL
PCLK
SYNCLK
Gear Ratio-
Logic
CONTROLLER
SW00290
Figure 1. System Clock Architecture
The ASIC drives the output clocks, Pclk and SynClk/N from the
Gear Ratio Logic to the DRCG Phase Detector inputs. The routing
of the Pclk/M and SynClk/N signal traces must be matched in
impedance and propagation delay on the ASIC as well as on the
board. These signals are not part of the Rambus Channel and their
routing must be matched by board designers.
In this manner, the distributed loop adjusts the phase of SynClk/N to
match that of Pclk/M, eliminating the phase error at the input of the
DRCG. When the clocks are aligned, data can be exchanged
directly from the Pclk domain to the SynClk domain.
The Gear Ratio Logic supports four clock ratios (2.0, 1.5, 1.33, and
1.0), where the ratio is defined as the ratio of Pclk/SynClk. Since
Busclk = 4*SynClk, this ratio also is equal to 4*Pclk/Busclk. Other
ratios could be used, depending on particular system
implementations.
After comparing the phases of Pclk/M and SynClk/N, the DRCG
Phase Detector drives a phase aligner that adjusts the phase of
DRCG output clock, Busclk. Since the other elements in the
distributed loop have a fixed delay, adjusting Busclk adjusts the
phase of SynClk and thus the phase of SynClk/N.
4
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
Power Management Modes
Table 2. POWER MANAGEMENT MODES
The DRCG device has three operating states: NORMAL, CLKSTOP
and POWERDOWN. In Normal mode, the clock source is on, and
the output is enabled. In CLKSTOP mode, the clock source is on,
but the output is disabled (STOPB deasserted). In Powerdown
mode, the device is powered down with the control signal PwrDnB
equal to 0. The control signals Mult0, Mult1, S0, S1 and S2 must be
stable before power is applied to the device, and can only be
changed in Power-down mode (PWRDNB=0).
MODE
PwrDnB
StopB
Clk
ClkB
NORMAL
CLKSTOP
1
1
0
1
0
PACLK
PACLKB
V , STOP V , STOP
X
X
POWERDOWN
X
GND
GND
Upon applying power to the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and StopB.
The clock source output need not be glitch-free during state
transitions.
PWRDNB
S0
S1
S2
STOPB
DRCG
TEST MUX
BYPASS MUX
BYPCLK
PLLCLK
X
CLK
REFCLK
PHASE
ALIGNER
B
A
CLKB
PPL
PACLK
ΦD
PCLKM
SYNCLKN
MULT
2
0
MULT
1
SW00360
Figure 2. Direct Rambus Clock Generator Package
5
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
Pclk
SynClk
Pclk/M =
SynClk/N
SW00292
Figure 3. Gear Ratio Timing Diagram
In order to reduce signal attenuation and EMI, clock signal rise/fall
times are controlled to within specifications. In addition, DRCG is
able to receive input signals that are generated from different
voltage power supplies. The phase detector signals come from the
controller. The controller output voltage supply is connected to the
pin VddIPD of DRCG, and is used as the reference for the
two-phase detector input signals, PclkM and SynClkN. The output
voltage supply is also used as the reference for the output
enable/disable signal, StopB.
PHYSICAL SPECIFICATION
General Requirements
The clock source generates differential signals with specified jitter,
voltage levels, duty cycle, and rise/fall times. Figure 5 shows the
clock equivalent circuit.
Z
R = Z
T CH
CH
The reference clock comes from the main clock source chip. The
main clock source output voltage supply is connected to the pin
VddIR of DRCG, and is used as the reference for the Refclk input
signal.
CHANNEL
Clock Jitter
The short-term jitter specification (over four cycles) for the clock
source is under 100 ps maximum. Jitter is measured using a jitter
measurement system that provides flexibility for measuring
cycle-cycle jitter as a function of cycle count.
R
T
= Z
CH
Z
CH
SW00291
Clock Source Specification
Figure 4. Equivalent Circuit
Rambus clock sources meet the output specifications listed in
Table 4 when characterized under the operating conditions listed in
Table 3.
The driver produces a specified voltage swing on the Channel. The
nominal value of the Channel impedance, Z CH , is 28 ohms.
6
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
Table 3. DC DEVICE CHARACTERISTICS
Symbol
Parameter
Min
Max
Unit
V
V DD
Supply voltage
3.135 3.465
T A
Ambient operating temperature
Refclk Input cycle time
0
70
°C
tCYCLE ,IN
tJ,IN
10
–
40
ns
1
Input Cycle-to-cycle jitter
250
60%
33
ps
DCIN
Input duty cycle over 10,000 cycles
Input frequency of modulation
40%
30
0.25
–
tCYCLE
kHz
%
3
fM,IN
PM,IN
Modulation index
0.5
0.6
Modulation index for triangular modulation
Modulation index for non-triangular modulation
3
PM,IN
%
4
4
–
0.5
tCYCLE,PD
tERR,INIT
DCIN,PD
tIR , tIF
CIN,PD
∆CIN,PD
CIN,CMOS
VIL
Phase Detector input cycle time at PclkM & SynClkN
30
–0.5
25%
1
100
0.5
75%
4
ns
Initial Phase error at Phase Detector inputs (Required range of Phase Aligner)
Phase Detector input duty cycle over 10,000 cycles
tCYCLE,PD
tCYCLE,PD
V/ns
pF
Input slew rate (measured at 20% – 80% of input voltage) for PclkM, SynClkN, and Refclk
2
Input capacitance at PclkM, SynClkN, and Refclk
–
7
2
Input capacitance matching at PclkM and SynClkN
–
0.5
10
0.3
–
pF
2
Input capacitance at CMOS pins
–
pF
Input (CMOS) signal low voltage
Input (CMOS) signal high voltage
Refclk input low voltage
–
Vdd
VIH
0.7
–
Vdd
VIL,R
0.3
–
VddI,R
VddI,R
VddI,PD
VddI,PD
V
VIH,R
Refclk input high voltage
0.7
–
VIL,PD
Input signal low voltage for PD inputs and StopB
Input signal high voltage for PD inputs and StopB
Input supply reference for Refclk
Input supply reference for PD inputs
0.3
–
VIH,PD
VDDI,R
VDDI,PD
NOTES:
0.7
1.3
1.3
3.3
3.3
V
1. Refclk jitter measured at V
(nom)/2
DDI,R
2. Capacitance measured at Freq = 1MHz, DC bias = 0.9V, and V < 100mV
AC
3. If the input modulation is used, input modulation is allowed but not required.
4. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot
exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about
0.5%.
7
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct Rambus Clock Generator
PCK2011
Table 4. AC DEVICE CHARACTERISTICS
Symbol
Parameter
Min
Max
Unit
tCYCLE
Clock cycle time
2.5
–
3.75
60
ns
ps
ps
ps
ps
Cycle-to-cycle jitter at Clk/ClkB
Total jitter over 2, 3, or 4 clock cycles
tJ
1
–
100
–
tSTEP
Phase Aligner phase step size (at Clk/ClkB)
1
tERR,PD
Phase Detector phase error for distributed loop Measured at PclkM-SynClkN (rising edges) (does not – 100 100
include clock jitter)
tERR,SSC
DC
PLL output Phase error when tracking SSC
Output duty cycle over 10,000 cycles
Output cycle-to-cycle duty cycle error
Output rise and fall times (measured at 20% – 80% of output voltage)
Difference between rise and fall times on a single device (20% – 80%)
Output voltage during Clkstop (StopB = 0)
Differential output crossing-point voltage
Output voltage swing (p-p single-ended)
Output HIGH voltage
– 100 100
ps
tCYCLE
ps
ps
ps
V
40%
–
60%
50
tDC,ERR
tCR , tCF
tCR,CF
250
–
500
100
2.0
1.8
0.6
2.0
–
V , stop
X
1.1
1.3
0.4
–
V
V
V
V
V
X
V
COS
OH
OL
V
Output LOW voltage
1.0
12
–
V
R
Output dynamic resistance (at pins)
50
Ω
OUT
I
I
I
I
I
Output current during Hi-Z (S0 = 0, S1 = 1)
Output current during ClkStop (StopB = 0)
Current on powerdown (PwrDnB = 0)
Current on ClkStop (StopB = 0)
50
µA
µA
µA
mA
mA
OZ
, stop
–
500
200
50
OZ
–
powerdown
ClkStop
Current on normal state (StopB = 1)
100
normal
NOTE:
1. Output jitter specs measured at t
= 2.5ns.
CYCLE
2. V
= V – V
COS
OH OL
3. R = ∆V /∆I ; this is defined at the output pins.
out
O
O
Table 5. DRCG FUNCTIONS
REFCLK
pin2
33
MULT0
MULT1
PLL
CLK/CLKB
pins 20/18
267
MODE
S0
S1
S2
CLK
CLKB
pin 18
PAclk
PLLclk
Refclk
–
pin15
pin14
multiplier
pin 24
pin 23
pin 13
pin 20
PAclk
PLLclk
Refclk
–
1
0
1
0
0
1
1
1
1
0
1
0
8
6
Normal
Bypass
0
1
1
0
1
1
0
0
0
1
0
0
1
1
0
0
0
1
1
1
x
50
300
50
8
400
Test
67
4
267
Vendor Test A
Vendor Test B
Reserved
Output Test
67
6
400
–
–
100
8/3
267
–
–
Hi-Z
Hi-Z
8
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct RAMbus Clock Generator
PCK2011
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
9
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct RAMbus Clock Generator
PCK2011
NOTES
10
1999 Jan 19
Philips Semiconductors
Preliminary specification
Direct RAMbus Clock Generator
PCK2011
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04956
Document order number:
Philips
Semiconductors
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