PLL520-20DC [PLL]
Oscillator;
| 型号： | PLL520-20DC |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Oscillator |
| 文件： | 总8页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
FEATURES
DIE CONFIGURATION
65 mil
•
•
100MHz to 200MHz Fundamental Mode Crystals
Output range (no PLL):
(1550,1475)
•
•
100MHz – 200MHz (3.3V).
100MHz – 170MHz (2.5V).
25
24 23 22 21
20
19
18
17
GNDBUF
16
15
14
26
•
•
•
•
•
•
•
Low Injection Power for crystal 50uW.
Complementary outputs: CMOS, PECL or LVDS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
XIN
CMOS
LVDSB
PECLB
Die ID:
A1919-19B
27
28
XOUT
DNC
13
12
VDDBUF
DNC
29
VDDBUF
Die thickness is 10 mil.
11
PECL
30
31
OE
10
9
DESCRIPTION
LVDS
C502A
VCON
OE_SELECT
2
3
4
5
6
7
8
1
PLL520-20 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of inter-
electrode capacitance and bonding capacitance to
improve yield. It achieves very low current into the
crystal resulting in better overall stability. Its internal
varicaps allow on-chip frequency pulling, controlled
by the VCON input.
(0,0)
Y
X
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
GND
BLOCK DIAGRAM
Reverse side
Pad dimensions
Thickness
80 micron x 80 micron
10 mil
OE
Q
Oscillator
VCON
Amplifier
Q
OUTPUT SELECTION AND ENABLE
w/
X+
integrated
varicaps
Pad #18
OUTSEL1
Pad #25
OUTSEL0
Selected Output
X-
PLL520-20
0
0
1
1
0
1
0
High Drive CMOS
Standard CMOS
LVDS
1
PECL (default)
OE_SELECT
(Pad #9)
OE
(Pad #30)
State
0
Tri-state
0
1 (Default)
0 (Default)
1
Output enabled
Output enabled
Tri-state
1 (Default)
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if O E_SELECT (pad #9) is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 1
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
V
V
V
Input Voltage, dc
Output Voltage, dc
VSS-0.5
VSS-0.5
VDD+0.5
VDD+0.5
VO
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature for 3.3V Supplies
Ambient Operating Temperature for 2.5V Supplies
Junction Temperature
TA
TA
TJ
-40
-20
85
70
°C
°C
°C
°C
kV
125
260
2
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Parallel Fundamental Mode
Crystal Resonator Frequency
FXIN
MHz
3.3V Supplies
2.5V Supplies
100
100
200
170
3.3V Supply
Die at VCON = 1.65V
4
5
pF
pF
Crystal Loading Rating
CL (xtal)
2.5V Supply
Die at VCON = 1.25V
Interelectrode Capacitance
Crystal Pullability
C0
3.5
pF
-
AT cut
C0/C1 (xtal)
250
AT cut
Recommended ESR
RE
30
15
Ω
3.3V Supplies
2.5V Supplies
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 2
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
TVCXOSTB
From power valid
10
ms
XTAL C0/C1 < 250
VCXO Tuning Range *
VCXO Pullability *
ppm
ppm
3.3V Supplies
2.5V Supplies
180
145
0V ≤ VCON ≤ VDD (at 25°C)
±100
±80
3.3V Supplies
2.5V Supplies
VCON = 0 to VDD
On-chip Varicaps Control Range *
Linearity *
pF
%
3.3V Supplies
2.5V Supplies
5 – 15
6 – 15
3.3V Supplies
2.5V Supplies
4
5
5
10
VCXO Tuning Characteristic
VCON Input Impedance
VCON Modulation BW
65
ppm/V
kΩ
60
25
kHz
0V ≤ VCON ≤ VDD, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
IDD
PECL/LVDS/CMOS
70/40/40
3.47
mA
3.3V Supplies
3.13
Operating Voltage
VDD
V
2.5V Supplies
@ 1.25V (LVDS), 3.3V Supply
@ VDD – 1.3V (PECL), 3.3V Supply
2.375
45
45
43
43
2.625
55
55
57
57
50
50
50
50
%
Output Clock Duty Cycle
Short Circuit Current
@ 1.25V (LVDS), 2.5V Supply
@ VDD – 1.3V (PECL), 2.5V Supply
%
mA
±50
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 3
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
5. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
2.5
MAX.
UNITS
Period Jitter RMS at 155MHz *
At 155.52MHz, with capacitive
decoupling between VDD and GND.
Over 10,000 cycles
ps
Period Jitter peak-to-peak at 155MHz *
18.5
20
At 155.52MHz, with capacitive
decoupling between VDD and GND.
Over 1,000,000 cycles.
Accumulated Jitter RMS at 155MHz *
Accumulated Jitter peak-to-peak, 155MHz *
Random Jitter *
2.5
24
ps
27
2.5
0.3
ps
ps
Integrated jitter RMS at 155MHz
* Measured on Wavecrest SIA 3000 at VDD=3.3V
Integrated 12 kHz to 20 MHz
0.4
6. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
Phase Noise relative to
carrier
155.52MHz
-75
-95
-125
-140
-145
dBc/Hz
Note: Phase Noise measured at VCON = 0V, VDD=3.3V
7. CMOS Electrical Specifications
3.3V Supplies
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
mA
IOH
IOL
IOH
IOL
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
30
30
10
10
Output drive current
(High Drive)
mA
mA
Output drive current
(Standard Drive)
mA
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
2.4
1.2
ns
2.5V Supplies
PARAMETERS
SYMBOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
MIN.
20
TYP.
MAX.
UNITS
mA
IOH
IOL
IOH
IOL
Output drive current
(High Drive)
20
mA
6.5
6.5
mA
Output drive current
(Standard Drive)
mA
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
0.25V ~ 2.25V with 15 pF
load
0.25V ~ 2.25V with 15 pF
load
3.0
1.5
ns
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 4
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
8. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
454
50
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
CONDITIONS
MIN.
0.2
TYP.
0.7
MAX.
1.0
UNITS
ns
RL = 100 Ω
CL = 10 pF
(see figure)
tr
tf
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 5
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
10. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
11. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
@20/80% - PECL
@80/20% - PECL
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50Ω
50Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 6
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
PAD ASSIGNMENT
Pad #
Name
X (µm)
Y (µm)
1
GND
248
361
109
109
2
GND
3
GND
473
109
4
GND
587
109
5
GND
702
109
6
DNC (Do Not Connect)
874
109
7
GND
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
109
8
GNDBUF
109
9
OE_SELECT
125
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LVDS
259
PECL
476
VDDBUF
616
VDDBUF
716
PECLB
871
LVDSB
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
CMOS
GNDBUF
OUTSEL1
DNC (Do Not Connect)
DNC (Do Not Connect)
VDD
659
VDD
559
VDD
459
VDD
358
OUTSEL0
194
XIN
109
XOUT
DNC (Do Not Connect)
DNC (Do Not Connect)
OE
109
109
109
646
109
397
VCON
109
181
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 7
PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-20 DC
PART NUMBER
TEMPERATURE
C=COMMERCIAL
PACKAGE TYPE
D=DIE
Order Number
Marking
Package Option
Die – Waffle Pack
PLL520-20DC
PLL520-20DC
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 3/13/07 Page 8
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