PLL520-20 [PLL]
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals); 低相位噪声压控石英振荡器（为100-200MHz基本晶体）
| 型号： | PLL520-20 |
| 厂家： | 
PHASELINK CORPORATION |
| 描述： | Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) |
| 文件： | 总7页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
FEATURES
DIE CONFIGURATION
65 mil
•
•
•
•
•
•
•
•
•
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100MHz – 200MHz (no PLL).
Low Injection Power for crystal 50uW.
Complementary outputs: CMOS, PECL or LVDS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Die thickness is 10 mil.
(1550,1475)
25
24 23 22 21
20
19
18
17
GNDBUF
16
15
14
26
XIN
N/C
Die ID:
A1919-19B
LVDSB
PECLB
27
28
XOUT
DNC
13
12
VDDBUF
VDDBUF
DNC
29
DESCRIPTIONS
11
PECL
OE
30
31
PLL520-20 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
CTRL
10
9
LVDS
C502A
VCON
OUTSEL^
2
3
4
5
6
7
8
1
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
(0,0)
Y
X
DIE SPECIFICATIONS
Name
Value
BLOCK DIAGRAM
Size
62 x 65 mil
GND
Reverse side
OE
Q
Pad dimensions
Thickness
80 micron x 80 micron
10 mil
Oscillator
VCON
Amplifier
w/
Q
X+
X-
integrated
varicaps
OUTPUT SELECTION AND ENABLE
PLL520-20
Pad #18
OUTSEL1
Pad #25
OUTSEL0
Selected Output
0
0
1
1
0
1
0
High Drive CMOS
Standard CMOS
LVDS
1
PECL (default)
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
0
Tri-state
0
1 (Default)
0 (Default)
1
Output enabled
Output enabled
Tri-state
1 (Default)
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
VDD
VI
4.6
V
V
V
Input Voltage, dc
Output Voltage, dc
VSS-0.5
VSS-0.5
VDD+0.5
VDD+0.5
VO
Storage Temperature
TS
-65
0
150
°C
Ambient Operating Temperature
Junction Temperature
TA
TJ
70
125
260
2
°C
°C
°C
kV
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
FXIN
Parallel Fundamental Mode
Die at VCON = 1.65V
120
200
MHz
Crystal Loading Rating
Interelectrode Capacitance
Crystal Pullability
CL (xtal)
C0
C0/C1 (xtal)
RE
4
pF
pF
-
3.5
250
30
AT cut
AT cut
Recommended ESR
Ω
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
VCXO Tuning Range
TVCXOSTB
From power valid
XTAL C0/C1 < 250
10
ms
180*
ppm
0V ≤ VCON ≤ 3.3V
at room temperature
VCON = 0 to 3.3V
CLK output pullability
ppm
±100*
On-chip Varicaps control range
Linearity
4 – 18*
4*
pF
%
5*
VCXO Tuning Characteristic
VCON input impedance
65
ppm/V
60
kΩ
25
VCON modulation BW
kHz
0V ≤ VCON ≤ 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
4. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded Outputs)
Operating Voltage
IDD
PECL/LVDS
100/80/40
3.47
mA
V
VDD
3.13
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
45
45
50
50
55
55
Output Clock Duty Cycle
Short Circuit Current
%
mA
±50
5. Jitter specifications
PARAMETERS
Period jitter RMS at 155MHz
CONDITIONS
MIN.
TYP.
2.5
MAX.
UNITS
At 155.52MHz, with capacitive
decoupling between VDD and GND.
Over 10,000 cycles
ps
Period jitter peak-to-peak at 155MHz
Accumulated jitter RMS at 155MHz
20
18.5
At 155.52MHz, with capacitive
decoupling between VDD and GND.
Over 1,000,000 cycles.
2.5
24
ps
Accumulated jitter peak-to-peak at 155MHz
Random Jitter
27
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
ps
ps
2.5
0.3
Integrated jitter RMS at 155MHz
Measured on Wavecrest SIA 3000
0.4
6. Phase noise specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz
@1kHz @10kHz @100kHz UNITS
-125 -140 -145 dBc/Hz
Phase Noise
relative to carrier
155.52MHz
-75
-95
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 3
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
454
50
UNITS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
∆VOD
VOH
247
-50
355
mV
mV
V
1.4
1.1
1.2
3
1.6
RL = 100 Ω
(see figure)
VOL
0.9
1.125
0
V
VOS
1.375
25
V
Offset Magnitude Change
mV
∆VOS
Vout = VDD or GND
VDD = 0V
Power-off Leakage
IOXD
IOSD
uA
±1
±10
Output Short Circuit Current
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
CONDITIONS
MIN.
0.2
TYP.
0.7
MAX.
1.0
UNITS
ns
RL = 100 Ω
CL = 10 pF
(see figure)
tr
tf
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50
50
Ω
Ω
VOD
VOS
VDIFF
RL = 100Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
80%
80%
VDIFF
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 4
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
Output Low Voltage
VOH
VOL
VDD – 1.025
V
V
RL = 50 Ω to (VDD – 2V)
(see figure)
VDD – 1.620
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
tr
tf
@20/80% - PECL
@80/20% - PECL
0.6
0.5
1.5
1.5
ns
ns
PECL Levels Test Circuit
PECL Output Skew
OUT
VDD
OUT
50
50
Ω
Ω
2.0V
50%
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
PAD ASSIGNMENT
Pad #
Name
X (µm)
Y (µm)
1
GND
248
361
109
109
2
GND
3
GND
473
109
4
GND
GND
587
109
5
702
109
6
N/C
874
109
7
GND
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
109
8
GNDBUF
OE_SELECT
LVDS
109
9
125
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
259
PECL
476
VDDBUF
VDDBUF
PECLB
616
716
871
LVDSB
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
CMOS
GNDBUF
OUTSEL1
DNC (Do Not Connect)
DNC (Do Not Connect)
VDD
659
VDD
559
VDD
459
VDD
358
OUTSEL0
XIN
194
109
XOUT
109
DNC (Do Not Connect)
DNC (Do Not Connect)
OE_CTRL
VCON
109
109
646
109
397
109
181
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 6
Preliminary PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-20 DC
PART NUMBER
TEMPERATURE
C=COMMERCIAL
PACKAGE TYPE
D=DIE
Order Number
Marking
Package Option
PLL520-20DC
PLL520-20DC
Die – Waffle Pack
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 7
相关型号：
©2020 ICPDF网 联系我们和版权申明