PE9304-EK [PSEMI]
1- 7 GHz Low Power CMOS Divide-by-2 Prescaler; 1- 7 GHz的低功耗CMOS分频预分频器
| 型号： | PE9304-EK |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 1- 7 GHz Low Power CMOS Divide-by-2 Prescaler |
| 文件： | 总6页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY SPECIFICATION
PE9304
Rad Hard for Space Applications
1- 7 GHz Low Power CMOS
Divide-by-2 Prescaler
Product Description
Features
• Fixed divide ratio of 2
The PE9304 is a high-performance CMOS prescaler with
a fixed divide ratio of 2. Its operating frequency range is
1GHz to 7GHz. The PE9304 operates on a nominal 3 V
supply and draws only 13.5mA. It is packaged in a small
8-lead ceramic SOIC and is ideal for frequency scaling
and clock generation solutions.
• Low-power operation: 13.5mA
typical @ 3 V
• Small package: 8-lead Ceramic
SOIC
• Guaranteed 100Krads(Si) Total
The PE9304 is manufactured in Peregrine’s patented
Ultra-Thin Silicon (UTSi) CMOS process, offering the
performance of GaAs with the economy and integration
of conventional CMOS.
Dose Performance
• Superior Single Event Upset
Immunity
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
8 Lead Gullwing Glass Flatpack
.380 / .410
.210 / .250
.180 SQ Max
.166 SQ TYP
Pin 1
.050 TYP
.150 TYP
.015 TYP
Table 1. Electrical Specifications (ZS = ZL = 50 Ω)
VDD = 3.0 V, -40° C ≤ TA ≤ 85° C, unless otherwise specified
Parameter
Conditions
Minimum
Typical
3.0
Maximum
3.15
18.0
7
Units
V
Supply Voltage
2.85
Supply Current
13.5
mA
Input Frequency (Fin)
1
+5
0
GHz
dBm
dBm
dBm
dBm
1GHz ≤ Fin < 2GHz
2GHz ≤ Fin < 6GHz
6 GHz ≤ Fin ≤ 7GHz
1GHz ≤ Fin < 2GHz
2GHz ≤ Fin < 6GHz
6 GHz ≤ Fin ≤ 7GHz
+12
Input Sensitivity (Pin)
Output Power (Pout)
+12
+5
0
+12
-7
-12
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 1 of 6
PE9304
Preliminary Specification
Figure 3. Pin Configuration
Electrostatic Discharge (ESD) Precautions
When handling this UTSi ® device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
1
2
3
4
8
7
6
5
VDD
IN
GND
OUT
NC
PE9304
DEC
GND
GND
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi ®
Table 2. Pin Descriptions
CMOS devices are immune to latch-up.
Pin No.
Pin
Description
Name
Device Functional Considerations
1
2
3
4
VDD
Power supply pin. Bypassing is required
(eg. 1000pF & 100pF).
The PE9304 divides a 1GHz – 7GHz input signal
by a factor of two thereby producing an output
frequency at half the input frequency. To work
properly at higher frequencies, the input and
output signals (pins 2 & 7) must be AC coupled
via an external capacitor, as shown in the test
circuit in Figure 7.
IN
Input signal pin. Should be coupled with a
capacitor (eg. 2.2pF).
DEC
GND
Decoupling Pin. This pin should have two
capacitors in parallel (eg. 1000pf, 10nF)
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance.
5
6
GND
NC
Ground pin.
No connection. This pin should be left
open.
7
8
OUT
GND
Divided frequency output pin. This pin
should be coupled with a capacitor
(eg. 2.2pF).
Ground Pin.
Table 3. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min Max Units
VDD
Pin
Supply voltage
Input Power
3.3
V
dBm
V
+12
VIN
Voltage on input
-0.3
VDD
+0.3
TST
TOP
Storage temperature range
-65
-40
150
85
°C
°C
Operating temperature
range
ESD voltage (Human Body
Model, MIL-STD 883
Method 3015.7)
500
50
V
V
V
ESD voltage (Machine
Model, JEDEC, JESD22-
A114-B)
VESD
ESD voltage (Charged
Device Model, JEDEC,
JESD22-C101)
1000
File No. 70/0152~00A | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 2 of 6
PE9304
Preliminary Specification
Typical Performance Data: VDD = 3.0V
Figure 4. Input Sensitivity
Figure 5. Device Current
Specified
Operating Window
Figure 6. Output Power
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 3 of 6
PE9304
Preliminary Specification
Figure 7. Evaluation Board Schematic Diagram
Figure 8. Evaluation Board Layout
J2-9
C10
C2
1000 pF
100 pF
VDD
IN
GND
OUT
J3
J1
C3
C1
1000 pF
2.2pF
2.2pF
NC
NC
C4
1000pF
C6
10nF
GND
GND
J4
J5
Evaluation Kit Operation
J2 provides DC power to the device via pin 1. Two
decoupling capacitors (C2=1000pF, C10=100pF)
are included on this trace. It is the responsibility of
the customer to determine proper supply decoupling
for their design application.
The Ceramic SOIC Prescaler Evaluation Board was
designed to help customers evaluate the PE9304
divide-by-2 prescaler. On this board, the device
input (pin 2) is connected to the SMA connector J1
through a 50 Ω transmission line. A series
capacitor (C3) provides the necessary DC block for
the device input. A value of 2.2pF was used for the
evaluation board; other applications may require a
different value.
The board is constructed using 4 layers. The top
and bottom layers are comprised of Rogers low loss
4350 material having a core thickness of 0.010”;
while the internal layers are comprised of FR-4.
The overall board thickness is 0.062”.
The device output (pin 7) is connected to SMA
connector J3 through a 50 Ω transmission line. A
series capacitor (C1) provides the necessary DC
block for the device output. This capacitor value
must be chosen to have low impedance at the
desired output frequency of the device. A value of
2.2pF was chosen for the evaluation board.
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 455-0660
and ask for applications support. You may also
contact us by fax or e-mail:
Fax: (858) 455-0770
E-Mail: help@peregrine-semi.com
File No. 70/0152~00A | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 4 of 6
PE9304
Preliminary Specification
Figure 9. Package Drawing
8 Lead Gullwing Glass Flatpack
.380 / .410
.210 / .250
.180 SQ MAX
Pin 1
.050 TYP
.015 TYP
.150 TYP
TOP VIEW
SIDE VIEW
.070 MAX
Table 4. Ordering Information
Order
Shipping
Method
Part Marking
Code
Description
Package
PE9304-08CFPG-1A Engineering
Samples
9304-01
PE9304
Gullwing Glass Flatpack
20 / Tray
9304-11
9304-00
PE9304
PE9304-08CFPG-1A Flight Units
PE9304 Evaluation Kit
Gullwing Glass Flatpack
Evaluation Kit
50 / Tray
1 / Box
PE9304-EK
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 5 of 6
PE9304
Preliminary Specification
Sales Offices
United States
Japan
Peregrine Semiconductor Corp.
6175 Nancy Ridge Drive
San Diego, CA 92121
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisiawaicho,
Chiyoda-ku, Tokyo, Japan
100-011
Tel 1-858-455-0660
Fax 1-858-455-0770
Tel. 011-81-3-3502-5211
Fax. 011-81-3-3502-5213
Europe
Peregrine Semiconductor Europe
Aix-En-Provence Office
Parc Club du Golf, bat 9
13856 Aix-En-Provence Cedex 3
France
Tel 33-0-4-4239-3360
Fax 33-0-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable. However,
Peregrine assumes no liability for the use of this information. Use
shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data sheet
contains design target specifications for product
development. Specifications and features may change in any
manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in devices
or systems intended for surgical implant, or in other applications
intended to support or sustain life, or in any application in which the
failure of the Peregrine product could create a situation in which
personal injury or death might occur. Peregrine assumes no liability
for damages, including consequential or incidental damages, arising
out of the use of its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right to
change specifications at any time without notice in order to
supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a PCN
(Product Change Notice).
Peregrine products are protected under one or more of the following
U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638;
5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336;
5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857;
5,416,043. Other patents are pending.
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi
are registered trademarks of Peregrine Semiconductor Corporation.
Copyright © 2002 Peregrine Semiconductor Corp. All rights reserved.
File No. 70/0152~00A | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 6 of 6
相关型号：
PE9304_06
1 GHz - 7 GHz Low Power UltraCMOS Divide-by-2 Prescaler Rad-hard for Space Applications
PSEMI
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