PE9701_技术文档

Product Specification

PE9701

3000 MHz UltraCMOS™ Integer-N PLL

Rad Hard for Space Applications

Product Description

Peregrine’s PE9701 is a high-performance integer-N PLL

capable of frequency synthesis up to 3.0 GHz. The device

is designed for superior phase noise performance while

providing an order of magnitude reduction in current

consumption, when compared with existing commercial

space PLLs.

Features

• 3.0 GHz operation

• ÷10/11 dual modulus prescaler

• Internal phase detector with charge

pump

The PE9701 features a 10/11 dual modulus prescaler,

counters, and a phase comparator as shown in Figure 1.

Counter values are programmable through either a serial or

parallel interface and can also be directly hard wired.

• Serial, parallel or hardwired

programmable

• Ultra-low phase noise

• SEU < 10^-9errors / bit-day

• 100 Krad (Si) total dose

• 44-lead CQFJ

The PE9701 is optimized for commercial space

applications. Single Event Latch up (SEL) is physically

impossible and Single Event Upset (SEU) is better than

10^-9errors per bit / day. It is manufactured on Peregrine’s

UltraCMOS™ process, a patented variation of silicon-on-

insulator (SOI) technology on a sapphire substrate, offering

excellent RF performance and intrinsic radiation tolerance.

Figure 1. Block Diagram

F_in

Prescaler

10/11

Main

Counter

f_p

13

D(7:0)

Primary

20-bit

Secon-

dary

20-bit

Latch

8

PD_U

Charge

Pump

Phase

20

Sdata

CP

Latch

Detector

20

16

PD_D

Pre_en

M(6:0)

A(3:0)

R(3:0)

6

f_r

R Counter

f_c

Document No. 70-0035-02 │ www.psemi.com

Page 1 of 13

PE9701

Product Specification

Figure 2. Pin Configurations (Top View)

Figure 3. Package Type

44-lead CQFJ

6

5

4

3

2

1

44 43 42 41 40

D₀, M₀

D₁, M₁

f_c

V

7

8

39

38

37

36

35

34

33

32

31

30

29

_DD_f_c

D₂, M₂

N/C

CP

9

D₃, M₃

10

11

12

13

14

15

16

17

V_DD

C_ext

V_DD

D_out

V_DD_f_p

f_p

V_DD

S_WR, D₄, M₄

Sdata, D₅, M₅

Sclk, D₆, M₆

FSELS, D₇, Pre_en

GND

18 19 20 21 22 23 24 25 26 27 28

Table 1. Pin Descriptions

Pin No. Pin Name

Interface Mode

Type

Description

Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing

recommended.

1

V_DD

ALL

(Note 1)

2

3

4

5

6

R₀

Direct

ALL

Input

R Counter bit0 (LSB).

R Counter bit1.

R₁

Input

R₂

Input

R Counter bit2.

R₃

Input

R Counter bit3.

GND

D₀

(Note 1)

Input

Ground.

Parallel

Direct

Parallel

Direct

Parallel

Direct

Parallel

Direct

ALL

Parallel data bus bit0 (LSB).

M Counter bit0 (LSB).

Parallel data bus bit1.

M Counter bit1.

7

8

M₀

D₁

Input

M₁

D₂

Input

9

Input

Parallel data bus bit2.

M Counter bit2.

M₂

D₃

Input

10

Input

Parallel data bus bit3.

M Counter bit3.

M₃

V_DD

Input

11

12

(Note 1)

Same as pin 1.

ALL

Same as pin 1.

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.

Primary register data is transferred to the secondary register on S_WR or Hop_WR

rising edge.

S_WR

Serial

Input

13

D₄

M₄

Parallel

Direct

Input

Parallel data bus bit4

M Counter bit4

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

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PE9701

Product Specification

Table 1. Pin Descriptions (continued)

Pin No. Pin Name

Interface Mode

Type

Description

Sdata

Serial

Input

Binary serial data input. Input data entered MSB first.

D₅

Parallel

Direct

Input

Parallel data bus bit5.

M Counter bit5.

14

15

16

M₅

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR

“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.

Sclk

D₆

Serial

Parallel

Direct

Parallel data bus bit6.

M Counter bit6.

M₆

Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for

programming of internal counters while in Serial Interface Mode.

FSELS

D₇

Serial

Parallel

Direct

Parallel data bus bit7 (MSB).

Pre_en

GND

FSELP

A₀

Prescaler enable, active “low”. When “high”, F_inbypasses the prescaler.

Ground.

17

18

ALL

Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for

programming of internal counters while in Parallel Interface Mode.

Parallel

Direct

Input

(Note 1)

Input

A Counter bit0 (LSB).

Enhancement register write enable. While E_WR is “high”, Sdata can be serially

clocked into the enhancement register on the rising edge of Sclk.

Enhancement register write. D[7:0] are latched into the enhancement register on the

rising edge of E_WR.

Serial

E_WR

19

Parallel

Direct

A₁

A Counter bit1.

M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising

edge of M2_WR.

M2_WR

A₂

Parallel

Direct

20

21

A Counter bit2.

Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode

(Bmode=0, Smode=0).

Smode

A₃

Serial, Parallel

Direct

A Counter bit3 (MSB).

Bmode

V_DD

Selects direct interface mode (Bmode=1).

Same as pin 1.

22

23

24

25

26

27

ALL

M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising

edge of M1_WR.

A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge

of A_WR.

Hop write. The contents of the primary register are latched into the secondary

register on the rising edge of Hop_WR.

M1_WR

A_WR

Hop_WR

F_in

Parallel

Serial, Parallel

ALL

Prescaler input from the VCO. 3.0 GHz max frequency.

Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor

should be placed as close as possible to this pin and be connected directly to the

ground plane.

F_in

28

ALL

Input

29

30

GND

f_p

ALL

Ground.

Monitor pin for main divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding V_DDpin 31.

Output

Document No. 70-0035-02 │ www.psemi.com

Page 3 of 13

PE9701

Product Specification

Table 1. Pin Descriptions (continued)

Pin No. Pin Name

Interface Mode

Type

Description

31

32

33

V_DD-f_p

Dout

V_DD

ALL

(Note 1)

V_DDfor f_p

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

Serial, Parallel

ALL

Output

(Note 1)

Same as pin 1.

Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.

Connecting Cext to an external capacitor will low pass filter the input to the inverting

amplifier used for driving LD.

34

Cext

ALL

Output

35

36

37

38

39

40

41

42

43

44

V_DD

CP

NC

V_DD-f_c

f_c

ALL

(Note 1)

Output

Same as pin 1.

Charge pump current is sourced for “up” when f_cleads f_pand sinked for “down”

when f_clags f_p.

ALL

No connection.

V_DDfor f_c

ALL

(Note 1)

Output

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding V_DDpin 38.

ALL

GND

f_r

ALL

Ground.

ALL

Ground.

ALL

Input

Reference frequency input.

Output,

OD

Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is

high impedance, otherwise LD is a logic low (“0”).

LD

ALL

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

Enh

Serial, Parallel

Input

Note 1: V_DDpins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

V_DDpins 31 and 38 are used to enable test modes and should be left floating.

Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

Page 4 of 13

PE9701

Product Specification

Table 2. Absolute Maximum Ratings

Table 4. ESD Ratings

Symbol

Parameter/Conditions

Level

Units

Symbol

Parameter/Conditions Min Max Units

ESD voltage (Human Body

Model) – Note 1

V_DD

V_I

Supply voltage

-0.3

-10

4.0

V

V_ESD

1000

V

V_DD

+ 0.3

Voltage on any input

DC into any input

DC into any output

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

I_I

+10

mA

Electrostatic Discharge (ESD) Precautions

I_O

Storage temperature

range

When handling this UltraCMOS™ device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating in Table 4.

T_stg

-65

150

°C

Table 3. Operating Ratings

Symbol

Parameter/Conditions Min Max Units

V_DD

Supply voltage

2.85

-40

3.15

85

V

Latch-Up Avoidance

Operating ambient

temperature range

T_A

°C

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Table 5. DC Characteristics: V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

I_DD

Operational supply current;

Prescaler disabled

V_DD= 2.85 to 3.15 V

10

24

mA

Prescaler enabled

31

Digital Inputs: All except f_r, F_in, F_in

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

V_DD= 2.85 to 3.15 V

V_IH= V_DD= 3.15 V

0.7 x V_DD

V

0.3 x V_DD

+70

µA

I_IL

V_IL= 0, V_DD= 3.15 V

-1

Reference Divider input: f_r

I_IHRHigh level input current

I_ILR

V_IH= V_DD= 3.15 V

+100

+70

0.4

µA

Low level input current

V_IL= 0, V_DD= 3.15 V

-100

R0 Input: R₀

I_IHRO

High level input current

Low level input current

V_IH= V_DD= 3.15 V

µA

I_ILRO

V_IL= 0, V_DD= 3.15 V

-5

Counter and phase detector outputs: f_c, f_p.

V_OLD

V_OHD

Output voltage LOW

Output voltage HIGH

I_out= 6 mA

I_out= -3 mA

V

V_DD- 0.4

Lock detect outputs: Cext, LD

V_OLC

V_OHC

V_OLLD

Output voltage LOW, Cext

I_out= 100 µA

I_out= -100 µA

I_out= 6 mA

0.4

V

Output voltage HIGH, Cext

Output voltage LOW, LD

Charge Pump output: CP

I_CP- Source

I_CP– Sink

I_CPL

Drive current

V_CP= V_DD/ 2

-2.6

1.4

-1

-2

2

-1.4

2.6

1

mA

µA

%

Drive current

V_CP= V_DD/ 2

Leakage current

Sink vs. source mismatch

1.0 V < V_CP< V_DD– 1.0 V

I_CP– Source

vs. I_CPSink

VCP = V_DD/ 2,

T_A= 25° C

25

I_CPvs. V_CP

Output current magnitude variation vs. voltage

V < V_CP< V_DD– 1.0 V

T_A= 25° C

25

%

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PE9701

Product Specification

Table 6. AC Characteristics: V_DD= 3.0 V, -40° C < T_A< 85° C, unless otherwise specified

Symbol

Parameter

Conditions

Min

Max

Units

Control Interface and Latches (see Figures 4, 5, 6)

f_Clk

t_ClkH

t_ClkL

Serial data clock frequency

Serial clock HIGH time

Serial clock LOW time

(Note 1)

10

MHz

ns

30

ns

Sdata hold time after Sclk rising edge, D[7:0] set-up time to

M1_WR, M2_WR, A_WR, E_WR rising edge

t_DSU

10

ns

Sdata hold time after Sclk rising edge, D[7:0] hold time to

M1_WR, M2_WR, A_WR, E_WR rising edge

t_DHLD

t_PW

t_CWR

t_CE

10

30

ns

S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width

Sclk rising edge to S_WR rising edge. S_WR, M1_WR,

M2_WR, A_WR falling edge to Hop_WR rising edge

Sclk falling edge to E_WR transition

S_WR falling edge to Sclk rising edge. Hop_WR falling

edge to S_WR, M1_WR, M2_WR, A_WR rising edge

t_WRC

t_EC

E_WR transition to Sclk rising edge

ns

t_MDO

MSEL data out delay after Fin rising edge

C_L= 12 pf

8

Main Divider (Prescaler Enabled)

F_in

Operating frequency

Input level range

500

-5

3000

5

MHz

dBm

P_Fin

External AC coupling

Main Divider (Prescaler Bypassed)

F_in

Operating frequency

Input level range

50

-5

300

5

MHz

dBm

P_Fin

Reference Divider

f_r

Operating frequency

(Note 3)

100

MHz

dBm

P_fr

Reference input power (Note 2)

Single-ended input

-2

Phase Detector

f_c

Comparison frequency

(Note 3)

20

MHz

Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk

specification.

Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 V_p-p

.

Note 3: Parameter is guaranteed through characterization only, and is not tested.

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

Page 6 of 13

PE9701

Product Specification

Functional Description

The PE9701 consists of a prescaler, counters, a

phase detector, a charge pump, and control logic.

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the

value of the modulus select. Counters “R” and

“M” divide the reference and prescaler output,

respectively, by integer values stored in a 20-bit

register. An additional counter (“A”) is used in the

modulus select logic. The phase-frequency

detector generates up and down frequency control

signals. The control logic includes a selectable

chip interface. Data can be written via serial bus,

parallel bus, or hardwired directly to the pins.

There are also various operational and test modes

and a lock detect output.

Figure 4. Functional Block Diagram

R Counter

f_r

f_c

(6-bit)

PD_U

R(5:0)

M(8:0)

A(3:0)

D(7:0)

Sdata

Control

Pins

Phase

Control

Logic

Charge

PD_D

CP

Detector

Pump

LD

Cext

2 kΩ

Modulus

Select

F_in

10/11

M Counter

(9-bit)

f_p

Prescaler

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Page 7 of 13

PE9701

Product Specification

Main Counter Chain

Reference Counter

The reference counter chain divides the

reference frequency, f_r, down to the phase

detector comparison frequency, f_c.

Normal Operating Mode

The main counter chain divides the RF input

frequency, F_in, by an integer derived from the

user-defined values in the “M” and “A” counters. It

is composed of the 10/11 dual modulus prescaler,

modulus select logic, and 9-bit M counter. Setting

Pre_en “low” enables the 10/11 prescaler. Setting

Pre_en “high” allows F_into bypass the prescaler

and powers down the prescaler.

The output frequency of the 6-bit R Counter is

related to the reference frequency by the

following equation:

f_c= f_r/ (R + 1)

(4)

where 0 ≤ R ≤ 63

The output from the main counter chain, f_p, is

related to the VCO frequency, F_in, by the following

equation:

Note that programming R with “0” will pass the

reference frequency, f_r, directly to the phase

detector.

f_p= F_in/ [10 x (M + 1) + A]

(1)

where A ≤ M + 1, 1 ≤ M ≤ 511

In Direct Interface Mode, R Counter inputs R₄

and R₅are internally forced low (“0”). In this

mode, the R value is limited to 0 ≤ R ≤ 15.

When the loop is locked, F_inis related to the

reference frequency, f_r, by the following equation:

Register Programming

F_in= [10 x (M + 1) + A] x (f_r/ (R+1))

(2)

Parallel Interface Mode

where A ≤ M + 1, 1 ≤ M ≤ 511

Parallel Interface Mode is selected by setting the

Bmode input “low” and the Smode input “low”.

A consequence of the upper limit on A is that F_in

must be greater than or equal to 90 x (f_r/ (R+1)) to

obtain contiguous channels. Programming the M

Counter with the minimum value of “1” will result in

a minimum M Counter divide ratio of “2”.

Parallel input data, D[7:0], is latched in a parallel

fashion into one of three 8-bit primary register

sections on the rising edge of M1_WR, M2_WR,

or A_WR per the mapping shown in Table 7 on

page 9. The contents of the primary register are

transferred into a secondary register on the

rising edge of Hop_WR according to the timing

diagram shown in Figure 5. Data is transferred

to the counters as shown in Table 7 on page 9.

In Direct Interface Mode, main counter inputs M₇

and M₈are internally forced low. In this mode, the

M value is limited to 1 ≤ M ≤ 127.

Prescaler Bypass Mode

The secondary register acts as a buffer to allow

rapid changes to the VCO frequency. This

double buffering for “ping-pong” counter control

is programmed via the FSELP input. When

FSELP is “high”, the primary register contents

set the counter inputs. When FSELP is “low”,

the secondary register contents are utilized.

Setting Pre_en “high” allows F_into bypass and

power down the prescaler. In this mode, the

10/11 prescaler and A register are not active, and

the input VCO frequency is divided by the M

counter directly. The following equation relates F_in

to the reference frequency, f_r:

F_in= (M + 1) x (f_r/ (R+1)) )

(3)

Parallel input data, D[7:0], is latched into the

enhancement register on the rising edge of

E_WR according to the timing diagram shown in

Figure 5. This data provides control bits as

shown in Table 8 on page 9 with bit functionality

enabled by asserting the Enh input “low”

where 1 ≤ M ≤ 511

In Direct Interface Mode, main counter inputs M₇

and M₈are internally forced low. In this mode, the

M value is limited to 1 ≤ M ≤ 127.

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

Page 8 of 13

PE9701

Product Specification

Serial Interface Mode

Serial Interface Mode is selected by setting the

Bmode input “low” and the Smode input “high”.

While the E_WR input is “low” and the S_WR

input is “low”, serial input data (Sdata input), B₀to

B₁₉, is clocked serially into the primary register on

the rising edge of Sclk, MSB (B₀) first. The

contents from the primary register are transferred

into the secondary register on the rising edge of

either S_WR or Hop_WR according to the timing

diagram shown in Figure 6. Data is transferred to

the counters as shown in Table 7 on page 9.

B₇, is clocked serially into the enhancement

register on the rising edge of Sclk, MSB (B₀) first.

The enhancement register is double buffered to

prevent inadvertent control changes during serial

loading, with buffer capture of the serially-entered

data performed on the falling edge of E_WR

according to the timing diagram shown in Figure

6. After the falling edge of E_WR, the data

provides control bits as shown in Table 8 with bit

functionality enabled by asserting the Enh input

“low”.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input “high”.

The double buffering provided by the primary and

secondary registers allows for “ping-pong” counter

control using the FSELS input. When FSELS is

“high”, the primary register contents set the

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

counter inputs M₇and M₈, and R Counter inputs

R₄and R₅are internally forced low (“0”).

counter inputs.

When FSELS is “low”, the

secondary register contents are utilized.

While the E_WR input is “high” and the S_WR

input is “low”, serial input data (Sdata input), B₀to

Table 7. Primary Register Programming

Interface

Mode

Smode

R₅

R₄

M₈

M₇

M₆

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

Enh

Bmode

Pre_en

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Parallel

1

0

1

0

1

D₃

B₀

D₂

B₁

D₁

B₂

D₀

B₃

D₇

B₄

D₆

B₅

D₅

B₆

D₄

B₇

D₃

B₈

D₂

B₉

D₁

D₀

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

Serial*

Direct

B₁₀

B₁₁

B₁₂

B₁₃

B₁₄

B₁₅

B₁₆

B₁₇

B₁₈B₁₉

X

0

Pre_en M₆

M₅

M₄

M₃

M₂

M₁

M₀

R₃

R₂

R₁

R₀

A₃

A₂

A₁

A₀

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

Power

down

Counter

load

MSEL

output

Prescaler

output

Smode

Reserved

f_c, f_pOE

Enh

Bmode

E_WR rising edge load

Parallel

Serial*

0

1

D₇

B₀

D₆

B₁

D₅

B₂

D₄

D₃

D₂

B₅

D₁

B₆

D₀

B₇

0

B₃

B₄

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB

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Page 9 of 13

PE9701

Product Specification

Figure 5. Parallel Interface Mode Timing Diagram

t_DSU

t_DHLD

[7: 0]

D

t_PW

t_CWR

t_WRC

M1_WR

M2_WR

A_WR

t_PW

E_WR

Hop_WR

Figure 6. Serial Interface Mode Timing Diagram

Sdata

E_WR

t_EC

t_CE

Sclk

S_WR

t_DSU

t_DHLD

t_ClkH

t_ClkL

t_CWR

t_PW

t_WRC

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

Page 10 of 13

PE9701

Product Specification

Enhancement Register

The functions of the enhancement register bits are shown below with all bits active “high”.

Table 9. Enhancement Register Bit Functionality

Bit Function

Description

Bit 0

Bit 1

Bit 2

Bit 3

Reserved**

Power down

Power down of all functions except programming interface.

Immediate and continuous load of counter programming as directed by the Bmode and

Bit 4

Counter load

Smode inputs.

Bit 5

Bit 6

Bit 7

MSEL output

Prescaler output

f_p, f_cOE

Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.

Drives the raw internal prescaler output (fmain) onto the Dout output.

f_p, f_coutputs disabled.

** Program to 0

Phase Detector

The phase detector is triggered by rising edges

from the main Counter (f_p) and the reference

counter (f_c). It has two outputs, namely PD_U,

and PD_D. If the divided VCO leads the divided

reference in phase or frequency (f_pleads f_c),

PD_D pulses “high”. If the divided reference leads

the divided VCO in phase or frequency (f_rleads

f_p), PD_U pulses “high”. The width of either pulse

is directly proportional to phase offset between the

two input signals, f_pand f_c.

pin CP. The current pulses from pin CP are low

pass filtered externally and then connected to the

VCO tune voltage. PD_U pulses result in a

current source, which increases the VCO

frequency; PD_D pulses result in a current sink,

which decreases VCO frequency.

A lock detect output, LD is also provided, via the

pin Cext. Cext is the logical “NAND” of PD_U and

PD_D waveforms, which is driven through a series

2k Ω resistor. Connecting Cext to an external

shunt capacitor provides integration. Cext also

drives the input of an internal inverting comparator

with an open drain output. Thus LD is an “AND”

function of PD_U and PD_D. See Figure 4 for a

schematic of this circuit.

The signals from the phase detector couple

directly to a charge pump. PD_U controls a

current source at pin CP with constant amplitude

and pulse duration approximately the same as

PD_U. PD_D similarly drives a current sink at

Document No. 70-0035-02 │ www.psemi.com

Page 11 of 13

PE9701

Product Specification

Figure 9. Package Drawing

44-lead CQFJ

All dimensions are in mils

Table 10. Ordering Information

Order Code

9701-01

Part Marking

PE9701 ES

PE9701

Description

Package

Shipping Method

40 units / Tray

1 / Box

Engineering Samples

44-pin CQFJ

9701-11

Flight Units

9701-00

PE9701 EK

Evaluation Kit

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

Page 12 of 13

PE9701

Product Specification

Sales Offices

The Americas

North Asia Pacific

Peregrine Semiconductor Corporation

Peregrine Semiconductor K.K.

9450 Carroll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Teikoku Hotel Tower 10B-6

1-1-1 Uchisaiwai-cho, Chiyoda-ku

Tokyo 100-0011 Japan

Fax: 858-731-9499

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

Europe

Peregrine Semiconductor, Korea

#B-2402, Kolon Tripolis, #210

Geumgok-dong, Bundang-gu, Seongnam-si

Gyeonggi-do, 463-480 S. Korea

Tel: +82-31-728-4300

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F-92380 Garches, France

Tel: +33-1-47-41-91-73

Fax : +33-1-47-41-91-73

Fax: +82-31-728-4305

South Asia Pacific

Space and Defense Products

Americas:

Peregrine Semiconductor, China

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Tel: 858-731-9453

Fax: +86-21-5836-7652

Europe, Asia Pacific:

180 Rue Jean de Guiramand

13852 Aix-En-Provence Cedex 3, France

Tel: +33(0) 4 4239 3361

Fax: +33(0) 4 4239 7227

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The information in this data sheet is believed to be reliable.

However, Peregrine assumes no liability for the use of this

information. Use shall be entirely at the user’s own risk.

The product is in a formative or design stage. The data

sheet contains design target specifications for product

development. Specifications and features may change in

any manner without notice.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Preliminary Specification

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including

consequential or incidental damages, arising out of the use of

its products in such applications.

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data. In the event Peregrine

decides to change the specifications, Peregrine will notify

customers of the intended changes by issuing a DCN

(Document Change Notice).

The Peregrine name, logo, and UTSi are registered trademarks

and UltraCMOS and HaRP are trademarks of Peregrine

Semiconductor Corp.

Document No. 70-0035-02 │ www.psemi.com

Page 13 of 13


型号：	PE9701
厂家：	Peregrine Semiconductor
描述：	3000 MHz UltraCMOS? Integer-N PLL Rad Hard for Space Applications 3000兆赫的UltraCMOS ？整数N分频PLL抗辐射的空间应用
文件：	总13页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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