PE9702ES [PSEMI]
3.0 GHz Integer-N PLL for Rad Hard Applications; 3.0 GHz的整数N分频PLL，抗辐射应用
| 型号： | PE9702ES |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | 3.0 GHz Integer-N PLL for Rad Hard Applications |
| 文件： | 总14页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
PE9702
3.0 GHz Integer-N PLL for Rad
Product Description
Hard Applications
Peregrine’s PE9702 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in
current consumption, when compared with existing
commercial space PLLs.
Features
• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial, parallel or hardwired
programmable
The PE9702 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial
or parallel interface and can also be directly hard wired.
• Ultra-low phase noise
• SEU < 10-9 errors / bit-day
• 100 Krad (Si) total dose
• 44-lead CQFJ
The PE9702 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than
10-9 errors per bit / day. Fabricated in Peregrine’s
patented UTSi® (Ultra Thin Silicon) CMOS technology,
the PE9702 offers excellent RF performance and intrinsic
radiation tolerance.
Figure 1. Block Diagram
Fin
Fin
Prescaler
10 / 11
Main
fp
Counter
13
D(7:0)
8
Sdata
Primary
20-bit
Secon-
dary
PD_U
Phase
20
20
20
Latch
20-bit
Latch
20
16
Detector
PD_D
Pre_en
M(6:0)
A(3:0)
R(3:0)
6
6
fr
R Counter
fc
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PE9702
Advance Information
Figure 2. Pin Configuration
6
5
4
3
2
1
44 43 42 41 40
D0, M0
D1, M1
fc
V
7
8
39
38
37
36
35
34
33
32
31
30
29
DD_fc
D2, M2
PD_U
PD_D
VDD
9
D3, M3
10
11
12
13
14
15
16
17
VDD
VDD
Cext
S_WR, D4, M4
Sdata, D5, M5
Sclk, D6, M6
FSELS, D7, Pre_en
GND
VDD
Dout
VDD_fp
fp
GND
18 19 20 21 22 23 24 25 26 27 28
Table 1. Pin Descriptions
Pin No.
Pin Name
Interface Mode
ALL
Type
(Note 1)
Input
Description
1
VDD
R0
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended.
2
3
4
5
6
Direct
Direct
Direct
Direct
ALL
R Counter bit0 (LSB).
R Counter bit1.
R1
Input
R2
Input
R Counter bit2.
R3
Input
R Counter bit3.
GND
D0
(Note 1)
Input
Ground.
Parallel
Direct
Parallel
Direct
Parallel
Direct
Parallel
Direct
ALL
Parallel data bus bit0 (LSB).
M Counter bit0 (LSB).
Parallel data bus bit1.
M Counter bit1.
7
8
M0
D1
Input
Input
M1
D2
Input
9
Input
Parallel data bus bit2.
M Counter bit2.
M2
D3
Input
10
Input
Parallel data bus bit3.
M Counter bit3.
M3
VDD
VDD
Input
11
12
(Note 1)
(Note 1)
Same as pin 1.
ALL
Same as pin 1.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary
register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
13
S_WR
Serial
Input
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PE9702
Advance Information
Pin No.
Pin Name
Interface Mode
Parallel
Type
Input
Description
D4
Parallel data bus bit4
M Counter bit4
M4
Direct
Input
Input
Input
Input
Sdata
D5
Serial
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
14
Parallel
M5
Direct
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Sclk
Serial
Input
15
16
D6
Parallel
Direct
Input
Input
Parallel data bus bit6.
M Counter bit6.
M6
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
FSELS
Serial
Input
D7
Parallel
Direct
ALL
Input
Input
Parallel data bus bit7 (MSB).
Pre_en
GND
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
17
18
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
FSELP
A0
Parallel
Direct
Serial
Input
Input
Input
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
E_WR
19
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
Parallel
Direct
Input
Input
Input
Input
Input
A1
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge
of M2_WR.
M2_WR
A2
Parallel
Direct
20
21
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
Smode
Serial, Parallel
A3
Direct
ALL
Input
A Counter bit3 (MSB).
22
23
Bmode
VDD
Input
Selects direct interface mode (Bmode=1).
Same as pin 1.
ALL
(Note 1)
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
24
25
M1_WR
A_WR
Parallel
Parallel
Input
Input
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.
Hop write. The contents of the primary register are latched into the secondary register
on the rising edge of Hop_WR.
26
27
Hop_WR
Fin
Serial, Parallel
ALL
Input
Input
Prescaler input from the VCO. 3.0 GHz max frequency.
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
28
Fin
ALL
Input
29
30
GND
fp
ALL
ALL
Ground.
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
Output
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PE9702
Advance Information
Pin No.
31
Pin Name
Interface Mode
ALL
Type
Description
VDD-fp
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
Data Out. The MSEL signal and the raw prescaler output are available on Dout through
enhancement register programming.
32
33
Dout
VDD
Serial, Parallel
ALL
Output
(Note 1)
Same as pin 1.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
34
Cext
ALL
Output
35
36
37
38
VDD
ALL
ALL
ALL
ALL
(Note 1)
Output
Same as pin 1.
PD_D
PD_U
VDD-fc
PD_D is pulse down when fp leads fc.
PD_U is pulse down when fc leads fp.
(Note 1)
Output
VDD for fc. Can be left floating or connected to GND to disable the fc output.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
39
fc
ALL
40
41
42
GND
GND
fr
ALL
ALL
ALL
Ground.
Ground.
Input
Reference frequency input.
Output,
OD
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
43
44
LD
ALL
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Enh
Serial, Parallel
Input
Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
VDD pins 31 and 38 are used to enable test modes and should be left floating.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
File No. 70/0036~00C | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
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PE9702
Advance Information
Table 2. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 4.
Symbol
Parameter/Conditions Min Max Units
VDD
VI
Supply voltage
Voltage on any input
-0.3
-0.3
4.0
V
V
VDD
+ 0.3
II
IO
Tstg
DC into any input
DC into any output
Storage temperature
range
-10
-10
-65
+10
+10
150
mA
mA
°C
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
Table 3. Operating Ratings
devices are immune to latch-up.
Symbol
Parameter/Conditions Min Max Units
VDD
TA
Supply voltage
Operating ambient
temperature range
2.85
-40
3.15
85
V
°C
Table 4. ESD Ratings
Symbol
VESD
Parameter/Conditions
ESD voltage (Human Body
Model) – Note 1
Level Units
1000
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
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PE9702
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Table 5. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Operational supply current;
Conditions
VDD = 2.85 to 3.15 V
Min
Typ
Max
Units
IDD
Prescaler disabled
Prescaler enabled
10
24
mA
mA
31
Digital Inputs: All except fr, Fin, Fin
VIH
VIL
IIH
High level input voltage
VDD = 2.85 to 3.15 V
VDD = 2.85 to 3.15 V
VIH = VDD = 3.15 V
VIL = 0, VDD = 3.15 V
0.7 x VDD
V
V
Low level input voltage
High level input current
Low level input current
0.3 x VDD
+70
µA
µA
IIL
-1
Reference Divider input: fr
IIHR
High level input current
VIH = VDD = 3.15 V
+100
+70
0.4
µA
µA
IILR
R0 Input: R0
IIHR
Low level input current
VIL = 0, VDD = 3.15 V
-100
High level input current
Low level input current
VIH = VDD = 3.15 V
µA
µA
IILR
VIL = 0, VDD = 3.15 V
-5
Counter and phase detector outputs: fc, fp.
VOLD
VOHD
Output voltage LOW
Output voltage HIGH
Iout = 6 mA
Iout = -3 mA
V
V
VDD - 0.4
VDD - 0.4
Lock detect outputs: Cext, LD
VOLC
VOHC
VOLLD
Output voltage LOW, Cext
Output voltage HIGH, Cext
Output voltage LOW, LD
Iout = 100 mA
Iout = -100 mA
Iout = 6 mA
0.4
0.4
V
V
V
File No. 70/0036~00C | UTSi CMOS RFIC SOLUTIONS
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PE9702
Advance Information
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
(Note 1)
Min
Max
Units
Control Interface and Latches (see Figures 3, 4, 5)
fClk
tClkH
tClkL
tDSU
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time after Sclk rising edge, D[7:0] set-up time
to M1_WR, M2_WR, A_WR, E_WR rising edge
10
MHz
ns
ns
30
30
10
ns
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
tPW
tCWR
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
30
30
ns
ns
tCE
tWRC
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
30
30
ns
ns
tEC
tMDO
E_WR transition to Sclk rising edge
MSEL data out delay after Fin rising edge
30
ns
ns
CL = 12 pf
8
Main Divider (Including Prescaler)
Fin
PFin
Operating frequency
Input level range
500
-5
3000
5
MHz
dBm
External AC coupling
External AC coupling
Main Divider (Prescaler Bypassed)
Fin
PFin
Operating frequency
Input level range
50
-5
300
5
MHz
dBm
Reference Divider
fr
Pfr
Operating frequency
Reference input power (Note 2)
(Note 3)
Single-ended input
100
MHz
dBm
-2
Phase Detector
fc
Comparison frequency
(Note 3)
20
MHz
Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p
.
Note 3: Parameter is guaranteed through characterization only and is not tested.
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Functional Description
The PE9702 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired directly to the pins. There
are also various operational and test modes and a
lock detect output.
Figure 3. Functional Block Diagram
R Counter
fr
fc
(6-bit)
D(7:0)
Sdata
R(5:0)
M(8:0)
A(3:0)
PD_U
PD_D
Phase
Control
Logic
Detector
Control
Pins
LD
Cext
Modulus
Select
Fin
Fin
10/11
M Counter
(9-bit)
fp
Prescaler
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PE9702
Advance Information
Main Counter Chain
Reference Counter
Normal Operating Mode
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the user-
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9-bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
fc = fr / (R + 1)
(4)
where 0 ≤ R ≤ 63
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
Note that programming R with “0” will pass the
reference frequency, fr, directly to the phase
detector.
In Direct Interface Mode, R Counter inputs R4 and
R5 are internally forced low (“0”). In this mode, the
R value is limited to 0 ≤ R ≤ 15.
fp = Fin / [10 x (M + 1) + A]
(1)
where A ≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
(2)
Register Programming
Parallel Interface Mode
where A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low. In this mode, the
M value is limited to 1 ≤ M ≤ 127.
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
Parallel input data, D[7:0], are latched in a parallel
fashion into one of three 8-bit primary register
sections on the rising edge of M1_WR, M2_WR, or
A_WR per the mapping shown in Table 7 on page
10. The contents of the primary register are
transferred into a secondary register on the rising
edge of Hop_WR according to the timing diagram
shown in Figure 5. Data is transferred to the
counters as shown in Table 7 on page 10.
Prescaler Bypass Mode
Setting Pre_en “high” allows Fin to bypass and
power down the prescaler. In this mode, the 10/11
prescaler and A register are not active, and the
input VCO frequency is divided by the M counter
directly. The following equation relates Fin to the
reference frequency, fr:
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This double
buffering for “ping-pong” counter control is
programmed via the FSELP input. When FSELP is
“high”, the primary register contents set the counter
inputs. When FSELP is “low”, the secondary
register contents are utilized.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of E_WR
according to the timing diagram shown in Figure 4.
This data provides control bits as shown in Table 8
on page 10 with bit functionality enabled by
asserting the Enh input “low”.
Fin = (M + 1) x (fr / (R+1)) )
(3)
where 1 ≤ M ≤ 511
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low. In this mode, the
M value is limited to 1 ≤ M ≤ 127.
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Serial Interface Mode
clocked serially into the enhancement register on
the rising edge of Sclk, MSB (B0) first. The
enhancement register is double buffered to prevent
inadvertent control changes during serial loading,
with buffer capture of the serially-entered data
performed on the falling edge of E_WR according to
the timing diagram shown in Figure 5. After the
falling edge of E_WR, the data provides control bits
as shown in Table 8 with bit functionality enabled by
asserting the Enh input “low”.
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
While the E_WR input is “low” and the S_WR input
is “low”, serial input data (Sdata input), B0 to B19, is
clocked serially into the primary register on the
rising edge of Sclk, MSB (B0) first. The contents
from the primary register are transferred into the
secondary register on the rising edge of either
S_WR or Hop_WR according to the timing diagram
shown in Figure 6. Data is transferred to the
counters as shown in Table 7 on page 10.
Direct Interface Mode
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the counter
inputs. When FSELS is “low”, the secondary
register contents are utilized.
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs R4
and R5 are internally forced low (“0”).
While the E_WR input is “high” and the S_WR input
is “low”, serial input data (Sdata input), B0 to B7, is
Table 7. Primary Register Programming
Interface
Enh
Bmode Smode
R5
R4
M8
M7 Pre_en M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Mode
Parallel
1
0
0
M2_WR rising edge load
M1_WR rising edge load
A_WR rising edge load
D3
B0
D2
B1
D1
B2
D0
B3
D7
B4
D6
B5
D5
B6
D4
B7
D3
B8
D2
B9
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Serial*
Direct
1
1
0
1
1
B10
B11
B12
B13
B14
B15
B16
B17
B18 B19
X
0
0
0
0
Pre_en M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1 A0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Power
down
Counter
load
MSEL
Prescaler
output
Enh
Bmode Smode
Reserved
Reserved
Reserved
fc, fp OE
Mode
output
E_WR rising edge load
Parallel
Serial*
0
0
0
0
0
1
D7
B0
D6
B1
D5
B2
D4
B3
D3
B4
D2
B5
D1
B6
D0
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
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Copyright Peregrine Semiconductor Corp. 2003
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PE9702
Advance Information
Figure 4. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
7 : 0
[ ]
D
tPW
tCWR
tWRC
M1_WR
M2_WR
A_WR
tPW
E_WR
Hop_WR
Figure 5. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
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Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Reserved**
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Reserved**
Reserved**
Power down
Counter load
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and
Smode inputs.
Bit 5
Bit 6
Bit 7
MSEL output
Prescaler output
fp, fc OE
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the raw internal prescaler output (fmain) onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc), PD_D
pulses “low”. If the divided reference leads the
divided VCO in phase or frequency (fr leads fp),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, fp and fc. The phase detector gain
is 430 mV / radian.
PD_U pulses result in an increase in VCO
frequency and PD_D results in a decrease in VCO
frequency.
A lock detect output, LD is also provided, via the pin
Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2k ohm resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D. See Figure 3 for a
schematic of this circuit.
PD_U and PD_D are designed to drive an active
loop filter which controls the VCO tune voltage.
File No. 70/0036~00C | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 12 of 15
PE9702
Advance Information
Figure 6. Package Drawing
44-lead CQFJ
All dimensions are in mils
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright Peregrine Semiconductor Corp. 2003
Page 13 of 15
PE9702
Advance Information
Table 10. Ordering Information
Order
Shipping
Method
40 units / Tray
40 units / Tray
1 / Box
Part Marking
Description
Engineering Samples
Flight Units
Evaluation Kit
Package
44-pin CQFJ
Code
9702-01
9702-11
9702-00
PE9702 ES
PE9702
PE9702 EK
44-pin CQFJ
File No. 70/0036~00C | UTSi CMOS RFIC SOLUTIONS
Copyright Peregrine Semiconductor Corp. 2003
Page 14 of 15
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