HYS72D64300GU-5-B [QIMONDA]
42184-Pin Unbuffered Double-Data-Rate Memory Modules; 42184针无缓冲双倍数据速率内存模块
| 型号： | HYS72D64300GU-5-B |
| 厂家： | 
QIMONDA AG |
| 描述： | 42184-Pin Unbuffered Double-Data-Rate Memory Modules |
| 文件： | 总42页 (文件大小：2531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
HYS64D32301[G/H]U–5–B
HYS[64/72]D64xxx[G/H]U–[5/6]–B
HYS[64/72]D128xxx[G/H]U–[5/6]–B
184-Pin Unbuffered Double-Data-Rate Memory Modules
UDIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.22
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
HYS64D32301[G/H]U–5–B, HYS[64/72]D64xxx[G/H]U–[5/6]–B, HYS[64/72]D128xxx[G/H]U–[5/6]–B
Revision History: 2007-01, Rev. 1.22
Page
Subjects (major changes since last revision)
Adapted internet edition
All
23
t
t
DQSS min from 0.75ns to 0.72ns
RFC min from 70ns to 65ns
Previous Revision: 2006-09, Rev. 1.21
All Qimonda update
Previous Revision: 1.2
4
Added new product type
16
18
20
Added raw card C Diagram
Updated IDD values
Added SPD Code for new product type
Previous Revision: Rev. 1.1
We Listen to Your Comments
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21
03292006-CXBY-V2JX
2
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
1
Overview
This chapter contains features and the description.
1.1
Features
•
184-Pin Unbuffered Double-Data-Rate Memory Modules
(ECC and non-parity) for PC and Workstation main
memory applications
One rank 32M × 64, 64M x 64, 64M ×72 and two ranks
128M × 64, 128M ×72 organization
standard Double Data Rate Synchronous DRAMs Single
+2.5V (± 0.2V) power supply
Built with 512-Mbit in P-TSOPII-66 package
Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
•
•
•
•
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor:
133.35 mm × 31.75 mm × 4.00 mm max.
Standard reference layout
Gold plated contacts
DDR400 speed grade supported
Lead-free
•
•
•
•
•
•
•
•
TABLE 1
Performance for –5 and –6
Part Number Speed Code
–5
–6
Unit
Speed Grade
Component
Module
@CL3
DDR400B
PC3200 - 3033
200
DDR333B
PC2700 - 2533
166
—
—
Max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1.2
Description
The Qimonda HYS64D32301[G/H]U–5–B, HYS[64/72]D64xxx[G/H]U–
[5/6]–B and HYS[64/72]D128xxx[G/H]U–[5/6]–B are industry standard
184-Pin Unbuffered Double-Data-Rate Memory Modules (UDIMM)
organized as 32M × 64M (256 MB), 64M ×64 (512 MB),
128M ×64 (1 GB) for non-parity and 64M ×72 (512 MB),
128M ×72 (1 GB) for ECC main memory applications. The
memory array is designed with 512Mbit Double Data Rate
Synchronous DRAMs. A variety of decoupling capacitors are
mounted on the printed circuit board. The DIMMs feature
serial presence detect (SPD) based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
Rev. 1.22, 2007-01
3
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
PC3200 (CL=3.0)
HYS64D64300GU–5–B
HYS72D64300GU–5–B
HYS64D128320GU–5–B
HYS72D128320GU–5–B
PC2700 (CL=2.5)
PC3200U–30330–A0
PC3200U–30330–A0
PC3200U–30330–B0
PC3200U–30330–B0
one rank 512 MB DIMM
one rank 512 MB ECC-DIMM
two ranks 1 GB DIMM
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
two ranks 1 GB ECC-DIMM
HYS64D64300GU–6–B
HYS72D64300GU–6–B
HYS64D128320GU–6–B
HYS72D128320GU–6–B
PC3200 (CL=3.0)
PC2700U–25330–A0
PC2700U–25330–A0
PC2700U–25330–B0
PC2700U–25330–B0
one rank 512 MB DIMM
one rank 512 MB ECC-DIMM
two ranks 1 GB DIMM
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
two ranks 1 GB ECC-DIMM
HYS64D32301HU–5–B
HYS64D64300HU–5–B
HYS72D64300HU–5–B
HYS64D128320HU–5–B
HYS72D128320HU–5–B
PC2700 (CL=2.5)
PC3200U–30330–C0
PC3200U–30330–A0
PC3200U–30330–A0
PC3200U–30330–B0
PC3200U–30330–B0
one rank 256 MB DIMM
one rank 512 MB DIMM
one rank 512 MB ECC-DIMM
two ranks 1 GB DIMM
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
two ranks 1 GB ECC-DIMM
HYS64D64300HU–6–B
HYS72D64300HU–6–B
HYS64D128320HU–6–B
HYS72D128320HU–6–B
PC2700U–25330–A0
PC2700U–25330–A0
PC2700U–25330–B0
PC2700U–25330–B0
one rank 512 MB DIMM
one rank 512 MB ECC-DIMM
two ranks 1 GB DIMM
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
two ranks 1 GB ECC-DIMM
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is
printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition
(for example “20330” means CAS latency of 2.0 clocks, RCD (Row-Column-Delay) latency of 3 clocks, Row Precharge
latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
Rev. 1.22, 2007-01
4
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM DIMM
is listed by function in Table 3 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 4
and Table 5 respectively. The pin numbering is depicted in
Figure 1.
TABLE 3
Pin Configuration of UDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
137
CK0
I
SSTL
–
Clock Signals 2:0
NC
NC
16
CK1
CK2
CK0
NC
I
SSTL
SSTL
SSTL
–
76
I
138
I
Complement Clock Signals 2:0
NC
17
CK1
CK2
CKE0
CKE1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
75
21
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
111
NC
NC
–
Control Signals
157
158
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
NC
–
154
65
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
63
Rev. 1.22, 2007-01
5
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
Address Signals
59
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Address Bus 11:0
52
48
43
A1
41
A2
130
37
A3
A4
32
A5
125
29
A6
A7
122
27
A8
Address Bus 11:0
A9
141
A10
AP
A11
A12
118
115
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: 128 Mbit based module
Address Signal 13
NC
NC
I
–
167
A13
SSTL
Note: 1 Gbit based module
NC
NC
–
Note: Module based on 512 Mbit or smaller dies
Rev. 1.22, 2007-01
6
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
Data Signals
2
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
Rev. 1.22, 2007-01
7
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
151
61
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CB0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
44
Check Bit 0
Note: ECC type module
Note: Non-ECC module
Check Bit 1
NC
NC
I/O
–
45
CB1
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 2
NC
NC
I/O
–
49
CB2
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 3
NC
NC
I/O
–
51
CB3
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 4
NC
NC
I/O
–
134
CB4
SSTL
Note: ECC type module
Note: Non-ECC module
NC
NC
–
Rev. 1.22, 2007-01
8
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
135
CB5
I/O
SSTL
Check Bit 5
Note: ECC type module
Note: Non-ECC module
Check Bit 6
NC
NC
I/O
–
142
144
CB6
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 7
NC
NC
I/O
–
CB7
SSTL
Note: ECC type module
Note: Non-ECC module
Data Strobe Bus 7:0
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
5
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
14
25
36
56
67
78
86
47
Data Strobe 8
Note: ECC type module
Note: Non-ECC module
Data Mask Bus 7:0
NC
NC
–
97
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
107
119
129
149
159
169
177
140
Data Mask 8
Note: ECC type module
Note: Non-ECC module
NC
NC
–
EEPROM
92
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
91
I/O
Serial Bus Data
181
I
I
I
CMOS
CMOS
CMOS
Slave Address Select Bus 2:0
182
183
Power Supplies
1
VREF
AI
–
–
I/O Reference Voltage
EEPROM Power Supply
184
VDDSPD
PWR
Rev. 1.22, 2007-01
9
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
15,
VDDQ
PWR
–
I/O Driver Power Supply
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
7,
VDD
PWRzp
–
Power Supply
38,
46,
70,
85,
108,
120,
148,
168
3,
VSS
GND
–
Ground Plane
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
Rev. 1.22, 2007-01
10
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
Other Pins
82
VDDID
O
OD
–
V
DD Identification
9,
NC
NC
Not connected
10,
71,
90,
101,
102,
103,
113,
163,
173
Rev. 1.22, 2007-01
11
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 4
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 5
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
TABLE 6
Address Format
Density
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period Interval
256 MB
512 MB
512 MB
1 GB
32M ×64
64M ×64
64M ×72
128M ×64
128M ×72
1
1
1
2
2
32M ×16
64M ×8
64M ×8
64M ×8
64M ×8
4
13/2/9
8K
8K
8K
8K
8K
64 ms
64 ms
64 ms
64 ms
64 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
8
13/2/11
13/2/11
13/2/12
13/2/12
8
16
18
1 GB
Rev. 1.22, 2007-01
12
03292006-CXBY-V2JX
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ꢀ
ꢀ
ꢀ
ꢆꢈ
ꢆꢈ
ꢆꢄ
ꢆꢄ
ꢆꢄ
ꢆꢄ
ꢆꢄ
ꢆꢉ
ꢆꢉ
ꢆꢉ
ꢆꢉ
ꢆꢉ
ꢆꢅ
ꢆꢅ
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ꢂꢉ
4
ꢀ
4ꢀ ꢇꢀ3
ꢇꢀ3
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ꢇꢀ3
4ꢀ ꢇꢀ3
ꢇꢀ3
ꢀ ꢇꢀ3
ꢇꢀ3
'ꢀ ꢇꢀ3
ꢇꢀ3
ꢀ ꢇꢀ3
ꢇꢀ3
ꢇꢀ3
ꢇꢀ3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
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ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢄ
ꢄ
ꢄ
ꢉ
ꢉ
ꢉ
ꢉ
ꢉ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢊ
ꢊ
ꢊ
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ꢃ
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ꢁ
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 1
Pin Configuration 184-Pin, UDIMM
9ꢀ )ꢀꢇꢀ 3
9ꢀ66ꢀꢇꢀ 3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁꢆꢀ
ꢁꢂꢀ
ꢁꢄꢀ
ꢁꢅꢀ
ꢁꢃꢀ
ꢆꢆꢀ
ꢆꢂꢀ
ꢆꢄꢀ
ꢆꢅꢀ
ꢆꢃꢀ
ꢋꢆꢀ
ꢋꢂꢀ
ꢋꢄꢀ
ꢋꢅꢀ
ꢋꢃꢀ
ꢂꢆꢀ
ꢂꢂꢀ
ꢂꢄꢀ
ꢂꢅꢀ
ꢂꢃꢀ
ꢈꢆꢀ
ꢈꢂꢀ
ꢈꢄꢀ
ꢈꢅꢀ
ꢈꢃꢀ
ꢄꢆꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
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ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢃꢂ
ꢃꢄ
ꢃꢅ
ꢃꢃ
ꢁꢆ
ꢁꢂ
ꢁꢄ
ꢁꢅ
ꢁꢃ
ꢆꢆ
ꢆꢂ
ꢆꢄ
ꢆꢅ
ꢆꢃ
ꢋꢆ
ꢋꢂ
ꢋꢄ
ꢋꢅ
ꢋꢃ
ꢂꢆ
ꢂꢂ
ꢂꢄ
ꢂꢅ
ꢂꢃ
ꢈꢆ
ꢈꢂ
ꢀꢇꢀ 9ꢀ
5(
66ꢀ
'
'
'
'
4
4
4
4
ꢁ
ꢁ
ꢁ
ꢁ
ꢁꢀꢇꢀ 3
ꢆꢀꢇꢀ 3
ꢋꢀꢇꢀ 3
ꢂꢀꢇꢀ 3
ꢀꢇꢀ 3
ꢊꢀꢇꢀ 3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
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ꢁ
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ꢁ
ꢁ
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ꢁ
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ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢋ
ꢋ
ꢋ
ꢋ
ꢋ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
ꢄ
ꢄ
ꢋꢀ
ꢈꢀ
ꢉꢀ
ꢊꢀ
ꢁꢀ
ꢋꢀ
ꢈꢀ
ꢉꢀ
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ꢁꢀ
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ꢁꢀ
ꢋꢀ
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ꢉꢀ
ꢊꢀ
ꢁꢀ
ꢋꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
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ꢀ
ꢀ
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ꢀ
ꢁꢃ
ꢁꢃ
ꢁꢃ
ꢆꢁ
ꢆꢁ
ꢆꢁ
ꢆꢁ
ꢆꢁ
ꢆꢆ
ꢆꢆ
ꢆꢆ
ꢆꢆ
ꢆꢆ
ꢆꢋ
ꢆꢋ
ꢆꢋ
ꢆꢋ
ꢆꢋ
ꢆꢂ
ꢆꢂ
ꢆꢂ
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ꢆꢂ
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ꢈꢀ ꢇꢀ'
4
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ꢀꢇꢀ '
ꢀꢇꢀ '
ꢀꢇꢀ '
ꢀꢇꢀ 1
ꢀꢇꢀ 1
ꢀꢇꢀ '
ꢀꢇꢀ '
ꢀꢇꢀ '
ꢀꢇꢀ &
ꢀꢇꢀ 1
ꢀꢇꢀ $
ꢀꢇꢀ '
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ꢀꢇꢀ '
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9ꢀ
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46
ꢁꢀꢇꢀ 3
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9ꢀ
ꢁꢀ ꢇꢀ
66ꢀ
1
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9ꢀ66ꢀꢇꢀ 3
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'
4
&
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9ꢀ 4ꢀꢇꢀ 3
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9ꢀ
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9ꢀ '
4ꢆ
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4ꢀ ꢇꢀ3
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9ꢀ
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9ꢀ
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9ꢀ
9ꢀ
9ꢀ '
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
13
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Operating Conditions
This chapter describes the operating conditions.
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note/ Test
Condition
min.
typ. max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
–1
–1
0
—
—
—
—
—
—
1
V
DDQ + 0.5
V
—
—
—
—
—
—
—
—
+3.6
+3.6
+3.6
+70
+150
—
V
VDD
V
VDDQ
TA
V
°C
°C
W
mA
TSTG
PD
–55
—
Power dissipation (per SDRAM component)
Short circuit output current
IOUT
—
50
—
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
Rev. 1.22, 2007-01
14
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note1) / Test Condition
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.3
2.5
2.3
2.5
2.3
0
2.5
2.6
2.5
2.6
2.5
—
2.7
2.7
2.7
2.7
3.6
0
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
VDDSPD
f
—
—
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
4)
5)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
V
V
I/O Termination Voltage
(System)
V
REF – 0.04
—
V
REF + 0.04
8)
8)
8)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
—
—
—
V
V
V
DDQ + 0.3
REF – 0.15
DDQ + 0.3
V
V
V
–0.3
–0.3
Input Voltage Level, CK and VIN(DC)
CK Inputs
8)6)
7)
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
0.71
–2
—
—
—
V
DDQ + 0.6
V
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
µA
Input Leakage Current
II
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
8)9)
Output Leakage Current
IOZ
–5
—
—
—
5
µA
DQs are disabled; 0 V ≤ VOUT
VDDQ
≤
8)
Output High Current, Normal IOH
Strength Driver
—
–16.2
—
mA
mA
V
OUT = 1.95 V 8)
OUT = 0.35 V 8)
Output Low Current, Normal IOL
16.2
V
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
.
.
5)
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
ID is the magnitude of the difference between the input level on CK and the input level on CK.
.
6)
V
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature
and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per component
Rev. 1.22, 2007-01
15
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 9
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
Unit
Note1) / Test
Condition
DDR400B
DDR333
Min.
Min.
Max.
Max.
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
–0.5
–0.6
0.45
0.45
+0.5
+0.6
0.55
0.55
–0.7
–0.6
0.45
0.45
+0.7
+0.6
0.55
0.55
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tDQSCK
tCH
CK low-level width
tCL
Clock Half Period
tHP
Min. (tCL, tCH
)
Min. (tCL, tCH)
Clock cycle time
tCK
5
8
—
—
12
12
—
—
—
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
12
12
—
—
—
7.5
7.5
0.45
0.45
2.2
7.5
0.4
0.4
2.2
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
tDH
tDS
2)3)4)5)
2)3)4)5)6)
Control and Addr. input pulse width (each tIPW
input)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
DQ and DM input pulse width (each input) tDIPW
Data-out high-impedance time from CK/CK tHZ
Data-out low-impedance time from CK/CK tLZ
1.75
–0.7
–0.7
0.75
—
1.75
–0.7
–0.7
0.75
—
ns
ns
ns
tCK
+0.7
+0.7
1.25
+0.7
+0.7
1.25
Write command to 1st DQS latching
tDQSS
transition
DQS-DQ skew (DQS and associated DQ tDQSQ
signals)
—
+0.40
+0.50
—
+0.45
+0.55
ns
TSOPII 2)3)4)5)
Data hold skew factor
tQHS
—
—
ns
ns
tCK
TSOPII 2)3)4)5)
2)3)4)5)
DQ/DQS output hold time
tQH
tHP –tQHS
tHP –tQHS
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQS input low (high) pulse width (write
cycle)
tDQSL,H
0.35
—
—
—
0.35
—
—
—
DQS falling edge to CK setup time (write tDSS
cycle)
0.2
0.2
tCK
tCK
DQS falling edge hold time from CK (write tDSH
0.2
0.2
cycle)
2)3)4)5)
Mode register set command cycle time
Write preamble setup time
Write postamble
tMRD
2
—
2
—
tCK
ns
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
tWPRES
tWPST
tWPRE
tIS
0
—
0
—
0.40
0.25
0.6
0.60
—
0.40
0.25
0.75
0.60
—
tCK
tCK
ns
Write preamble
Address and control input setup time
—
—
Fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
ns
Slow slew rate
3)4)5)6)10)
Rev. 1.22, 2007-01
16
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Parameter
Symbol
–5
–6
Unit
Note1) / Test
Condition
DDR400B
DDR333
Min.
Max.
Min.
Max.
Address and control input hold time
tIH
0.6
—
0.75
—
ns
ns
Fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
Slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Read preamble
tRPRE
tRPST
tRAS
tRC
0.9
0.40
40
1.1
0.9
0.40
42
1.1
tCK
tCK
ns
ns
Read postamble
0.60
70E+3
—
0.60
70E+3
—
Active to Precharge command
Active to Active/Auto-refresh command
period
55
60
2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
tRFC
70
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
tRCD
tRP
15
15
—
—
18
18
—
—
ns
ns
ns
ns
ns
tCK
tRAP
tRCD – tRASmin
Active bank A to Active bank B command tRRD
Write recovery time tWR
10
15
—
—
—
—
12
15
—
—
—
—
Auto precharge write recovery + precharge tDAL
time
2)3)4)5)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
tWTR
tXSNR
tXSRD
tREFI
2
—
—
—
7.8
1
—
—
—
7.8
tCK
ns
2)3)4)5)
75
200
—
75
200
—
2)3)4)5)
tCK
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Rev. 1.22, 2007-01
17
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
3.2
Current Conditions and Specification
This chapter describes the Conditions and Specification.
TABLE 10
DD Specification for HYS[64/72]D[32/64/128]3xxHU–5–B
I
Product Type
Unit Note 1)2)
Organization
256 MB
×64
512 MB
×64
512 MB
×64
1 GB
×64
1 GB
×72
1 Rank
–5
1 Rank
–5
1 Rank
–5
2 Ranks
–5
2 Ranks
–5
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
3)
IDD0
400
460
10
480
560
20
640
720
10
800
880
30
720
810
20
900
990
40
950
1030
30
1180
1260
64
1070
1160
31
1330
1420
70
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
120
80
140
100
60
240
150
100
310
680
720
1640
22
290
210
130
380
800
840
1960
42
270
170
110
350
770
810
1850
30
320
230
140
420
900
950
2210
50
480
300
190
620
990
1030
1950
45
580
540
650
5)
420
340
470
5)
50
260
220
290
5)
170
480
500
820
11
200
580
600
980
20.8
1360
750
700
850
3)4)
3)
1180
1220
2340
80
1120
1160
2200
50
1320
1370
2630
90
3)
3)
IDD6
3)4)
IDD7
1140
2080
2480
2340
2790
2390
2860
2690
3210
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx [component] + n × IDD3N [component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDDx values are calculated from the component IDDx data sheet values as: (m + n) × IDDx [component]
Rev. 1.22, 2007-01
18
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 11
DD Specification for HYS[64/72]D[64/128]3xxHU–6–B
I
Product Type
Unit
Note 1)2)
Organization
512 MB
×64
512 MB
×72
1 GB
×64
1 GB
×72
1 Rank
–6
1 Rank
–6
2 Ranks
–6
2 Ranks
–6
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
3)
IDD0
600
680
10
720
800
30
680
770
10
810
900
40
880
960
30
1050
1130
64
990
1180
1270
70
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
1080
290
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
200
140
90
240
190
120
330
720
760
1760
42
230
150
100
320
690
730
1670
24
270
220
140
370
810
860
1980
47
400
270
180
560
900
930
1760
43
480
450
540
5)
380
310
430
5)
240
200
270
5)
280
620
650
1480
22
660
630
740
3)4)
3)
1050
1090
2090
80
1010
1040
1980
49
1180
1220
2350
94
3)
3)
IDD6
3)4)
IDD7
1870
2230
2110
2510
2150
2560
2420
2880
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx [component] + n × IDD3N [component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx [component]
Rev. 1.22, 2007-01
19
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
Table 12 “HYS[64/72]D[64/128]3x0GU-5-B” on Page 20
Table 13 “HYS[64/72]D[64/128]3x0GU-6-B” on Page 24
Table 14 “HYS[64/72]D[32/64/128]3xxHU-5-B” on Page 28
Table 15 “HYS[64/72]D[64/128]3x0HU-6-B” on Page 32
TABLE 12
HYS[64/72]D[64/128]3x0GU-5-B
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0B
01
40
00
04
50
50
00
80
08
07
0D
0B
01
48
00
04
50
50
02
80
08
07
0D
0B
02
40
00
04
50
50
00
80
08
07
0D
0B
02
48
00
04
50
50
02
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Rev. 1.22, 2007-01
20
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Refresh Rate
82
08
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
82
08
08
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
82
08
00
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
82
08
08
01
0E
04
1C
01
02
20
C1
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK@ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
Module Density per Rank
tAS, CS [ns]
tAH, CH [ns]
DS [ns]
DH [ns]
t
t
t
t
36 - 40 Not used
41 RCmin [ns]
t
Rev. 1.22, 2007-01
21
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
42
43
44
45
46
47
t
t
t
t
RFCmin [ns]
CKmax [ns]
41
28
28
50
00
00
00
00
3E
7F
7F
7F
7F
7F
51
00
00
xx
41
28
28
50
00
00
00
00
50
7F
7F
7F
7F
7F
51
00
00
xx
41
28
28
50
00
00
00
00
3F
7F
7F
7F
7F
7F
51
00
00
xx
41
28
28
50
00
00
00
00
51
7F
7F
7F
7F
7F
51
00
00
xx
DQSQmax [ns]
QHSmax [ns]
Not used
DIMM PCB Height
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
36
34
44
36
34
33
30
30
37
32
44
36
34
33
30
30
36
34
44
31
32
38
33
32
37
32
44
31
32
38
33
32
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Rev. 1.22, 2007-01
22
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 9
47
55
35
42
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
47
55
35
42
20
20
20
20
20
20
1x
xx
xx
xx
xx
00
30
47
55
35
42
20
20
20
20
20
1x
xx
xx
xx
xx
00
30
47
55
35
42
20
20
20
20
20
1x
xx
xx
xx
xx
00
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.22, 2007-01
23
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 13
HYS[64/72]D[64/128]3x0GU-6-B
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0B
01
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 1.22, 2007-01
24
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
t
t
t
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax-1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
42
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
54
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
43
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
55
7F
7F
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
Module Density per Rank
tAS, CS [ns]
tAH, CH [ns]
DS [ns]
DH [ns]
t
t
t
t
36 - 40 Not used
41
42
43
44
45
46
47
t
t
t
t
t
RCmin [ns]
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
Not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Rev. 1.22, 2007-01
25
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
36
34
44
36
34
33
30
30
47
55
36
42
20
20
20
20
20
20
1x
37
32
44
36
34
33
30
30
47
55
36
42
20
20
20
20
20
20
1x
36
34
44
31
32
38
33
32
30
47
55
36
42
20
20
20
20
20
1x
37
32
44
31
32
38
33
32
30
47
55
36
42
20
20
20
20
20
1x
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Rev. 1.22, 2007-01
26
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
92
93
94
Test Program Revision Code
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.22, 2007-01
27
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 14
HYS[64/72]D[32/64/128]3xxHU-5-B
Product Type
Organization
256MB
512MB
512MB
1 GByte 1 GByte
×64 ×72
2 Ranks 2 Ranks
×64
×64
×72
1 Rank
1 Rank
1 Rank
(×16)
(×8)
(×8)
(×8) (×8)
Label Code
PC3200U PC3200U PC3200U PC3200U PC3200U
–30331 –30330 –30330 –30330 –30330
JEDEC SPD Revision
Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
40
00
04
50
50
00
82
10
00
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
01
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
01
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
02
40
00
04
50
50
00
82
08
00
01
0E
04
1C
01
02
20
C1
80
08
07
0D
0B
02
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
20
C1
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 1.22, 2007-01
28
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
256MB
512MB
512MB
1 GByte 1 GByte
×64 ×72
2 Ranks 2 Ranks
×64
×64
×72
1 Rank
1 Rank
1 Rank
(×16)
(×8)
(×8)
(×8) (×8)
Label Code
PC3200U PC3200U PC3200U PC3200U PC3200U
–30331 –30330 –30330 –30330 –30330
JEDEC SPD Revision
Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
23
24
25
26
27
28
29
30
31
32
33
34
35
t
t
t
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
60
50
75
50
3C
28
3C
28
40
60
60
40
40
00
37
41
28
28
50
00
01
00
10
16
7F
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
41
28
28
50
00
00
00
00
3E
7F
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
41
28
28
50
00
00
00
00
50
7F
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
41
28
28
50
00
00
00
00
3F
7F
60
50
75
50
3C
28
3C
28
80
60
60
40
40
00
37
41
28
28
50
00
00
00
00
51
7F
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
Module Density per Rank
tAS, CS [ns]
tAH, CH [ns]
DS [ns]
DH [ns]
t
t
t
t
36 - 40 Not used
41
42
43
44
45
46
47
t
t
t
t
t
RCmin [ns]
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
Not used
DIMM PCB Height
48 - 61 Not used
62
63
64
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Rev. 1.22, 2007-01
29
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
256MB
512MB
512MB
1 GByte 1 GByte
×64 ×72
2 Ranks 2 Ranks
×64
×64
×72
1 Rank
1 Rank
1 Rank
(×16)
(×8)
(×8)
(×8) (×8)
Label Code
PC3200U PC3200U PC3200U PC3200U PC3200U
–30331 –30330 –30330 –30330 –30330
JEDEC SPD Revision
Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
36
34
44
33
32
33
30
31
48
55
35
42
20
20
20
20
20
36
34
44
36
34
33
30
30
48
55
35
42
20
20
20
20
20
37
32
44
36
34
33
30
30
48
55
35
42
20
20
20
20
20
36
34
44
31
32
38
33
32
30
48
55
35
42
20
20
20
20
37
32
44
31
32
38
33
32
30
48
55
35
42
20
20
20
20
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Rev. 1.22, 2007-01
30
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
256MB
512MB
512MB
1 GByte 1 GByte
×64 ×72
2 Ranks 2 Ranks
×64
×64
×72
1 Rank
1 Rank
1 Rank
(×16)
(×8)
(×8)
(×8) (×8)
Label Code
PC3200U PC3200U PC3200U PC3200U PC3200U
–30331 –30330 –30330 –30330 –30330
JEDEC SPD Revision
Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
90
91
92
93
94
Part Number, Char 18
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
20
1x
xx
xx
xx
xx
00
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.22, 2007-01
31
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 15
HYS[64/72]D[64/128]3x0HU-6-B
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0B
01
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
t
t
CK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 1.22, 2007-01
32
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
t
t
t
t
t
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
42
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
54
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
43
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
00
00
00
55
7F
7F
RRDmin [ns]
RCDmin [ns]
RASmin [ns]
Module Density per Rank
tAS, CS [ns]
tAH, CH [ns]
DS [ns]
DH [ns]
t
t
t
t
36 - 40 Not used
41
42
43
44
45
46
47
t
t
t
t
t
RCmin [ns]
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
Not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Rev. 1.22, 2007-01
33
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
36
34
44
36
34
33
30
30
48
55
36
42
20
20
20
20
20
20
1x
37
32
44
36
34
33
30
30
48
55
36
42
20
20
20
20
20
20
1x
36
34
44
31
32
38
33
32
30
48
55
36
42
20
20
20
20
20
1x
37
32
44
31
32
38
33
32
30
48
55
36
42
20
20
20
20
20
1x
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Rev. 1.22, 2007-01
34
03292006-CXBY-V2JX
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Rev. 0.0
HEX
Byte#
Description
92
93
94
Test Program Revision Code
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 1.22, 2007-01
35
03292006-CXBY-V2JX
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Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 2
Raw Card C DDR UDIMM HYS64D32301HU–5–B (1 Rank Module)
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Rev. 1.22, 2007-01
03292006-CXBY-V2JX
36
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 3
Raw Card A DDR UDIMM HYS64D64300HU–[5/6/7]–B (1 Rank Module)
133.30
±.10
A B C
128.90
2.7 MAX.
A
1
2.36
92
6.62
2.170
B
C
±±.1
ø±.1
A B C
64.77
±.4
6.30
±±.1
1.27
49.03
90 x 1.27 = 12±.60
±±.1
1.8
±.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±±.±0
1
±.1
A B C
Burr max. ±.4 allowed
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
37
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 4
Raw Card A DDR UDIMM HYS72D64300HU–[5/6/7F]–B (1 Rank Module)
133.30
±.10
A B C
128.90
2.7 MAX.
1)
A
1
2.36
92
6.62
2.170
B
C
±±.1
ø±.1
A B C
64.77
±.4
6.30
±±.1
1.27
49.03
90 x 1.27 = 12±.60
±±.1
1.8
±.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±±.±0
1
±.1
A B C
1) On ECC modules only
Burr max. ±.4 allowed
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
38
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 5
Raw Card B DDR UDIMM HYS64D128320HU–[5/6/7]–B (2 Ranks Module)
133.30
±.10
A B C
128.90
4 MAX.
A
1
2.36
92
6.62
2.170
B
C
±±.1
ø±.1
A B C
64.77
±.4
6.30
±±.1
1.27
49.03
90 x 1.27 = 12±.60
±±.1
1.8
±.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±±.±0
1
±.1
A B C
Burr max. ±.4 allowed
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
39
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 6
Raw Card B DDR UDIMM HYS72D128320HU–[5/6/7]–B (2 Rank Module)
133.30
±.10
A B C
128.90
4 MAX.
1)
A
1
2.36
92
6.62
2.170
B
C
±±.1
ø±.1
A B C
64.77
±.4
6.30
±±.1
1.27
49.03
90 x 1.27 = 12±.60
±±.1
1.8
±.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±±.±0
1
±.1
A B C
1) On ECC modules only
Burr max. ±.4 allowed
Rev. 1.22, 2007-01
03292006-CXBY-V2JX
40
Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
5
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Rev. 1.22, 2007-01
41
03292006-CXBY-V2JX
Internet Data Sheet
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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