HYS72T1G242EP-3-C_技术文档

July 2007

HYS72T1G242EP–[25F/2.5]–C

HYS72T1G242EP–[3/3S/3.7]–C

240-Pin Dual Die Registered DDR2 SDRAM Modules

RDIMM SDRAM

RoHS Compliant

Internet Data Sheet

Rev. 1.0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

HYS72T1G242EP–[25F/2.5]–C, HYS72T1G242EP–[3/3S/3.7]–C

Revision History: 2007-07, Rev. 1.0

Page

Subjects (major changes since last revision)

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Adapted to internet version

Final document

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07242007-LR08-OZC0

2

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

1

Overview

This chapter gives an overview of the 1.8 V 240-Pin Dual Die Registered DDR2 SDRAM Modules with parity bit product family

and describes its main characteristics.

1.1

Features

•

240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2

SDRAM memory modules.

1024M ×72 module organization and 512M ×4 chip

organization

Registered DIMM Parity bit for address and control bus

8 GByte modules built with stacked 2 Gbit (1Gbit Dual

Dies) DDR2 SDRAMs in P-TFBGA-63 chipsize packages.

Standard Double-Data-Rate-Two Synchronous DRAMs

(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power

supply

•

Programmable self refresh rate via EMRS2 setting

Programmable partial array refresh via EMRS2 settings

DCC enabling via EMRS2 setting

All inputs and outputs SSTL_18 compatible

Off-Chip Driver Impedance Adjustment (OCD) and On-Die

Termination (ODT)

•

Serial Presence Detect with E²PROM

RDIMM Dimensions (nominal): 30 mm high, 133.35 mm

wide

•

Based on standard reference card layouts Raw Card “Z”

All speed grades faster than DDR2–400 comply with

DDR2–400 timing specifications.

•

Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4

& 8)

Auto Refresh (CBR) and Self Refresh

•

RoHS compliant products¹⁾

TABLE 1

Performance Table

Product Type Speed Code

DRAM Speed Grade

Speed Grade

–25F

–2.5

–3

–3S

–3.7

Unit

DDR2–800D DDR2–800E DDR2–667C DDR2–667D DDR2–533C

PC2–6400

6-6-6

PC2–5300

4-4-4

PC2–5300

5-5-5

PC2–4200

4-4-4

CAS-RCD-RP latencies

5-5-5

t_CK

Max. Clock

Frequency

@CL6 f_CK6

–

400

333

266

200

15

–

MHz

ns

@CL5 f_CK5400

333

200

12

333

266

200

15

266

200

15

@CL4 f_CK4266

@CL3 f_CK3200

Min. RAS-CAS-Delay

t_RCD12.5

Min. Row Precharge Time t_RP

12.5

57.5

15

12

15

ns

Min. Row Active Time

Min. Row Cycle Time

t_RAS45

45

ns

t_RC

60

57

60

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.0, 2007-07

3

07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

1.2

Description

The Qimonda HYS72T1G242EP–[25F/2.5/3//3S/3.7]–C module

family are Registered DIMM (with parity) modules with 30 mm

height based on DDR2 technology.

distribution. This reduces capacitive loading to the system

bus, but adds one cycle to the SDRAM timing. Decoupling

capacitors are mounted on the PCB board. The DIMMs

feature serial presence detect based on a serial E2PROM

device using the 2-pin I2C protocol. The first 128 bytes are

programmed with configuration data and the second

128 bytes are available to the customer.

DIMMs are available as ECC modules in 1024M × 72 (8 GB)

organization and density, intended for mounting into 240-Pin

connector sockets.

The memory array is designed with stacked 2 Gbit (1Gbit

Dual Dies) Double-Data-Rate-Two (DDR2) Synchronous

DRAMs. All control and address signals are re-driven on the

DIMM using register devices and a PLL for the clock

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM

Technology

PC2–6400

HYS72T1G242EP-2.5-C

HYS72T1G242EP-25F-C

PC2–5300

8GB 4Rx4 PC2-6400P-666-12-ZZ

8GB 4Rx4 PC2-6400P-555-12-ZZ

4 Rank, ECC

1Gbit (× 4)

HYS72T1G242EP-3-C

HYS72T1G242EP-3S-C

PC2–4200

8GB 4Rx4 PC2-5300P-444-12-ZZ

8GB 4Rx4 PC2-5300P-555-12-ZZ

4 Rank, ECC

1Gbit (× 4)

HYS72T1G242EP-3.7-C

8GB 4Rx4 PC2-4200P-444-12-ZZ

4 Rank, ECC

1Gbit (× 4)

1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T1G242EP-3.7-C, indicating Rev.

“C” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data

sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–ZZ”, where 4200P

means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe

(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2

and produced on the Raw Card “F”

TABLE 3

Address Format

DIMM

Density

Module

Organization

Memory

Ranks

ECC/

Non-ECC

# of SDRAMs # of row/bank/column

bits

Raw

Card

8 GByte

1024M ×72

4

ECC

36DDP¹⁾

14/3/11

Z

1) DDP Dual Die Package

TABLE 4

Components on Modules

DRAM Organization

2 × 512M × 4

Product Type¹⁾

DRAM Components

DRAM Density

HYS72T1G242EP

HYB18T2G402CF

1 Gbit

1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.

Rev. 1.0, 2007-07

4

07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

2

Pin Configuration and Block Diagrams

This chapter contains the pin configuration and block diagrams.

2.1

Pin Configuration

The pin configuration of the Registered DDR2 SDRAM DIMM

is listed by function in Table 5 (240 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 6

and Table 7 respectively. The pin numbering is depicted in

Figure 1.

TABLE 5

Pin Configuration of RDIMM

Pin No.

Name

Buffer

Function

Type Type

Clock Signals

185

186

CK0

I

SSTL

Clock Signal CK0, Complementary Clock Signal CK0

The system clock inputs. All address and command lines are sampled

on the cross point of the rising edge of CK and the falling edge of CK.

A Delay Locked Loop (DLL) circuit is driven from the clock inputs and

output timing for read operations is synchronized to the input clock.

52

CKE0

CKE1

I

SSTL

Clock Enables 1:0

Activates the DDR2 SDRAM CK signal when HIGH and deactivates

the CK signal when LOW. By deactivating the clocks, CKE0 initiates

the Power Down Mode or the Self Refresh Mode.

171

Note: 2-Ranks module

Not Connected

NC

—

Note: 1-Rank module

Control Signals

193

76

S0

S1

I

SSTL

Chip Select

Enables the associated DDR2 SDRAM command decoder when LOW

and disables the command decoder when HIGH. When the command

decoder is disabled, new commands are ignored but previous

operations continue.

Rank 0 is selected by S0

Rank 1 is selected by S1

The input signals also disable all outputs (except CKE and ODT) of the

register(s) on the DIMM when both inputs are high. When S is HIGH,

all register outputs (except CK, ODT and Chip select) remain in the

previous state.

Note: 2-Ranks module

Not Connected

NC

—

Note: 1-Rank module

Rev. 1.0, 2007-07

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07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

220

S2

I

SSTL

—

Rank 2 is selected by S2

NC

Not Connected

Note: 1-Rank, 2-Ranks module

221

S3

I

SSTL

—

Rank 3 is selected by S3

Not Connected

NC

Note: 1-Rank, 2-Ranks module

192

74

RAS

CAS

WE

I

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

When sampled at the cross point of the rising edge of CK, and falling

edge of CK, RAS, CAS and WE define the operation to be executed by

the SDRAM.

73

18

RESET

I

CMOS

Register Reset

The RESET pin is connected to the RST pin on the register and to the

OE pin on the PLL. When LOW, all register outputs will be driven LOW

and the PLL clocks to the DRAMs and the register(s) will be set to low-

level. The PLL will remain synchronized with the input clock.

Address Signals

71

BA0

BA1

BA2

I

SSTL

Bank Address Bus 1:0

Selects internal SDRAM memory bank

190

54

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

NC

I

SSTL

Not Connected

Less than 1Gb DDR2 SDRAMS

188

183

63

A0

I

SSTL

—

Address Bus 12:0, Address Signal 10/AutoPrecharge

During a Bank Activate command cycle, defines the row address when

sampled at the crosspoint of the rising edge of CK and falling edge of

CK. During a Read or Write command cycle, defines the column

address when sampled at the cross point of the rising edge of CK and

falling edge of CK. In addition to the column address, AP is used to

invoke autoprecharge operation at the end of the burst read or write

cycle. If AP is HIGH, autoprecharge is selected and BA[2:0] defines the

bank to be precharged. If AP is LOW, autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with

BA[2:0] to control which bank(s) to precharge. If AP is HIGH, all banks

will be precharged regardless of the state of BA[2:0] inputs. If AP is

LOW, then BA[2:0] are used to define which bank to precharge.

A1

I

A2

I

182

61

A3

I

A4

I

60

A5

I

180

58

A6

I

A7

I

179

177

70

A8

I

A9

I

A10

AP

A11

A12

A13

NC

I

57

I

176

196

I

Address Signal 13

NC

Not Connected

Note: Non CA parity modules based on 256 Mbit component

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Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Pin No.

Name

A14

NC

Type Type

Buffer

Function

174

I

SSTL

—

Address Signal 14

Note: CA Parity module

Not Connected

NC

I

Note: Non CA parity module. Less than 1 GBit per DRAM die.

Address Signal 14

173

A15

NC

SSTL

—

Note: CA Parity module

NC

Not Connected

Note: Non CA parity module. Less than 1 GBit per DRAM die.

Data Signals

3

DQ0

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

4

DQ1

9

DQ2

10

DQ3

122

123

128

129

12

DQ4

DQ5

DQ6

DQ7

DQ8

13

DQ9

21

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

Rev. 1.0, 2007-07

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Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

159

80

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

81

86

87

199

200

205

206

89

90

95

96

208

209

214

215

98

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bits

42

CB0

CB1

CB2

CB3

I/O

SSTL

Check Bits 7:0

Check Bit Input / Output pins

43

Note: NC on Non-ECC module

48

49

Rev. 1.0, 2007-07

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07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

161

CB4

CB5

CB6

CB7

I/O

SSTL

Check Bits 7:0

Check Bit Input / Output pins

162

Note: NC on Non-ECC module

167

168

Data Strobe Bus

7

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DQS9

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

I/O

SSTL

Data Strobes 17:0

The data strobes, associated with one data byte, sourced with data

transfers. In Write mode, the data strobe is sourced by the controller

and is centered in the data window. In Read mode the data strobe is

sourced by the DDR2 SDRAM and is sent at the leading edge of the

data window. DQS signals are complements, and timing is relative to

the crosspoint of respective DQS and DQS. If the module is to be

operated in single ended strobe mode, all DQS signals must be tied on

the system board to V_SSthrough a 20 Ω to 10 kΩ resistor and DDR2

SDRAM mode registers programmed appropriately.

6

16

15

28

27

37

36

Note: See block diagram for corresponding DQ signals

84

83

93

92

105

104

114

113

46

45

125

126

134

135

146

147

155

156

202

203

211

212

223

224

232

Rev. 1.0, 2007-07

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Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

233

DQS16

DQS17

I/O

SSTL

Data Strobes 17:0

164

165

Data Mask

125

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

SSTL

Data Masks 8:0

The data write masks, associated with one data byte. In Write mode,

DM operates as a byte mask by allowing input data to be written if it is

LOW but blocks the write operation if it is HIGH. In Read mode, DM

lines have no effect.

134

146

155

202

Note: ×8 based module

211

223

232

164

EEPROM

120

SCL

SDA

I

CMOS

OD

Serial Bus Clock

This signal is used to clock data into and out of the SPD EEPROM.

119

I/O

Serial Bus Data

This is a bidirectional pin used to transfer data into or out of the SPD

EEPROM. A resistor must be connected from SDA to V_DDSPDon the

motherboard to act as a pull-up.

239

240

101

Parity

55

SA0

SA1

SA2

I

CMOS

Serial Address Select Bus 2:0

These signals are tied at the system planar to either V_SSor V_DDSPDto

configure the serial SPD EEPROM address range

ERR_OUT

PAR_IN

O

I

CMOS

Parity bits

Note: Only for modules with parity bit for address and control bus. Not

connected on non-parity registered modules.

68

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

Reference voltage for the SSTL-18 inputs.

238

V_DDSPD

PWR

EEPROM Power Supply

Serial EEPROM positive power supply, wired to a separated power pin

at the connector which supports from 1.7 Volt to 3.6 Volt.

51, 56, 62, 72, 75, V_DDQ

78, 170, 175, 181,

191, 194

PWR

—

I/O Driver Power Supply

Power and ground for the DDR SDRAM

53, 59, 64, 67, 69, V_DD

172, 178, 184, 187,

189, 197

Power Supply

Power and ground for the DDR SDRAM

Rev. 1.0, 2007-07

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07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Pin No.

Name

Buffer

Function

Type Type

2, 5, 8, 11, 14, 17, V_SS

20, 23, 26, 29, 32,

35, 38, 41, 44, 47,

50, 65, 66, 79, 82,

85, 88, 91, 94, 97,

100, 103, 106, 109,

112, 115, 118, 121,

124, 127, 130, 133,

136, 139, 142, 145,

148, 151, 154, 157,

160, 163, 166, 169,

198, 201, 204, 207,

210, 213, 216, 219,

222, 225, 228, 231,

234, 237

GND —

Ground Plane

Power and ground for the DDR SDRAM

Other Pins

19, 102, 137, 138, NC

NC

—

Not connected

Pins not connected on Qimonda RDIMM’s

195

77

ODT0

I

SSTL

On-Die Termination Control 1:0

Asserts on-die termination for DQ, DM, DQS, and DQS signals if

enabled via the DDR2 SDRAM mode register.

ODT1

Note: 2-Ranks module

NC

—

Note: 1-Rank modules

TABLE 6

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

CMOS

OD

Serial Stub Terminated Logic (SSTL_18)

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate,

and allows multiple devices to share as a wire-OR.

Rev. 1.0, 2007-07

11

07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

TABLE 7

Abbreviations for Pin Type

Abbreviation

Description

I

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

O

I/O

AI

PWR

GND

NU

NC

Ground

Not Usable

Not Connected

Rev. 1.0, 2007-07

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07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

FIGURE 1

Pin Configuration for RDIMM (240 pins)

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6&/

Rev. 1.0, 2007-07

07242007-LR08-OZC0

13

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

3

Electrical Characteristics

This chapter lists the electrical characteristics.

3.1

Absolute Maximum Ratings

Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.

TABLE 8

Absolute Maximum Ratings

Symbol

Parameter

Rating

Min.

Unit

Notes

Max.

1)

V_DD

Voltage on V_DDpin relative to V_SS

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

–1.0

–0.5

–55

+2.3

+100

V

1)2)

1)

V_DDQ

V_DDL

V

V_IN, V_OUT

T_STG

V

1)2)

°C

1) When V_DDand V_DDQand V_DDLare less than 500 mV; V_REFmay be equal to or less than 300 mV.

2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.

Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability.

TABLE 9

DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Unit

Notes

Min.

Max.

1)2)3)4)

T_OPER

Operating Temperature

0

95

°C

1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.

2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case

temperature must be maintained between 0 - 95 °C under all other specification parameters.

3) Above 85 °C the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%

Rev. 1.0, 2007-07

14

07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

3.2

DC Operating Conditions

This chapter contains the DC operating conditions tables.

TABLE 10

Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Max.

Operating temperature (ambient)

DRAM Case Temperature

T_OPR

T_CASE

T_STG

PBar

H_OPR

H_STG

0

+65

+95

+100

+105

90

°C

kPa

%

1)2)3)4)

5)

0

Storage Temperature

– 50

+69

10

5

Barometric Pressure (operating & storage)

Operating Humidity (relative)

Storage Humidity (without condensation)

95

%

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported

3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4) When operating this product in the 85 °C to 95 °C T_CASEtemperature range, the High Temperature Self Refresh has to be enabled by

setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of I_DD6by approximately 50%.

5) Up to 3000 m.

TABLE 11

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Notes

Typ.

Max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

1.9

V

1)

2)

V_DDQ

V_REF

1.7

1.8

1.9

V

0.49 × V_DDQ

0.5 × V_DDQ

0.51 × V_DDQ

V

V_DDSPD

V_IH(DC)

V_{IL (DC}

I_L

1.7

—

3.6

V

DC Input Logic High

V

_REF+ 0.125

V

5

_DDQ+ 0.3

V

DC Input Logic Low

)

– 0.30

– 5

_REF– 0.125

V

3)

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

.

Rev. 1.0, 2007-07

15

07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

3.3

Timing Characteristics

This chapter describes the timing characteristics.

3.3.1

Speed Grade Definitions

All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(t_CK= 5ns with t_RAS= 40ns).

Speed Grade Definitions:Table 12 for DDR2–800E , Table 13 for DDR2–667D, Table 14 for DDR2–533C

TABLE 12

Speed Grade Definition Speed Bins for DDR2–800

Speed Grade

DDR2–800D

DDR2–800E

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–2.5F

–2.5

5–5–5

6–6–6

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

@ CL = 6

t_CK

5

8

5

8

ns

t_CK

3.75

2.5

8

3.75

3

8

t_CK

8

t_CK

2.5

45

8

2.5

45

60

15

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

70000

—

57.5

12.5

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

TABLE 13

Speed Grade Definition Speed Bins for DDR2–667

Speed Grade

DDR2–667C

DDR2–667D

Unit

Notes

QAG Sort Name

CAS-RCD-RP latencies

–3

–3S

4–4–4

5–5–5

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

5

3

8

5

8

ns

3.75

3

Rev. 1.0, 2007-07

16

07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Speed Grade

DDR2–667C

–3

DDR2–667D

–3S

Unit

Notes

QAG Sort Name

CAS-RCD-RP latencies

Parameter

4–4–4

5–5–5

t_CK

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)5)

1)2)3)4)

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

45

57

12

70000

—

45

60

15

70000

—

ns

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

TABLE 14

Speed Grade Definition Speed Bins for DDR2–533C

Speed Grade

DDR2–533C

Unit

Note

QAG Sort Name

CAS-RCD-RP latencies

–3.7

4–4–4

t_CK

Parameter

Symbol

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

5

8

ns

t_CK

3.75

45

8

t_CK

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0)

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

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Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

3.3.2

Component AC Timing Parameters

Timing Parameters:Table 15 for DDR2–800E, Table 16 for DDR2–667D, Table 17 for DDR2–533C

TABLE 15

DRAM Component Timing Parameter by Speed Grade - DDR2–800

Parameter

Symbol

DDR2–800

Unit

Notes^1)2)3)4)5)6)

7)8)

Min.

Max.

9)

DQ output access time from CK / CK

CAS to CAS command delay

Average clock high pulse width

Average clock period

t_AC

–400

2

+400

—

ps

t_CCD

nCK

t_CK.AVG

ps

10)11)

12)

t_CH.AVG

t_CK.AVG

0.48

2500

3

0.52

8000

—

CKE minimum pulse width ( high and low pulse t_CKE

nCK

width)

10)11)

13)14)

Average clock low pulse width

t_CL.AVG

0.48

0.52

—

t_CK.AVG

nCK

ns

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t_IS+ t_{CK .AVG}

t_IH

+

––

19)20)15)

9)

DQ and DM input hold time

t_DH.BASE

t_DIPW

t_DQSCK

t_DQSH

125

––

ps

DQ and DM input pulse width for each input

DQS output access time from CK / CK

DQS input high pulse width

0.35

–350

0.35

—

t_CK.AVG

ps

+350

—

t_CK.AVG

ps

DQS input low pulse width

t_DQSL

—

16)

17)

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

200

+ 0.25

DQS latching rising transition to associated clock t_DQSS

– 0.25

t_CK.AVG

edges

18)19)20)

17)

DQ and DM input setup time

t_DS.BASE

t_DSH

t_DSS

50

0.2

35

45

––

—

__

ps

DQS falling edge hold time from CK

DQS falling edge to CK setup time

t_CK.AVG

ns

17)

35)

Four Activate Window for 1KB page size products t_FAW

Four Activate Window for 2KB page size products t_FAW

35)

ns

21)

CK half pulse width

t_HP

Min(t_CH.ABS

,

ps

t_CL.ABS

)

9)22)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

—

ps

23)25)

t_IH.BASE

250

0.6

ps

Control & address input pulse width for each input t_IPW

—

t_CK.AVG

ps

24)25)

9)22)

35)

Address and control input setup time

DQ low impedance time from CK/CK

DQS/DQS low-impedance time from CK / CK

MRS command to ODT update delay

Mode register set command cycle time

OCD drive mode output delay

t_IS.BASE

175

—

t_LZ.DQ

t_LZ.DQS

t_MOD

t_MRD

t_OIT

2 x t_AC.MIN

t_AC.MAX

12

ps

t_AC.MIN

ps

0

2

0

ns

—

nCK

ns

35)

26)

12

DQ/DQS output hold time from DQS

t_QH

t

_HP– t_QHS

—

ps

Rev. 1.0, 2007-07

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07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Parameter

Symbol

DDR2–800

Min.

Unit

Notes^1)2)3)4)5)6)

7)8)

Max.

27)

DQ hold skew factor

t_QHS

t_REFI

—

300

7.8

3.9

—

ps

µs

ns

28)29)

29)30)

31)

Average periodic refresh Interval

—

Auto-Refresh to Active/Auto-Refresh command t_RFC

127.5

period

Precharge-All (8 banks) command period

Read preamble

t_RP

t

_RP+ 1 × t_CK

—

ns

32)33)

32)34)

35)

t_RPRE

t_RPST

t_RRD

0.9

0.4

7.5

1.1

0.6

—

t_CK.AVG

ns

Read postamble

Active to active command period for 1KB page

size products

35)

Active to active command period for 2KB page

size products

t_RRD

10

—

ns

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

0.35

0.4

15

—

0.6

—

ns

t_WPRE

t_WPST

t_WR

t_CK.AVG

ns

Write postamble

35)

Write recovery time

35)36)

Internal write to read command delay

Exit power down to read command

t_WTR

t_XARD

7.5

2

ns

nCK

Exit active power-down mode to read command t_XARDS

8 – AL

(slow exit, lower power)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

t_XP

2

—

nCK

35)

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

nCK

Write command to DQS associated clock edges WL

RL – 1

1) For details and notes see the relevant Qimonda component data sheet

2)

V_DDQ= 1.8 V ± 0.1V; V_DD= 1.8 V ± 0.1 V.

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode.

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

.

8) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVGof the input clock

under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and

DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command

may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG+ t_{ERR.2PER(Min)}

.

9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per)of the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN}= – 272

ps and t_{ERR(6- 10PER).MAX}= + 293 ps, then t_{DQSCK.MIN(DERATED)}= t_DQSCK.MIN– t_{ERR(6-10PER).MAX}= – 400 ps – 293 ps = – 693 ps and

t_{DQSCK.MAX(DERATED)}= t_DQSCK.MAX– t_{ERR(6-10PER).MIN}= 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQfor DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}

= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)}= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)

10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to

DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.

Rev. 1.0, 2007-07

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Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and

the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).

12) t_CKE.MINof 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the

entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during

the time period of t_IS+ 2 x t_CK+ t_IH.

13) DAL = WR + RU{t_RP(ns) / t_CK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For t_RP, if the result

of the division is not already an integer, round up to the next highest integer. t_CKrefers to the application clock period. Example: For

DDR2–533 at t_CK= 3.75 ns with t_WRprogrammed to 4 clocks. t_DAL= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.

14) t_DAL.nCK= WR [nCK] + t_nRP.nCK= WR + RU{t_RP[ps] / t_CK.AVG[ps] }, where WR is the value programmed in the EMR.

15) Input waveform timing t_DHwith differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to

the input signal crossing at the V_IH.DClevel for a falling signal and from the differential data strobe crosspoint to the input signal crossing

at the V_IL.DClevel for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAXand

V_IH.DC.MIN. See Figure 3.

16) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output

slew rate mismatch between DQS / DQS and associated DQ in any given cycle.

17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC, etc.), as these are relative to the clock signal

crossing. That is, these parameters should be met whether clock jitter is present or not.

18) Input waveform timing t_DSwith differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AClevel

to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AClevel to the differential data strobe

crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAXand V_ih(DC)MIN. See

Figure 3.

19) If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.

20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal

((L/U/R)DQS / DQS) crossing.

21) t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not an input specification parameter.

It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The value to be used for t_QHcalculation is determined by the

following equation; t_HP= MIN (t_CH.ABS, t_CL.ABS), where, t_CH.ABSis the minimum of the actual instantaneous clock high time; t_CL.ABSis the

minimum of the actual instantaneous clock low time.

22) t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level

which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .

23) Input waveform timing is referenced from the input signal crossing at the V_IL.DClevel for a rising signal and V_IH.DCfor a falling signal applied

to the device under test. See Figure 4.

24) Input waveform timing is referenced from the input signal crossing at the V_IH.AClevel for a rising signal and V_IL.ACfor a falling signal applied

to the device under test. See Figure 4.

25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to

its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT.PER, t_JIT.CC

,

etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should

be met whether clock jitter is present or not.

26) t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis the specification value under

the max column. {The less half-pulse width distortion present, the larger the t_QHvalue is; and the larger the valid data eye will be.}

Examples: 1) If the system provides t_HPof 1315 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 975 ps minimum. 2) If the system

provides t_HPof 1420 ps into a DDR2–667 SDRAM, the DRAM provides t_QHof 1080 ps minimum.

27) t_QHSaccounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation

of the output drivers.

28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C

and 95 °C.

29) 0 °C≤ T_CASE≤ 85 °C

30) 85 °C < T_CASE≤ 95 °C

31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.

32) t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the device output is no longer driving

(t_RPST), or begins driving (t_RPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (t_RPST), or begins

driving (t_RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the

calculation is consistent.

Rev. 1.0, 2007-07

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HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.PERof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.PER.MIN= – 72 ps

and t_JIT.PER.MAX= + 93 ps, then t_{RPRE.MIN(DERATED)}= t_RPRE.MIN+ t_JIT.PER.MIN= 0.9 x t_CK.AVG– 72 ps = + 2178 ps and t_{RPRE.MAX(DERATED)}= t_RPRE.MAX

+ t_JIT.PER.MAX= 1.1 x t_CK.AVG+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).

34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_JIT.DUTYof the input clock. (output

deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_JIT.DUTY.MIN= – 72 ps

and t_JIT.DUTY.MAX= + 93 ps, then t_{RPST.MIN(DERATED)}= t_RPST.MIN+ t_JIT.DUTY.MIN= 0.4 x t_CK.AVG– 72 ps = + 928 ps and t_{RPST.MAX(DERATED)}= t_RPST.MAX

+ t_JIT.DUTY.MAX= 0.6 x t_CK.AVG+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).

35) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM= RU{t_PARAM/ t_CK.AVG}, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP= RU{t_RP/ t_CK.AVG}, which is in

clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP= 15 ns, the device will support

t_nRP= RU{t_RP/ t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at

Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.

36) t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

TABLE 16

DRAM Component Timing Parameter by Speed Grade - DDR2–667

Parameter

Symbol

DDR2–667

Unit

Notes^1)2)3)4)5)6)

7)8)

Min.

Max.

9)

DQ output access time from CK / CK

CAS to CAS command delay

Average clock high pulse width

Average clock period

t_AC

–450

2

+450

—

ps

t_CCD

nCK

t_CK.AVG

ps

10)11)

12)

t_CH.AVG

t_CK.AVG

0.48

3000

3

0.52

8000

—

CKE minimum pulse width ( high and low pulse t_CKE

nCK

width)

10)11)

13)14)

Average clock low pulse width

t_CL.AVG

0.48

0.52

—

t_CK.AVG

nCK

ns

Auto-Precharge write recovery + precharge time t_DAL

WR + t_nRP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_DELAY

t_IS+ t_{CK .AVG}

t_IH

+

––

19)20)15)

9)

DQ and DM input hold time

t_DH.BASE

t_DIPW

t_DQSCK

t_DQSH

175

––

ps

DQ and DM input pulse width for each input

DQS output access time from CK / CK

DQS input high pulse width

0.35

–400

0.35

—

t_CK.AVG

ps

+400

—

t_CK.AVG

ps

DQS input low pulse width

t_DQSL

—

16)

17)

DQS-DQ skew for DQS & associated DQ signals t_DQSQ

240

+ 0.25

DQS latching rising transition to associated clock t_DQSS

– 0.25

t_CK.AVG

edges

18)19)20)

17)

DQ and DM input setup time

t_DS.BASE

t_DSH

t_DSS

100

0.2

37.5

50

––

—

__

ps

DQS falling edge hold time from CK

DQS falling edge to CK setup time

t_CK.AVG

ns

17)

35)

Four Activate Window for 1KB page size products t_FAW

Four Activate Window for 2KB page size products t_FAW

35)

ns

21)

CK half pulse width

t_HP

Min(t_CH.ABS

,

ps

t_CL.ABS

)

9)22)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

ps

25)23)

t_IH.BASE

275

—

Rev. 1.0, 2007-07

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07242007-LR08-OZC0

Internet Data Sheet

HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C

Registerd DDR2 SDRAM Module

Parameter

Symbol

DDR2–667

Min.

Unit

Notes^1)2)3)4)5)6)

7)8)

Max.

Control & address input pulse width for each input t_IPW

0.6

—

t_CK.AVG

ps

24)25)

9)22)

35)

Address and control input setup time

DQ low impedance time from CK/CK

DQS/DQS low-impedance time from CK / CK

MRS command to ODT update delay

Mode register set command cycle time

OCD drive mode output delay

t_IS.BASE

200

—

t_LZ.DQ

t_LZ.DQS

t_MOD

t_MRD

t_OIT

2 x t_AC.MIN

t_AC.MAX

12

ps

t_AC.MIN

ps

0

2

0

ns

—

nCK

ns

35)

12

26)

DQ/DQS output hold time from DQS

DQ hold skew factor

t_QH

t

_HP– t_QHS

—

ps

27)

t_QHS

t_REFI

—

340

7.8

3.9

—

ps

28)29)

29)30)

31)

Average periodic refresh Interval

—

µs

—

µs

Auto-Refresh to Active/Auto-Refresh command t_RFC

127.5

ns

period

Precharge-All (8 banks) command period

Read preamble

t_RP

t

_RP+ 1 × t_CK

—

ns

32)33)

32)34)

35)

t_RPRE

t_RPST

t_RRD

0.9

0.4

7.5

1.1

0.6

—

t_CK.AVG

ns

Read postamble

Active to active command period for 1KB page

size products

35)

Active to active command period for 2KB page

size products

t_RRD

10

—

ns

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

0.35

0.4

15

—

0.6

—

ns

t_WPRE

t_WPST

t_WR

t_CK.AVG

ns

Write postamble

35)

Write recovery time

35)36)

Internal write to read command delay

Exit power down to read command

t_WTR

t_XARD

7.5

2

ns

nCK

Exit active power-down mode to read command t_XARDS

7 – AL

(slow exit, lower power)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

t_XP

2

—

nCK

35)

Exit self-refresh to a non-read command

Exit self-refresh to read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

nCK

Write command to DQS associated clock edges WL

RL–1