HYS72T1G842EFA-3S-C2 [QIMONDA]
DDR DRAM Module, 1GX72, CMOS, GREEN, DIMM-240;![HYS72T1G842EFA-3S-C2](http://pdffile.icpdf.com/pdf2/p00310/img/icpdf/HYS72T1G842E_1864555_icpdf.jpg)
型号: | HYS72T1G842EFA-3S-C2 |
厂家: | ![]() |
描述: | DDR DRAM Module, 1GX72, CMOS, GREEN, DIMM-240 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总29页 (文件大小:1151K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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July 2008
HYS72T1G842EFA-3S-C2
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
EU RoHS Compliant Products
Advance
Internet Data Sheet
Rev.0.60
Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.0.60, 2008-07-25
All
All
Adapted Internet Edition
Portfolio Change
Previous Revision: Rev. 0.53, 2008-07
Page 1 Editorial change
Previous Revision: Rev. 0.52, 2008-07
All
Editorial change
Page 20
Updated “SPD Codes” on Page 20
Previous Revision: Rev. 0.51, 2008-05
Page 24
Changed Table 15 “Raw Card Reference” on Page 24
Previous Revision: Rev. 0.50, 2008-02
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_A4, 4.20, 2008-01-25
03062008-DGNT-Z82N
2
Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
1
Overview
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
1.1
Features
•
240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM
Module for PC, Workstation and Server main memory
applications.
four rank 1024M × 72 module organization, and
2 ×256M × 4 chip organization.
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
8GB Modules built with chipsize packages PG-TFBGA-63.
Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
High-Speed Differential Point-to-Point Link Interface at
1.5 V (industry standard pending).
•
Detects errors on the channel and reports them to the host
memory controller.
Automatic DDR2 DRAM Bus Calibration.
Automatic Channel Calibration.
•
•
•
•
•
•
•
•
•
•
•
Full Host Control of the DDR2 DRAMs.
Over-Temperature Detection and Alert.
Hot Add-on and Hot Remove Capability.
MBIST and IBIST Test Functions.
Transparent Mode for DRAM Test Support.
Low profile: 133.35 mm x 30.35 mm
240 Pin gold plated card connector with 1.00mm contact
centers (industry standard pending).
Based on industry standard reference card designs
(industry standard pending).
•
•
•
•
•
•
•
•
Host Interface and AMB component industry standard
compliant.
Supports SMBus protocol interface for access to the AMB
configuration registers.
SPD (Serial Presence Detect) with 256 Byte serial
E2PROM.Performance.
RoHS Compliant Products1)
TABLE 1
Performance Table
QAG Speed Code
–3S
Unit
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
DDR2–667D
PC2–5300D
5–5–5
tCK
Max. Clock Frequency
CL3
CL5
CL4
fCK3
fCK5
fCK4
tRCD
tRP
200
333
266
15
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
ns
tRAS
tRC
45
ns
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
1.2
Description
This document describes the electrical and mechanical
features of a 240-pin, PC2-5300F ECC type, Fully Buffered
Double-Data-Rate Two Synchronous DRAM Dual In-Line
Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered
DIMMs use commodity DRAMs isolated from the memory
channel behind a buffer on the DIMM. They are intended for
use as main memory when installed in systems such as
servers and workstations. PC2-5300F refers to the DIMM
naming convention indicating the DDR2 SDRAMs running at
333 MHz clock speed and offering 5300 Mbit/s peak
bandwidth. FB-DIMM features a novel architecture including
the Advanced Memory Buffer. This single chip component,
located in the center of each DIMM, acts as a repeater and
buffer for all signals and commands which are exchanged
between the host controller and the DDR2 SDRAMs including
data in- and output. The AMB communicates with the host
controller and / or the adjacent DIMMs on a system board
using an Industry Standard High-Speed Differential Point-to-
Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
TABLE 2
Ordering Information
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-5300 (5-5-5)
HYS72T1G842EFA-3S-C2 8GB 4R×4 PC2–5300F–555–11–Y0
4 Ranks, ECC
1Gbit (×4)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–5300F–555–11–Y0" where 5300F
means Fully-Buffered DIMM modules with 5.34 GB/sec Module Bandwidth and "555–11" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.1 and
produced on the Raw Card "Y".
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
8GB
1024M × 72
4
ECC
36 DDP
14/3/11
Y
TABLE 4
Components on Modules
DRAM Organisation
2 ×256M × 4
Product Type1)2)
DRAM Components1)
DRAM Density
HYS72T1G842EFA
1) Green Product
HYB18T2G406C2F
2 ×1Gbit
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev.0.60, 2008-07-25
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns
Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of FB-DIMM
Pin#
Name Pin
Type
Buffer
Type
Function
Clock Signals
228
229
SCK
SCK
I
HSDL_15
HSDL_15
System Clock Input, positive line
System Clock Input, negative line
I
Control Signals
17
RESE
I
LV-CMOS
AMB reset signal
T
Northbound
22
25
28
31
34
37
51
54
57
60
63
66
48
40
23
26
29
32
35
38
52
55
58
61
64
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
PN11
PN12
PN13
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Northbound Data, positive lines
Rev.0.60, 2008-07-25
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Pin#
Name Pin
Type
Buffer
Type
Function
67
PN11
PN12
PN13
SN0
O
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
49
O
O
I
41
142
145
148
151
154
157
171
174
177
180
183
186
168
160
143
146
149
152
155
158
172
175
178
181
184
187
169
161
Southbound
70
Secondary Northbound Data, positive lines
SN1
I
SN2
I
SN3
I
SN4
I
SN5
I
SN6
I
SN7
I
SN8
I
SN9
I
SN10
SN11
SN12
SN13
SN0
I
I
I
I
I
SN1
I
SN2
I
SN3
I
SN4
I
SN5
I
SN6
I
SN7
I
SN8
I
SN9
I
SN10
SN11
SN12
SN13
I
I
I
I
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
I
I
I
I
I
I
I
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Southbound Data, positive lines
73
76
79
82
93
96
99
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Pin#
Name Pin
Type
Buffer
Type
Function
102
90
PS8
PS9
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
I
71
I
Primary Southbound Data, negative lines
Secondary Southbound data, positive lines
Secondary Southbound data, negative lines
74
I
77
I
80
I
83
I
94
I
97
I
100
103
91
I
I
I
190
193
196
199
202
213
216
219
222
210
191
194
197
200
203
214
217
220
223
211
EEPROM
120
119
239
240
118
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
I/O
Serial Bus Data
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
Power Supplies
238 VDDSPD PWR
–
EEPROM Power Supply
Rev.0.60, 2008-07-25
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Pin#
Name Pin
Type
Buffer
Type
Function
9,10,12,13,
129,130,132,
133
VCC
PWR
–
AMB Core Power / Channel Interface Power
15,117,135, VTT
237
PWR
PWR
–
–
Address/Command/Clock Termination Power
Power Supply
1,2,3,5,6,7,
VDD
108,109,111,
112,113,115,
116,121,122,
123,125,126,
127,231,232,
233,235,236
4,8,11,14,18, VSS
21,24,27,30,
33,36,39,42,
43,46,47,50,
53,56,59,62,
65,68,69,72,
75,78,81,84,
85,88,89,92,
95,98,101,
GND
–
Ground Plane
104,107,110,
114,124,128,
131,134,138,
141,144,147,
150,153,156,
159,162,163,
166,167,170,
173,176,179,
182,185,188,
189,192,195,
198,201,204,
205,208,209,
212,215,218,
221,224,227,
230,234
Other Pins
19,20,44,45, RFU
86,87,105,
106,139,140,
164,165,206,
207,225,226
NC
–
Not connected
Pins not connected on Infineon FB-DIMM’s. Pin positions are reserved for
future architecture flexibility.
136
16
VID0
VID1
–
–
–
–
Voltage ID
Note: These Pins must be unconnected for DDR2-based Fully Buffered
DIMMs VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is
VCC value: OPEN = 1.5 V, GND = 1.2 V
137
Test
AI
–
VREF
Note: Pin must be unconnected for normal operation
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
HSDL_15
LV-CMOS
CMOS
High-Speed Differential Point-to-Point Link Interface at 1.5 V
Low Voltage CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple
devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
10
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for FB-DIMM (240 pin)
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Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
11
Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
3
Basic Functionality
This chapter describes the basic functionality.
3.1
Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.
3.2
Advanced Memory Buffer Functionality
The Advanced Memory Buffer will perform the following FB-
DIMM channel functions:
•
•
•
Detects errors on the channel and reports them to the host
memory controller.
Support the FB-DIMM configuration register set as defined
in the register chapters.
Acts as DRAM memory buffer for all read, write, and
configuration accesses addressed to the DIMM.
Provides a read buffer FIFO and a write buffer FIFO.
Supports an SMBus protocol interface for access to the
AMB configuration registers.
Provides logic to support MEMBIST and IBIST Design for
Test functions.
Provides a register interface for the thermal sensor and
status indicator.
Functions as a repeater to extend the maximum length of
FB-DIMM Links.
•
Supports channel initialization procedures as defined in
the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame
boundaries, verify channel connectivity, and identify AMB
DIMM position.
•
•
•
•
Supports the forwarding of southbound and northbound
frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the
return data into the northbound frames.
If the AMB resides on the last DIMM in the channel, the
AMB initializes northbound frames.
•
•
•
Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower
speed tester access to DRAM pins through the FB-DIMM I/O
pins. This allows the tester to send an arbitrary test pattern to
the DRAMs. Transparent mode only supports a maximum
DRAM frequency equivalent to DDR2 400. Transparent mode
functionality:
•
Reconfigures FB-DIMM inputs from differential high speed
link receivers to two single ended lower speed receivers
(~200 MHz).
These inputs directly control DDR2 Command/Address
and input data that is replicated to all DRAMs.
Uses low speed direct drive FB-DIMM outputs to bypass
high speed Parallel/Serial circuitry and provide test results
back to tester.
•
•
DDR2 SDRAM Interface
•
•
Supports DDR2 at speeds of 667 MT/s.
Supports 256Mb, 512Mb and 1Gb devices in x4 and x8
configurations.
•
72-bit DDR2 SDRAM memory array.
3.3
Interfaces
Figure 2 illustrates the Advanced Memory Buffer and all of its
interfaces. They consist of two FB-DIMM links, one DDR2
channel and an SMBus interface. Each FB-DIMM link
connects the Advanced Memory Buffer to a host memory
controller or an adjacent FB-DIMM. The DDR2 channel
supports direct connection to the DDR2 SDRAMs on a Fully
Buffered DIMM.
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
12
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
FIGURE 2
Block Diagram Advanced Memory Buffer Interface
0
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Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide
expansion from a single DIMM per channel to up to 8 DIMMs
per channel. The host sends data on the southbound link to
the first DIMM where it is received and redriven to the second
DIMM. On the southbound data path each DIMM receives the
data and again re-drives the data to the next DIMM until the
last DIMM receives the data. The last DIMM in the chain
initiates the transmission of data in the direction of the host
(a.k.a. northbound). On the northbound data path each DIMM
receives the data and re-drives the data to the next DIMM
until the host is reached.
FIGURE 3
Block Diagram of Channel Southbound and Northbound Paths
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
13
Advance Internet Data Sheet
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Fully-Buffered DDR2 SDRAM Modules
3.4
High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces
The Advanced Memory Buffer supports one FB-DIMM
Channel consisting of two bidirectional link interfaces using
highspeed differential point-to-point electrical signaling. The
southbound input link is 10 lanes wide and carries commands
and write data from the host memory controller or the
adjacent DIMM in the host direction. The southbound output
link forwards this same data to the next FB-DIMM. The
northbound input link is 14 lanes wide and carries read return
data or status information from the next FB-DIMM in the chain
back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any
read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel
southbound on 10 primary differential signal line pairs. Data
received from the DRAMs and status information travel
northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated
and travel further southbound on 10 secondary differential
pairs. Data and status information received from the adjacent
DIMM upstream travel further northbound on 14 secondary
differential pairs.
3.4.1
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports
direct connection to DDR2 SDRAMs. The DDR2 channel
supports two ranks of eight banks with 16 row/column
request, 64 data, and eight check-bit signals. There are two
copies of address and command signals to support DIMM
routing and electrical requirements. Four transfer bursts are
driven on the data and check-bit lines at 800 MHz.
Propagation delays between read data/check-bit strobe lanes
on a given channel can differ. Each strobe can be calibrated
by hardware state machines using write/read trial and error.
Hardware aligns the read data and check-bits to a single core
clock. The Advanced Memory Buffer provides four copies of
the command clock phase references (CLK[3:0]) and write
data/check-bit strobes (DQSs) for each DRAM nibble.
3.4.2
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface
to allow system access to configuration registers independent
of the FB-DIMM link. The Advanced Memory Buffer will never
be a master on the SMBus, only a slave. Serial SMBus data
transfer is supported at 100 kHz. SMBus access to the
Advanced Memory Buffer may be a requirement to boot and
to set link strength, frequency and other parameters needed
to insure robust configurations. It is also required for
diagnostic support when the link is down. The SMBus
address straps located on the DIMM connector are used by
the unique ID.
3.4.3
Channel Latency
FB-DIMM channel latency is measured from the time a read
request is driven on the FB-DIMM channel pins to the time
when the first 16 bytes (2nd chunk) of read completion data is
sampled by the memory controller. When not using the
Variable Read Latency capability, the latency for a specific
DIMM on a channel is always equal to the latency for any
other DIMM on that channel. However, the latency for each
DIMM in a specific configuration with some number of DIMMs
installed may not be equal to the latency for each FB-DIMM
in a configuration with some different number of DIMMs
installed. As more DIMMs are added to the channel,
additional latency is required to read from each DIMM on the
channel. Because the channel is based on the point-to-point
interconnection of buffer components between DIMMs,
memory requests are required to travel through N-1 buffers
before reaching the Nth buffer. The result is that a 4 DIMM
channel configuration will have greater idle read latency
compared to a 1 DIMM channel configuration. The Variable
Read Latency capability can be used to reduce latency for
DIMMs closer to the host. The idle latencies listed in this
section are representative of what might be achieved in
typical AMB designs. Actual implementations with latencies
less than the values listed will have higher application
performance and vice versa.
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
14
Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
3.4.4
Peak Theoretical Channel Throughput
An FB-DIMM channel transfers read completion data on the
Northbound data connection. 144 bits of data are transferred
for every Northbound data frame. This matches the 18-byte
data transfer of an ECC DDR DRAM in a single DRAM
command clock. A DRAM burst of 8 from a single channel or
a DRAM burst of four from two lock stepped channels
provides a total of 72 bytes of data (64 bytes plus 8 bytes
ECC). The FB-DIMM frame rate matches the DRAM
command clock because of the fixed 6:1 ratio of the FB-DIMM
channel clock to the DRAM command clock. Therefore, the
Northbound data connection will exhibit the same peak
theoretical throughput as a single DRAM channel. For
example, when using DDR2 533 DRAMs, the peak theoretical
bandwidth of the Northbound data connection is 4.267 GB/s.
Write data is transferred on the Southbound command and
data connection, via Command+Wdata frames. 72 bits of
data are transferred for every Command+Wdata frame. Two
Command+Wdata frames match the 18-byte data transfer of
an ECC DDR DRAM in a single DRAM command clock. A
DRAM burst of 8 transfers from a single channel, or a burst of
4 from two lock-step channels provides a total of 72 bytes of
data (64 bytes plus 8 bytes ECC). When the frame rate
matches the DRAM command clock, the Southbound
command and data connection will exhibit one half the peak
theoretical throughput of a single DRAM channel. For
example, when using DDR2 533 DRAMs, the peak theoretical
bandwidth of the Southbound command and data connection
is 2.133 GB/s. The total peak theoretical throughput for a
single FB-DIMM channel is defined as the sum of the peak
theoretical throughput of the Northbound data connection and
the Southbound command and data connection. When the
frame rate matches the DRAM command clock, this is equal
to 1.5 times the peak theoretical throughput of a single DRAM
channel. For example, when using DDR2 533 DRAMs, the
peak theoretical throughput of a single DDR2-533 channel
would be 4.267 GB/s, while the peak theoretical throughput of
the entire FB-DIMM PC4200F channel would be 6.4 GB/s.
3.5
Hot-add
The FB-DIMM channel does not provide a mechanism to
automatically detect and report the addition of a new DIMM
south of the currently active last DIMM. It is assumed the
system will be notified through some means of the addition of
one or more new DIMMs so that specific commands can be
sent to the host controller to initialize the newly added
DIMM(s) and perform a Hot-Add Reset to bring them into the
channel timing domain. It should be noted that the power to
the DIMM socket must be removed before a “hot-add” DIMM
is inserted or removed. Applying or removing the power to a
DIMM socket is a system platform function.
3.6
Hot-remove
In order to accomplish removal of DIMMs the host must
perform a Fast Reset sequence targeted at the last DIMM that
will be retained on the channel. The Fast Reset re-establish
the appropriate last DIMM so that the Southbound Tx outputs
of the last active DIMM and the Southbound and Northbound
outputs of the DIMMs beyond the last active DIMM are
disabled. Once the appropriate outputs are disabled the
system can coordinate the procedure to remove power in
preparation for physical removal of the DIMM if needed. It
should be noted that the power to the DIMM socket must be
removed before a “hot-add” DIMM is inserted or removed.
Applying or removing the power to a DIMM socket is a system
platform function.
3.7
Hot-replace
Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
15
Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
4
Electrical Characteristics
This chapter describes the electrical characteristics.
4.1
Operating Conditions
This chapter describes the operating conditions.
TABLE 8
Absolute Maximum Ratings
Parameter
Symbol
Rating
Min.
Unit
Notes
Max.
1)
2)
Voltage on any SMbus interface signal pin relative to VSS
Voltage on VDD pin relative to VSS
Voltage on VCC pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Voltage on VTT pin relative to VSS
Storage Temperature
VIN, VOUT
VDD
–0.5
–0.5
–0,3
–0.5
–0.5
–0.3
–0.5
–55
+4.00
+2.4
V
V
V
V
V
V
V
°C
VCC
+1.75
+2.3
–
2)3)
VDDQ
VDDL
2)3)
2)
+2.3
VIN, VOUT
VTT
+1.75
+2.3
–
2)3)
TSTG
+100
1) Stresses greater than those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
3) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
16
Advance Internet Data Sheet
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Fully-Buffered DDR2 SDRAM Modules
TABLE 9
Operating Temperature Range
Parameter
Symbol Values
Min Max
Unit Note
1)2)
3)4)
1)2)
Junction Temperature
TJ
0
0
0
115
95
°C
°C
°C
DRAM Component Case Temperature Range
AMB Component Case Temperature Range
TCASE
111
1) Stresses greater than those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2) Within the DRAM Component Case temperature range all DRAM specifications will be supported.
3) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C case
temperature before initiating self-refresh operation.
4) Above 85 °C DRAM case temperature the Auto-Refresh command has to be reduced to tREFI = 3.9 μs.
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit Notes
Min.
Nom.
Max.
1)
AMB Supply Voltage DC
AMB Supply Voltage DC + AC
DRAM Supply Voltage
VCC
1.455
1.425
1.7
1.5
1.575
1.590
1.9
V
2)
1.5
V
VDD
1.8
V
–
–
Termination Voltage
VTT
0.48 ×VDD
3.0
0.50 ×VDD
0.52 ×VDD
3.6
V
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
DC Input Logic High(RESET)
DC Input Logic Low(RESET)
Leakage Current (RESET)
Leakage Current (Link)
VDDSPD
VIH(DC)
VIL(DC)
VIH(DC)
VIL(DC)
IL
3.3
—
—
—
—
—
—
V
–
3)
2.1
VDDSPD
0.8
V
3)
4)
3)
4)
5)
—
V
1.0
—
V
—
+0.5
+90
V
–90
–5
μΑ
μΑ
IL
+5
1) At 0KHz - 30KHz.
2) At 30KHz - 1 MHz.
3) Applies for SMB and SPD Bus Signals.
4) Applies for AMB CMOS Signal RESET.
5) For all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications.
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HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
TABLE 11
FB-DIMM Latency Range
Parameter
DDR2–667D
Min.
Unit
Note
Typ.
Max.
1)
tC2D_DIMM
17.5
1.4
1.3
2.5
2.4
21
21.5
2.4
2.3
3.7
3.6
ns
ns
ns
ns
ns
1)2)
1)3)
1)4)
1)5)
tRESAMPLE_DIMM_SB
tRESAMPLE_DIMM_NB
tRESYNC_DIMM_SB
tRESYNC_DIMM_NB
1.69
1.73
2.8
2.8
1) Measured delay at FB-DIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector
pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) – [CL (DRAM CAS
latency) value] * [frame clock period – AL (DRAM additional latency) value * frame clock period].
2) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the primary southbound lane 8 (connector pins 102
& 103) and the center of the 1st UI of the same frame on the secondary southbound lane 8 (connector pins 222 & 223).
3) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins
142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
4) Measured delay at FB-DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins
142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
5) Measured delay at FB-DIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector
pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) – [CL (DRAM CAS
latency) value] * [frame clock period – AL (DRAM additional latency) value * frame clock period].
TABLE 12
Environmental Parameters
Parameter
Symbol
Rating
Units
Notes
1)
2)
2)
2)
2)
2)
Operating Temperature
TOPR
HOPR
TSTG
HSTG
PBAR
PBAR
See Note
10 to 90
-50 to +100
5 to 95
Operating Humidity (relative)
Storage Temperature
%
°C
%
m
m
Storage Humidity (without condensation)
Barometric pressure (operating)
Barometric pressure (storage)
3050
14240
1) The designer must meet the case temperature specifications for individual module components.
2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Attention: The specified maximum operating temperature for DRAM components should not be exceeded. Please
make sure that the system provides sufficient cooling.
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HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
5
Current Spec. and Conditions
The following table provides an overview of the measurement conditions.
TABLE 13
DD Measurement Conditions
I
Parameter
Symbol
Idle Current, single or last DIMM
L0 state, idle (0 BW)
ICC_Idle_0
IDD_Idle_0
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
Idle Current, first DIMM
L0 state, idle (0 BW)
ICC_Idle_1
IDD_Idle_1
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
Active Power
L0 state
ICC_Active_1
IDD_Active_1
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB.
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.
7. Termination is referenced to VTT = VDD / 2.
5.1
ICC/IDD Conditions
In the following table you can find the Measurement Conditions and Power Supply Currents.
Conditions have TBD.
Rev.0.60, 2008-07-25
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Fully-Buffered DDR2 SDRAM Modules
6
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
Table 14 “PC2–5300–555” on Page 20
TABLE 14
PC2–5300–555
Product Type
Organization
HYS72T1G842EFA–3S–C2
8 GByte
×72
4 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
0
SPD Size CRC / Total / Used
SPD Revision
92
11
09
12
49
23
07
20
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
1
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
3
4
5
Module Physical Attributes
Module Type
6
7
Module Organization
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
9
10
11
12
13
14
15
16
17
18
19
20
t
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
t
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
HYS72T1G842EFA–3S–C2
8 GByte
×72
4 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
t
t
t
t
t
t
t
t
RP.MIN (min. Row Precharge Time)
3C
00
B4
F0
FE
01
1E
RAS and tRC Extension
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
RFC.MIN LSB (min. Refresh Recovery Time Delay)
RFC.MIN MSB (min. Refresh Recovery Time Delay)
WTR.MIN (min. Internal Write to Read Cmd Delay)
RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
41
51
60
44
34
3D
28
3E
22
23
00
11
00
02
00
10
54
50
44
26
3F
50
t
REFI (avg. SDRAM Refresh Period)
CASE.MAX Delta / ΔT4R4W Delta
T
Psi(T-A) DRAM
ΔT0 (DT0) DRAM
ΔT2Q (DT2Q) DRAM
ΔT2P (DT2P) DRAM
ΔT3N (DT3N) DRAM
ΔT4R (DT4R) / ΔT4R4W Sign (DT4R4W) DRAM
ΔT5B (DT5B) DRAM
ΔT7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
85
86
87
88
89
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
ΔTIdle_0 (DT Idle_0) AMB
ΔTIdle_1 (DT Idle_1) AMB
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HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
HYS72T1G842EFA–3S–C2
8 GByte
×72
4 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
90
91
92
93
ΔTIdle_2 (DT Idle_2) AMB
ΔTActive_1 (DT Active_1) AMB
ΔTActive_2 (DT Active_2) AMB
ΔTL0s (DT L0s) AMB
54
57
53
00
00
11
1A
00
15
2F
08
C2
00
00
40
00
00
00
00
00
00
00
85
51
85
51
xx
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
Module Manufacturing Date Year
xx
Module Manufacturing Date Week
xx
122 -
125
Module Serial Number
xx
126
127
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
55
43
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
Product Type
Organization
HYS72T1G842EFA–3S–C2
8 GByte
×72
4 Ranks (×4)
PC2–5300F–555
Rev. 1.1
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
37
32
54
31
47
38
34
32
45
46
41
33
53
43
32
20
20
20
3x
xx
Test Program Revision Code
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
85
51
44
00
00
152 -
175
176 -
255
Blank for customer use
FF
Rev.0.60, 2008-07-25
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HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
7
Package Outline
All Components are surface mounted on one or both sides of
the printed circuit board (PCB) and positioned on the PCB to
meet the minimum and maximum trace lengths required for
DDR2 SDRAM signals. Bypass capacitors for DDR2 SDRAM
devices are located near the device power pins. The AMB
device in the center of the DIMM has a metal Heat Sink.
TABLE 15
Raw Card Reference
Raw Card
PCB
Dimensions
Width [mm] Height [mm] Thickness [mm] Notes
1)2)3)4)5)
R/C Y
LG-DIM-240-28
Figure 4
133.35
30.35
8.2
1) Thickness includes Heat Sink. Some early production modules with Heatspreader may be thicker up to 8.2mm.
2) Please contact your sales or marketing representative for more details on package dimensions.
3) Drawing according to ISO 8015.
4) Dimensions in mm.
5) General tolerances +/- 0.15.
Attention: Heat Sink heats up during operation. When unplugging a DIMM from a system direct skin contact should
be avoided until the Heat Sink has reached room temperature.
Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries.
Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while plugging or
unplugging the module may permanently damage the DIMM.
Rev.0.60, 2008-07-25
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Fully-Buffered DDR2 SDRAM Modules
FIGURE 4
Package Outline LG-DIM-240-28 with Full Module Heat Sink
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Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
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Advance Internet Data Sheet
HYS72T1G842EFA-3S-C2
Fully-Buffered DDR2 SDRAM Modules
8
Product Type Nomenclature
TABLE 16
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
12
FB-DIMM
HYS
HYB
72
18
T
T
256
512
5
2
0
0
E
A
F
A
–3S
–5
–A
DDR2 DRAM
16
C
TABLE 17
FB-DIMM Nomenclature
Field
Description
Values
Coding
1
Prefix
HYS
Standard prefix for SDRAM-based memory
products
2
Data width
64
72
T
¥ 64 (Non-ECC)
¥ 72 (ECC)
3
4
Power supply
Memory density per DQ1)
1.8 V (DDR2 SDRAM Modules)
256 MByte
32
64
128
256
512
1G
2G
0 .. 9
0
512 MByte
1 GByte
2 GByte
4 GByte
8 GByte
16 GByte
5
6
Designator
Data sheet defined (heat sink options)
One memory module rank
Two memory module ranks
Four memory module ranks
Product variations
Lead- and halogen-free (RoHS-compliant)
Lead-free (RoHS-compliant)
SO-DIMM
Number of memory ranks
1
2
7
8
Designator
0 .. 9
E
Package type
H
9
Module family
D
M
Micro-DIMM
R
Registered DIMM
Unbuffered DIMM
Fully-buffered DIMM
U
F
Rev.0.60, 2008-07-25
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Advance Internet Data Sheet
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Fully-Buffered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Power & AMB
N / D / A / E
L
AMB variants
Low operation voltage (1.55 V)
PC2–6400 5–5–5
11
Speed
–25F
–2.5
–3
PC2–6400 6–6–6
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
–5
PC2–4200 4–4–4
PC2–3200 3–3–3
12
Product revision
–A ...
Die revision of component
1) Multiplying “Memory density per DQ” with “Data width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module
memory density in MBytes as listed in column “Coding”.
TABLE 18
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Prefix
HYB
18
Memory component
1.8 V
Supply voltage
Memory type
Memory density
T
DDR2 (Double-Data-Rate-Two SDRAM)
256 Mbit
256
512
1G
2G
40
512 Mbit
1024 Mbit
2048 Mbit
5+6
7
Organization
× 4
80
× 8
16
× 16
Product variation
0
Standard product
Stacked die in an FBGA
Die revision
2
8
9
Product revision
Package
A .. Z
C
FBGA; Lead-containing
FBGA; Lead- and halogen-free
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
F
11
Speed
–25F
–2.5
–3
–3S
–3.7
–5
Rev.0.60, 2008-07-25
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Fully-Buffered DDR2 SDRAM Modules
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
Basic Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Advanced Memory Buffer Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hot-add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hot-remove. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Hot-replace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.6
3.7
4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
5.1
Current Spec. and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ICC/IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
7
8
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rev.0.60, 2008-07-25
03062008-DGNT-Z82N
28
Advance Internet Data Sheet
Edition 2008-07-25
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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