ALC5626-GRT [REALTEK]
I2S AUDIO DAC HEADPHONE AND STEREO CLASS-AB/D SPEAKER AMPLIFIER;
| 型号： | ALC5626-GRT |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | I2S AUDIO DAC HEADPHONE AND STEREO CLASS-AB/D SPEAKER AMPLIFIER 放大器 |
| 文件： | 总55页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALC5626
I2S AUDIO DAC + HEADPHONE AND STEREO
CLASS-AB/D SPEAKER AMPLIFIER
DATASHEET
Rev. 1.0
10 September 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5626
Datasheet
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5626 Audio DAC IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date
Summary
1.0
2009/09/10
First release.
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Speaker Amplifier
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Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
SYSTEM APPLICATIONS...............................................................................................................................................3
BLOCK DIAGRAMS.........................................................................................................................................................4
4.1.
4.2.
FUNCTION BLOCK ........................................................................................................................................................4
AUDIO MIXER PATH.....................................................................................................................................................5
5.
6.
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................6
PIN DESCRIPTIONS.........................................................................................................................................................7
6.1.
DIGITAL I/O PINS.........................................................................................................................................................7
ANALOG I/O PINS ........................................................................................................................................................7
FILTER/REFERENCE/TEST PINS ....................................................................................................................................8
POWER & GROUND PINS ..............................................................................................................................................8
NOT CONNECTED.........................................................................................................................................................8
6.2.
6.3.
6.4.
6.5.
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................9
7.1.
7.2.
POWER .........................................................................................................................................................................9
RESET ..........................................................................................................................................................................9
7.2.1. Power-On Reset (POR) ..........................................................................................................................................9
7.3.
7.4.
CLOCKING..................................................................................................................................................................10
I2C CONTROL INTERFACE ..........................................................................................................................................11
7.4.1. Addressing Setting................................................................................................................................................11
7.4.2. Complete Data Transfer.......................................................................................................................................11
7.4.3. Odd-Addressed Register Access ...........................................................................................................................12
7.5.
DIGITAL DATA INTERFACE ........................................................................................................................................12
7.5.1. I2S/PCM Interface ................................................................................................................................................12
7.6.
ANALOG SIGNAL PATH ..............................................................................................................................................14
7.6.1. Line Input .............................................................................................................................................................14
7.6.2. Auxiliary Input......................................................................................................................................................15
7.6.3. LINE3 Input..........................................................................................................................................................15
7.6.4. Speaker Output.....................................................................................................................................................15
7.6.5. Headphone Output................................................................................................................................................15
7.6.6. Stereo DAC...........................................................................................................................................................16
7.6.7. Headphone Mixer.................................................................................................................................................16
7.6.8. Speaker Mixer.......................................................................................................................................................16
7.7.
7.8.
POWER MANAGEMENT...............................................................................................................................................17
GPIO AND JACK DETECT (JD) FUNCTION ..................................................................................................................17
7.8.1. GPIO Interface.....................................................................................................................................................17
7.8.2. Interrupt ...............................................................................................................................................................17
7.9.
7.10.
7.11.
HEADPHONE DEPOP ...................................................................................................................................................17
AVC CONTROL..........................................................................................................................................................18
ZERO CROSS ..............................................................................................................................................................19
8.
REGISTER DESCRIPTIONS.........................................................................................................................................20
8.1. REG-02H: SPEAKER OUTPUT VOLUME.......................................................................................................................20
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8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
REG-04H: HEADPHONE OUTPUT VOLUME .................................................................................................................20
REG-08: AUXILIARY INPUT VOLUME.........................................................................................................................21
REG-0A: LINE INPUT VOLUME...................................................................................................................................21
REG-0C: STEREO DAC DIGITAL VOLUME .................................................................................................................22
REG-0E: LINE3 VOLUME ..........................................................................................................................................23
REG-16H: SOFT DELAY VOLUME CONTROL TIME......................................................................................................23
REG-1CH: OUTPUT MIXER CONTROL ........................................................................................................................24
REG-34H: STEREO AUDIO SERIAL DATA PORT CONTROL ..........................................................................................25
REG-38H: STEREO DAC CLOCK CONTROL ................................................................................................................25
REG-3AH: POWER MANAGEMENT ADDITION 1..........................................................................................................26
REG-3CH: POWER MANAGEMENT ADDITION 2..........................................................................................................27
REG-3EH: POWER MANAGEMENT ADDITION 3 ..........................................................................................................28
REG-40H: GENERAL PURPOSE CONTROL ...................................................................................................................28
REG-42H: GLOBAL CLOCK CONTROL ........................................................................................................................29
REG-44H: PLL M/N CODE CONTROL.........................................................................................................................30
REG-48H: INTERNAL STATUS AND IRQ CONTROL .....................................................................................................30
REG-4AH: GPIO CONTROL........................................................................................................................................31
REG-5AH: JACK DETECT CONTROL ...........................................................................................................................31
REG-5CH: MISC1 CONTROL......................................................................................................................................32
REG-5EH: MISC2 CONTROL......................................................................................................................................33
REG-66H: EQ CONTROL.............................................................................................................................................34
REG-68H: AVC CONTROL..........................................................................................................................................35
REG-6AH: PRIVATE REGISTER INDEX ........................................................................................................................35
REG-6CH: PRIVATE REGISTER DATA .........................................................................................................................35
PRIVATE-00H: EQ BAND-0 COEFFICIENT (LP0: A1) ..................................................................................................36
PRIVATE-01H: EQ BAND-0 GAIN (LP0: HO)..............................................................................................................36
PRIVATE-02H: EQ BAND-1 COEFFICIENT (BP1: A1) ..................................................................................................36
PRIVATE-03H: EQ BAND-1 COEFFICIENT (BP1: A2) ..................................................................................................36
PRIVATE-04H: EQ BAND-1 GAIN (BP1: HO)..............................................................................................................37
PRIVATE-05H: EQ BAND-2 COEFFICIENT (BP2: A1) ..................................................................................................37
PRIVATE-06H: EQ BAND-2 COEFFICIENT (BP2: A2) ..................................................................................................37
PRIVATE-07H: EQ BAND-2 GAIN (BP2: HO)..............................................................................................................37
PRIVATE-08H: EQ BAND-3 COEFFICIENT (BP3: A1) ..................................................................................................37
PRIVATE-09H: EQ BAND-3 COEFFICIENT (BP3: A2) ..................................................................................................38
PRIVATE-0AH: EQ BAND-3 GAIN (BP3: HO).............................................................................................................38
PRIVATE-0BH: EQ BAND-4 COEFFICIENT (HPF: A1) .................................................................................................38
PRIVATE-0CH: EQ BAND-4 GAIN (HPF: HO).............................................................................................................38
PRIVATE-11H: EQ INPUT VOLUME CONTROL ............................................................................................................39
PRIVATE-12H: EQ OUTPUT VOLUME CONTROL.........................................................................................................39
PRIVATE-21H: AUTO VOLUME CONTROL REGISTER 1 ...............................................................................................39
PRIVATE-22H: AUTO VOLUME CONTROL REGISTER 2 ...............................................................................................39
PRIVATE-23H: AUTO VOLUME CONTROL REGISTER 3 ...............................................................................................40
PRIVATE-24H: AUTO VOLUME CONTROL REGISTER 4 ...............................................................................................40
PRIVATE-25H: AUTO VOLUME CONTROL REGISTER 5 ...............................................................................................40
PRIVATE-39H: DIGITAL INTERNAL REGISTER ............................................................................................................40
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.
8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.
8.42.
8.43.
8.44.
8.45.
8.46.
9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................41
9.1.
DC CHARACTERISTICS...............................................................................................................................................41
9.1.1. Absolute Maximum Ratings..................................................................................................................................41
9.1.2. Recommended Operating Conditions...................................................................................................................41
9.1.3. Static Characteristics ...........................................................................................................................................41
9.2.
9.3.
ANALOG PERFORMANCE CHARACTERISTICS..............................................................................................................42
AC TIMING CHARACTERISTICS ..................................................................................................................................43
9.3.1. I2C Control Interface............................................................................................................................................43
9.3.2. I2S/PCM Interface Master Mode ..........................................................................................................................44
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Speaker Amplifier
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Datasheet
9.3.3. I2S/PCM Interface Slave Mode.............................................................................................................................45
10.
11.
12.
APPLICATION CIRCUITS .......................................................................................................................................46
MECHANICAL DIMENSIONS.................................................................................................................................47
ORDERING INFORMATION...................................................................................................................................48
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Speaker Amplifier
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List of Tables
TABLE 1. DIGITAL I/O PINS.........................................................................................................................................................7
TABLE 2. ANALOG I/O PINS ........................................................................................................................................................7
TABLE 3. FILTER/REFERENCE PINS .............................................................................................................................................8
TABLE 4. POWER/GROUND PINS .................................................................................................................................................8
TABLE 5. NOT CONNECTED PINS.................................................................................................................................................8
TABLE 6. RESET OPERATION.......................................................................................................................................................9
TABLE 7. POWER-ON RESET VOLTAGE .......................................................................................................................................9
TABLE 8. PLL CLOCK SETTING TABLE FOR 48K (UNIT: MHZ).................................................................................................10
TABLE 9. PLL CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ)..............................................................................................11
TABLE 10. MX02 SPEAKER OUTPUT VOLUME ...........................................................................................................................20
TABLE 11. MX04 HEADPHONE OUTPUT VOLUME ......................................................................................................................20
TABLE 12. MX08 AUXILIARY INPUT VOLUME ...........................................................................................................................21
TABLE 13. MX0A LINE INPUT VOLUME.....................................................................................................................................21
TABLE 14. MX0C STEREO DAC DIGITAL VOLUME ...................................................................................................................22
TABLE 15. MX0E LINE3 VOLUME ............................................................................................................................................23
TABLE 16. MX16 SOFT DELAY VOLUME CONTROL TIME ..........................................................................................................23
TABLE 17. MX1C OUTPUT MIXER CONTROL .............................................................................................................................24
TABLE 18. MX34 STEREO AUDIO SERIAL DATA PORT CONTROL...............................................................................................25
TABLE 19. MX38 STEREO DAC CLOCK CONTROL.....................................................................................................................25
TABLE 20. MX3A POWER MANAGEMENT ADDITION 1 ..............................................................................................................26
TABLE 21. HEADPHONE DRIVE ABILITY SELECTION ..................................................................................................................26
TABLE 22. MX3C POWER MANAGEMENT ADDITION 2...............................................................................................................27
TABLE 23. MX3E POWER MANAGEMENT ADDITION 3...............................................................................................................28
TABLE 24. MX40 GENERAL PURPOSE CONTROL ........................................................................................................................28
TABLE 25. MX42 GLOBAL CLOCK CONTROL .............................................................................................................................29
TABLE 26. MX44 PLL M/N CODE CONTROL .............................................................................................................................30
TABLE 27. MX48 INTERNAL STATUS AND IRQ CONTROL..........................................................................................................30
TABLE 28. MX4A GPIO CONTROL ............................................................................................................................................31
TABLE 29. MX5A JACK DETECT CONTROL................................................................................................................................31
TABLE 30. MX5C MISC1 CONTROL ..........................................................................................................................................32
TABLE 31. MX5E MISC2 CONTROL ..........................................................................................................................................33
TABLE 32. MX66 EQ CONTROL .................................................................................................................................................34
TABLE 33. MX68 AVC CONTROL ..............................................................................................................................................35
TABLE 34. MX6A PRIVATE REGISTER INDEX.............................................................................................................................35
TABLE 35. MX6C PRIVATE REGISTER DATA..............................................................................................................................35
TABLE 36. PR00H: EQ BAND-0 COEFFICIENT (LP0: A1) ............................................................................................................36
TABLE 37. PR01H: EQ BAND-0 GAIN (LP0: HO)........................................................................................................................36
TABLE 38. PR02H: EQ BAND-1 COEFFICIENT (BP1: A1)............................................................................................................36
TABLE 39. PR03H: EQ BAND-1 COEFFICIENT (BP1: A2)............................................................................................................36
TABLE 40. PR04H: EQ BAND-1 GAIN (BP1: HO) .......................................................................................................................37
TABLE 41. PR05H: EQ BAND-2 COEFFICIENT (BP2: A1)............................................................................................................37
TABLE 42. PR06H: EQ BAND-2 COEFFICIENT (BP2: A2)............................................................................................................37
TABLE 43. PR07H: EQ BAND-2 GAIN (BP2: HO) .......................................................................................................................37
TABLE 44. PR08H: EQ BAND-3 COEFFICIENT (BP3: A1)............................................................................................................37
TABLE 45. PR09H: EQ BAND-3 COEFFICIENT (BP3: A2)............................................................................................................38
TABLE 46. PR0AH: EQ BAND-3 GAIN (BP3: HO).......................................................................................................................38
TABLE 47. PR0BH: EQ BAND-4 COEFFICIENT (HPF: A1)...........................................................................................................38
TABLE 48. PR0CH: EQ BAND-4 GAIN (HPF: HO) ......................................................................................................................38
TABLE 49. PR11H: EQ INPUT VOLUME CONTROL ......................................................................................................................39
TABLE 50. PR12H: EQ OUTPUT VOLUME CONTROL...................................................................................................................39
TABLE 51. PR21 AUTO VOLUME CONTROL REGISTER 1 ............................................................................................................39
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Speaker Amplifier
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Datasheet
TABLE 52. PR22 AUTO VOLUME CONTROL REGISTER 2 ............................................................................................................39
TABLE 53. PR23 AUTO VOLUME CONTROL REGISTER 3 ............................................................................................................40
TABLE 54. PR24 AUTO VOLUME CONTROL REGISTER 4 ............................................................................................................40
TABLE 55. PR25 AUTO VOLUME CONTROL REGISTER 5 ............................................................................................................40
TABLE 56. PR39 DIGITAL INTERNAL REGISTER .........................................................................................................................40
TABLE 57. ABSOLUTE MAXIMUM RATINGS................................................................................................................................41
TABLE 58. RECOMMENDED OPERATING CONDITIONS.................................................................................................................41
TABLE 59. THRESHOLD VOLTAGE ..............................................................................................................................................41
TABLE 60. ANALOG PERFORMANCE CHARACTERISTICS .............................................................................................................42
TABLE 61. I2C CONTROL INTERFACE TIMING .............................................................................................................................43
TABLE 62. I2S/PCM MASTER MODE TIMING..............................................................................................................................44
TABLE 63. I2S/PCM SLAVE MODE TIMING.................................................................................................................................45
TABLE 64. ORDERING INFORMATION..........................................................................................................................................48
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................4
FIGURE 2. AUDIO MIXER PATH ...................................................................................................................................................5
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................6
FIGURE 4. AUDIO SYSCLK ......................................................................................................................................................10
FIGURE 5. DATA TRANSFER OVER I2C CONTROL INTERFACE ...................................................................................................11
FIGURE 6. WRITE WORD PROTOCOL .......................................................................................................................................12
FIGURE 7. READ WORD PROTOCOL .........................................................................................................................................12
FIGURE 8. PCM STEREO DATA MODE A FORMAT-1 (SEL_I2S_DATA_FORMAT=10’B, CTRL_I2S_BCLK_POLARITY=0’B) .........13
FIGURE 9. PCM STEREO DATA MODE A FORMAT-2 (SEL_I2S_DATA_FORMAT=10’B, CTRL_I2S_BCLK_POLARITY=1’B) .........13
FIGURE 10. PCM STEREO DATA MODE B FORMAT (SEL_I2S_DATA_FORMAT=11’B, CTRL_I2S_BCLK_POLARITY=0’B) ............13
FIGURE 11. I2S DATA FORMAT (SEL_I2S_DATA_FORMAT=00’B)................................................................................................14
FIGURE 12. LEFT-JUSTIFIED DATA FORMAT (SEL_I2S_DATA_FORMAT=01’B, CTRL_I2S_BCLK_POLARITY=0’B).......................14
FIGURE 13. AVC BLOCK OF DAC MODULE ...............................................................................................................................18
FIGURE 14. AVC BEHAVIOR.......................................................................................................................................................18
FIGURE 15. ZERO CROSS DISABLED WHEN OUTPUT MUTED.......................................................................................................19
FIGURE 16. ZERO CROSS ENABLED WHEN OUTPUT MUTED........................................................................................................19
FIGURE 17. GLOBAL CLOCK CONTROL.......................................................................................................................................29
FIGURE 18. I2C CONTROL INTERFACE WAVEFORM.....................................................................................................................43
FIGURE 19. I2S/PCM MASTER MODE WAVEFORM .....................................................................................................................44
FIGURE 20. I2S/PCM SLAVE MODE WAVEFORM ........................................................................................................................45
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Datasheet
1. General Description
The ALC5626 is a highly-integrated I2S/PCM interface audio DAC with multiple input/output ports, and
is designed for multimedia handheld devices. It provides a Stereo Hi-Fi DAC for playback via the
I2S/PCM interface.
To reduce component count, the ALC5626 can connect to:
• LINEIN_L/R stereo Single-Ended analog inputs that can be configured to Differential analog input
• AUXIN_L/R stereo Single-Ended analog inputs that can be configured to Differential analog input
• LINE3_L/R stereo Single-Ended analog inputs
• Single-Ended stereo Headphone Output
• STEREO Bridge-Tied Load (BTL) Speaker Output
Multiple analog input and output pins are provided for seamless integration with analog connected
wireless communication devices. Differential input/output connections efficiently reduce noise
interference, providing better sound quality. Class-AB/D amplifiers can be directly connected to an up to
2.4 Watt Stereo Speaker, removing the need for an additional amplifier, further cutting both cost and
required board area.
The ALC5626 AVDD operates at supply voltages from 2.3V to 3.6V. DCVDD and DBVDD operate
from 1.8 to 3.6V, and SPKVDD operates from 2.3 to 5V. To extend battery life, each section of the
device can be powered down individually under software control. Leakage current in maximum power
saving state is less than 10µA.
The ALC5626 is available in a 5x5mm ‘Green’ QFN-32 package, making it ideal for use in handheld
portable systems.
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Datasheet
2. Features
Digital-to-Analog Converter with 100dB SNR, and –86dB THD+N at 3.3V
Three analog stereo single-ended or one stereo differential input, LINEIN_L/R, AUXIN_L/R, and
LINE3_L/R
Stereo BTL (Bridge-Tied Load) Class-AB/D Speaker output with on-chip 2.4W speaker driver
(SPKVDD=5V, 4Ω load, 10% THD+N)
Supports playback soft-mute, digital volume, digital AVC
Stereo headphone output with on-chip 45mW headphone driver (AVDD=3.3V, 16Ω load)
Supports pop noise suppression with external capacitor
Speaker amplifier power supplies from 2.3V to 5V
Digital power supplies from 1.8V to 3.6V
Analog power and headphone power supplied from 2.3V to 3.6V
Power management and enhanced power saving
Internal PLL can receive wide range of clock input
Supports sampling rate 8KHz~192KHz
Supports I2C control interface
Supports three programmable data interfaces
I2S, left justified, or DSP
16/20/24 bits word length
Master or Slave clock mode
32-pin QFN 5x5mm package for small footprint
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Speaker Amplifier
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Datasheet
3. System Applications
Portable Media Player
MP3 Player
Bluetooth A2DP (Advanced Audio Distribution Profile) Headsets
Portable Navigation Device (PND)
Multimedia Phone
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Speaker Amplifier
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4. Block Diagrams
4.1. Function Block
Figure 1. Block Diagram
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Datasheet
4.2. Audio Mixer Path
Figure 2. Audio Mixer Path
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Speaker Amplifier
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Datasheet
5. Pin Assignments
Figure 3. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3.
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Speaker Amplifier
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6. Pin Descriptions
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name
MCLK
SCLK
SDA
Type
Pin No. Description
Characteristic Definition
I
I
11
17
18
13
12
14
15
16
Main Clock Input
Schmitt trigger input
Schmitt trigger input
Schmitt trigger input/output
Schmitt trigger input/output
Schmitt trigger input/output
Schmitt trigger input
Schmitt trigger input/output
-
I2C: Clock Input
IO
IO
IO
I
I2C: Data Input and Output
Digital Audio Input Frame Sync
Digital Audio Serial Clock
Digital Audio Serial Data Input
General Purpose I/O
LRCK
BCLK
SDAC
GPIO
A1
IO
I
I2C Address A1; Directly Connect to GND
or VDD
6.2. Analog I/O Pins
Table 2. Analog I/O Pins
Description
Name
Type
Pin No
Characteristic Definition
Analog input
LINE_IN_L/JD1
LINE_IN_R/JD2
AUXIN_L
I
I
2
7
Line Input Left Channel/Jack Detect_1
Line Input Right Channel/Jack Detect_2
Aux Input Left Channel
Analog input
I
4
Analog input
AUXIN_R
I
5
Aux Input Right Channel
Analog input
LINE3_L
I
3
LINE3 Input Left Channel
Analog input
LINE3_R
I
6
LINE3 Input Right Channel
Speaker Out Right Channel
Speaker Out Negative Right Channel
Speaker Out Left Channel
Analog input
SPK_OUT_R
SPK_OUT_RN
SPK_OUT_L
SPK_OUT_LN
HP_OUT_R
HP_OUT_L
O
O
O
O
O
O
22
19
25
23
29
31
Speaker amplifier output
Speaker amplifier output
Speaker amplifier output
Speaker amplifier output
Analog amplifier output
Analog amplifier output
Speaker Out Negative Left Channel
Headphone Out Left Channel
Headphone Out Right Channel
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Speaker Amplifier
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Datasheet
6.3. Filter/Reference/Test Pins
Table 3. Filter/Reference Pins
Name
Type
Pin No
Description
Characteristic Definition
VREF
O
27
Reference Voltage Output; Connect
4.7µf Capacitor to Analog GND
Capacitor to analog ground
Cdepop
O
30
Cdepop Capacitor; Connect 1µF
Capacitor to Analog GND
Capacitor to analog ground
6.4. Power & Ground Pins
Table 4. Power/Ground Pins
Name
Type
P
Pin No
9
Description
Characteristic Definition
Digital ground
DGND
Digital GND
DCVDD
DBVDD
SPKGND1
SPKGND2
SPKVDD1
SPKVDD2
AGND
P
8
Digital VDD
Digital power for core
P
10
20
24
21
26
28
32
Digital VDD
Digital power for I/O and PLL
Analog ground for amplifier
Analog ground for amplifier
Analog power for amplifier
Analog power for amplifier
Analog ground for mixer and DACs
Analog power for mixer and DACs
Analog ground for amplifier
P
Speaker Amplifier GND
Speaker Amplifier GND
Speaker Amplifier VDD
Speaker Amplifier VDD
Analog GND
P
P
P
P
AVDD
P
Analog VDD
SPKGND
P
Exposed Pad Speaker Amplifier GND; must be
connected to system DGND
Note1: DBVDD ≥ DCVDD, SPKVDD ≥ AVDD ≥ DCVDD.
Note2: SPDVDD connected to 10µF Capacitor to SPKGND is required.
6.5. Not Connected
Table 5. Not Connected Pins
Name
Type
Pin No
Description
Characteristic Definition
NC
-
1
Not Connected
-
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Speaker Amplifier
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ALC5626
Datasheet
7. Functional Description
7.1. Power
The ALC5626 has many power blocks. The power supply limit conditions are DBVDD ≥ DCVDD and
SPKVDD ≥ AVDD ≥ DCVDD. To prevent pop noise, we suggest you to power on DCVDD before
powering on AVDD.
7.2. Reset
There are two type of reset operation: Power-On-Reset (POR) and Register reset.
Table 6. Reset Operation
Reset Type
Trigger Condition
Codec Response
POR
Monitor Digital Power Supply Voltage Reach VPOR
Reset all hardware logic and all registers to
default values.
Register Reset
Write Reg00
Reset all registers to default values.
7.2.1.
Power-On Reset (POR)
When power is on, DCVDD passes through the VPOR band of the ALC5626 (VPORH~VPORL). A Power-On
Reset (POR) will generate an internal reset signal (POR reset ‘LOW’) to reset the whole chip.
Table 7. Power-On Reset Voltage
Symbol
VPOR_ON
VPOR_OFF
Min
1.0
-
Typical
Max
1.6
-
Unit
V
-
1.3
V
Note: VPOR_OFF must be below VPOR_ON
.
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7.3. Clocking
The ALC5626 audio system clock can be selected from an external MCLK or an internal PLL. No matter
which is used, the ALC5626 requires 256/384*Fs to provide audio SYSCLK.
pllout div ratio
_
_
PLLOUT
BCLK
DIV
sel_dac_filter_clk
sel_i2s_pre_div[2:0]
DIV
PLL
/2
Audio SYSCLK
(256/384Fs)
MCLK
Figure 4. Audio SYSCLK
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz (64Fs of 32KHz)
to 40MHz. Typical choices are 2.048MHz, 4.096MHz, and 13MHz. The source of the PLL can be set to
MCLK or BCLK by setting sel_pll_sour (Reg42[14]). Firmware can setup a PLL to output the desired
frequency as the system clock.
The PLL transmit formula is: FOUT = (MCLK*(N+2)) / ((M+2)*(K+2)) (Typical K=2)
Table 8. PLL Clock Setting Table for 48K (Unit: MHz)
MCLK
2.048
3.6864
4.096
12
M Code
N Code
94
Fvco
98.304
98.304
98.304
98.25
K Code
Fout
24.576
24.576
24.576
24.5625
24.57812
24.576
24.57143
24.5647
24.6
0
1
2
2
2
2
2
2
2
2
2
78
0
46
14
14
3
129
119
30
13
98.3125
98.304
98.28571
98.25882
98.4
15.36
16
5
41
19.2
15
0
85
19.68
8
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Table 9. PLL Clock Setting Table for 44.1K (Unit: MHz)
MCLK
2.048
3.6864
4.096
12
M Code
N Code
86
Fvco
K Code
Fout
0
90.112
2
2
2
2
2
2
2
2
2
22.528
0
47
90.3168
90.48436
90.35294
90.23529
90.35294
90.28571
90.35294
90.29647
22.5792
9
241
126
116
98
22.62109
22.58824
22.55882
22.58824
22.57143
22.58824
22.57412
15
15
15
12
15
15
13
15.36
16
77
19.2
78
19.68
76
7.4. I2C Control Interface
I2C is a 2-wire half-duplex serial communication interface, supporting only slave mode. The host must
support MCLK during register access.
7.4.1.
Addressing Setting
(MSB)
BIT
(LSB)
RW
0
0
1
1
0
0
A1
Note: A1 must be directly connected to VCC or GND.
7.4.2.
Complete Data Transfer
Data Transfer over I2C Control Interface
Figure 5. Data Transfer Over I2C Control Interface
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Write WORD Protocol
Read WORD Protocol
Figure 6. Write WORD Protocol
S: Start Condition
A: 0 for ACK, 1 for NACK
Slave Address: 7-bit Device Address
Wr: 0 for Write Command
Data Byte: 16-bit Mixer data
ꢀ: Master-to-Slave
Rd: 1 for Read Command
ꢀ: Slave-to-Master
Command Code: 8-bit Register Address
Figure 7. Read WORD Protocol
7.4.3.
Odd-Addressed Register Access
The ALC5626 will return ‘0000h’ when odd-addressed and unimplemented registers are read.
7.5. Digital Data Interface
7.5.1.
I2S/PCM Interface
The Digital to Analog Converter (DAC) serial data is input via the SDAC pin. The serial data is shifted in
on the rising edge of BCLK (ctrl_i2s_bclk_polarity=0’b) or the falling edge (ctrl_i2s_bclk_polarity=1’b).
The Left/Right Clock (LRCK) signal is the frame sync signal. Left/Right data can be swapped by
en_dac_lrck_swap.
The ALC5626 I2S/PCM interface can be configured as Master mode or Slave mode. In Master mode
(sel_i2s_mode=0’b), BCLK and LRCK are configured as output. In Slave mode (sel_i2s_mode=1’b),
BCLK and LRCK are configured as input. The MCLK provides BCLK synchronized clock externally as
Stereo System Clock.
The ALC5626 supports three independent I2S/PCM interfaces for Stereo Audio data formats:
• PCM/DSP mode
• Left justified mode
• I2S mode
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Figure 8. PCM Stereo Data Mode A Format-1 (sel_i2s_data_format=10’b, ctrl_i2s_bclk_polarity=0’b)
Figure 9. PCM Stereo Data Mode A Format-2 (sel_i2s_data_format=10’b, ctrl_i2s_bclk_polarity=1’b)
Figure 10. PCM Stereo Data Mode B Format (sel_i2s_data_format=11’b, ctrl_i2s_bclk_polarity=0’b)
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Figure 11. I2S Data Format (sel_i2s_data_format=00’b)
Figure 12. Left-Justified Data Format (sel_i2s_data_format=01’b, ctrl_i2s_bclk_polarity=0’b)
7.6. Analog Signal Path
7.6.1.
Line Input
LINE_IN_L and LINE_IN_R provide 2-channel stereo single-ended inputs that can be mixed into any
analog output mixer. In addition, LINE_IN_L and LINE_IN_R can be configured as mono channel
differential input by en_li_diff, which can only output to the HP mixer.
• LINE_IN_L/R volume and mute are controlled by Reg0A
• sel_li_l_vol and sel_li_r_vol can be used to power down LINE_IN volume control
• LINE_IN_L is pin shared with JD1 and can be configured by sel_jd_source
• LINE_IN_R is pin shared with JD2 and can be configured by sel_jd_source
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7.6.2.
Auxiliary Input
AUXIN_L and AUXIN_R provide 2-channel stereo single-ended input that can be mixed into any analog
output mixer. In addition, AUXIN_L and AUXIN_R can be configured as mono channel differential
input by en_auxi_diff, which can only output to the HP mixer.
• AUXIN_L/R volume and mute are controlled by Reg08
• sel_auxi_l_vol and sel_auxi_r_vol can be used to power down AUXIN_L/R volume control
7.6.3.
LINE3 Input
LINE3_L and LINE3_R provide 2-channel stereo single-ended input that can be mixed into any analog
output mixer.
• LINE3_L/R volume and mute are controlled by Reg0E
• sel_li3_l_vol and sel_li3_r_vol can be used to power down LINE3_L/R volume control
7.6.4.
Speaker Output
SPK_OUT provides two-channel differential output and can be configured to dual single-ended output.
The SPK_OUT source is selected in sel_spk_vol_in as below:
• No Input (VMID
)
• Headphone mixer
• Speaker mixer
The ALC5626 Speaker-out supports Class-AB and Class-D type amplifiers that are configured by
spk_out_sel. As the power voltage of SPKVDD is usually higher than AVDD, it must set Class-AB/D
VMID ratio at spk_ampd_ratio in order to extend the output level.
The SPK_OUT volume and mute are controlled by Reg02. pow_spkl_vol and pow_spkr_vol can be used
to power down Speaker output. pow_clsd is used to power down the Class-AB/D amplifier.
SPK_OUT supports ‘Soft Volume Delay Mute’ and ‘Zero-Crossing Detect’ functions which can be
enabled by en_sp_l_dezero, en_sp_l_softvol, en_sp_r_dezero, and en_sp_r_softvol.
7.6.5.
Headphone Output
HP_OUT_L/R provides 2-channel single-ended output. The source of HP_OUT_L/R can be selected
from sel_hp_l_in & sel_hp_r_in as below.
• VMID
• Headphone mixer
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The HP_OUT_L/R volume and mute are controlled by Reg04, and pow_hp_l_vol and pow_hp_r_vol can
be used to power down the HP output volume.
HP_OUT supports ‘Soft Volume Delay Mute’ and ‘Zero-Crossing Detect’ functions which can be
enabled by en_hp_l_dezero, en_hp_l_softvol, en_hp_r_dezero, and en_hp_r_softvol.
HP_OUT_L/R source can be selected from DAC Stereo output (en_dac_hp) for high quality performance
playback.
7.6.6.
Stereo DAC
The stereo DAC can be configured to different sample rates by driving 256Fs/384Fs into audio SYSCLK,
and individually set by sel_i2s_bclk_ms.
sel_dac_l_vol & sel_dac_r_vol can be used to control the DAC output volume.
7.6.7.
Headphone Mixer
The headphone (HP) mixer is used to drive stereo output, including HP_OUT_L/R, SPK_OUT_L/LN,
and SPK_OUT_R/RN.
The following signals can be mixed into the headphone mixer:
• LINE_IN_L/R (controlled by Reg0A)
• AUXIN_L/R (controlled by Reg08)
• LINE3_L/R (controlled by Reg0E)
• Stereo DAC output (controlled by Reg0C)
When the SPK_OUT source is from HP mixer, SPK_OUT_L/LN can be configured to stereo
single-ended or mono differential output by setting spkon_source. The headphone mixer can be powered
down by setting pow_hp_l_vol & pow_hp_r_vol.
7.6.8.
Speaker Mixer
The speaker (SPK) mixer is used to drive SPK_OUT and HP_OUT. The stereo output (HP_OUT_L/R) of
the SPK mixer has the same signal on both channels.
The following signals can be mixed into the speaker mixer:
• LINE_IN_L/R (controlled by Reg0A)
• AUXIN_L/R (controlled by Reg08)
• LINE3_L/R (controlled by Reg0E)
• Stereo DAC output (controlled by Reg0C)
Note: The speaker mixer can be powered down by setting pow_mix_spk.
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7.7. Power Management
The ALC5626 supports detailed Power Management control registers within Reg3A, 3C, and 3E. Each
particular block will be active only when individual bits of Reg3A, 3C, and 3E are set to ‘Enable’.
7.8. GPIO and Jack Detect (JD) Function
7.8.1.
GPIO Interface
The ALC5626 supports one GPIO that can be configured as Input/Output by sel_gpio_io. When GPIO is
configured as Input, the status will be indicated in status_gpio_in. When GPIO is configured as Output,
sel_gpio_o_logic is used to drive GPIO to High (1’b) or Low (0’b), and the status can be read in
status_gpio_in.
GPIO input polarity can be changed by setting sel_polarity_gpio, and setting Reg48 in order to generate
the interrupt (IRQ).
The ALC5626 supports Jack Detect (JD1/JD2/GPIO) to switch ON/OFF the Analog Output (Headphone
Out and Speaker Out) and Mute (VMID). JD1 and JD2 can be pin-shared from LINE_IN_L/R, and are
used to enable specified Analog Output configured in the Reg5A Jack Detect Control Register.
In addition, GPIO can be configured to PLLOUT or IRQ_Output by setting Reg4A.
7.8.2.
Interrupt
Independent of GPIOs, some Internal Event Signals (over-temperature or over-current) are handled the
same as GPIO input, and can be treated as Interrupt sources. The application of an Internal Event Signal
is the same as GPIO.
7.9. Headphone Depop
The ALC5626 provides a headphone depop mechanism in order to eliminate the pop noise of headphone
out. An external 1µF capacitor is required to connect Cdepop and AGND in this application. See the
separate ALC5626 Application Notes for details.
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7.10. AVC Control
The Automatic Volume Control (AVC) function dynamically adjusts the input signal quantized by the
DAC to an expected sound level by setting THmax and THmin.
When the average level of input signal quantized by the DAC is higher than THmax, the AVC will
decrease the selected analog gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a
lower amplitude than THmax. When the average level of input signal quantized by DAC is lower than
THmin, the AVC will increase the selected analog gain to amplify the input signal. The quantized PCM
signal is then set to a higher amplitude than THmin. The quantized PCM has an average level between
THmin and THmax.
In order to avoid outputting a strong amplified signal when the gain detector input level is transiting from
a very small signal to a normal signal, the AVC block will limit the selected analog gain to unit gain
(=0dB) when the input level of the gain detector is lower than THnonact.
Figure 13. AVC Block of DAC Module
Figure 14. AVC Behavior
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7.11. Zero Cross
When Zero-Cross detect is enabled, the ALC5626 will change each output volume or mute only if the
signal swing crosses the zero point. This function can avoid pop noise when volume is changed or muted.
Figure 15. Zero Cross Disabled when Output Muted
Figure 16. Zero Cross Enabled when Output Muted
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8. Register Descriptions
8.1. Reg-02h: Speaker Output Volume
Default: 8080’h
Table 10. MX02 Speaker Output Volume
Name
Bits
RW Default Description
mute_sp_l
15
RW
1’h
0’h
Mute SPK Left Output
0: On
1: Mute (-∞ dB)
Reserved
14:13
12:8
7
R
Reserved
sel_sp_l_vol
mute_sp_r
RW
RW
00’h SPK Left Output Volume (SPKL[4:0]) in 1.5dB Steps
1’h
Mute SPK Right Output
0: On
1: Mute (-∞ dB)
Reserved
6:5
4:0
R
0’h
Reserved
sel_sp_r_vol
RW
00’h SPK Right Output Volume (SPKR[4:0]) in 1.5dB Steps
Note: For SPKR/SPKL: 00h: 0dB attenuation.
1Fh: 46.5dB attenuation.
8.2. Reg-04h: Headphone Output Volume
Default: C080’h
Table 11. MX04 Headphone Output Volume
Name
Bits
RW
Default Description
mute_hp_l
15
RW
1’h
Mute Left Headphone Amp Control
0: On
1: Mute Left Channel (-∞ dB)
Reserved
14:13
12:8
7
RW
RW
RW
01’h
00’h
1’h
Reserved
sel_hp_l_vol
mute_hp_r
Headphone Output Left Volume (HPL[4:0]) in 1.5dB Steps
Mute Right Headphone Amp Control
0: On
1: Mute Left Channel (-∞ dB)
Reserved
6:5
4:0
R
0’h
Reserved
sel_hp_r_vol
RW
00’h
Headphone Output Right Volume (HPR[4:0]) in 1.5dB Steps
Note: For HPR/HPL: 00h: 0dB attenuation.
1Fh: 46.5dB attenuation.
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8.3. Reg-08: Auxiliary Input Volume
Default: C8C8’h
Table 12. MX08 Auxiliary Input Volume
RW Default Description
Name
Bits
mute_auxil2hp
15
RW
1’h
Mute AUXIN Left Volume Output to Headphone Left Mixer Control
0: On 1: Mute
Mute AUXIN Left Volume Output to Speaker Mixer Control
mute_auxil2spk
14
RW
1’h
0: On
1: Mute
Reserved
13
12:8
7
R
0’h
08’h
1’h
Reserved
sel_auxi_l_vol
mute_auxir2hp
RW
RW
AUXIN Left Volume (AUXLV [4:0]) in 1.5dB Steps
Mute AUXIN Right Volume Output to Headphone Right Mixer
Control*
0: On
Mute AUXIN Right Volume Output to Speaker Mixer Control*
0: On 1: Mute
1: Mute
mute_auxir2spk
en_auxi_diff
6
5
RW
RW
1’h
0’h
AUXIN Differential Input Control
0: Disable
1: Enable. Only output to HP right mixer
AUXIN Right Volume (AUXIRV [4:0]) in 1.5dB Steps*
Note: For AUXIRV/AUXI LV: 00h: +12dB gain.
08h: 0dB attenuation.
sel_auxi_r_vol
4:0
RW
8’h
1Fh: 34.5dB attenuation.
Note: ‘*’indicates no function when Reg-08[5] = 1’b.
8.4. Reg-0A: Line Input Volume
Default: C8C8’h
Table 13. MX0A Line Input Volume
Default Description
Name
Bits
RW
mute_lil2hp
15
RW
1’h
Mute Left Volume Output to Headphone Left Mixer Control
0: On 1: Mute
Mute Left Volume Output to Speaker Mixer Control
mute_lil2spk
14
RW
1’h
0: On
1: Mute
Reserved
13
12:8
7
R
0’h
08’h
1’h
Reserved
sel_li_l_vol
mute_lir2hp
RW
RW
Line-In Left Volume (NLV[4:0]) in 1.5dB Steps
Mute Right Volume Output to Headphone Right Mixer Control*
0: On
Mute Right Volume Output to Speaker Mixer Control*
0: On 1: Mute
1: Mute
mute_lir2spk
6
RW
1’h
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Name
Bits
RW
Default Description
en_li_diff
5
RW
0’h
Line-In Differential Input Control
0: Disable
1: Enable. Only output to HP left mixer
Line-In Right Volume (NRV[4:0]) in 1.5dB Steps*
Note: For NRV/NLV: 00h: +12dB gain.
08h: 0dB attenuation.
sel_li_r_vol
4:0
RW
08’h
1Fh: 34.5dB attenuation.
Note: ‘*’indicates no function when Reg-0A[5] = 1’b.
8.5. Reg-0C: Stereo DAC Digital Volume
Default: D0D0’h
Table 14. MX0C Stereo DAC Digital Volume
Name
Bits
RW
Default Description
mute_dacl2hp
15
RW
1’h
Mute DAC Left Channel Digital Volume Output to Headphone Left
Mixer Control
0: On
1: Mute (-∞ dB)
mute_dacl2spk
14
RW
1’h
Mute DAC Left Channel Digital Volume Output to Speaker Mixer
Control
0: On
1: Mute (-∞ dB)
set_dac_l_vol
mute_dacr2hp
13:8
7
RW
RW
10’h
1’h
DAC Left Channel Digital Volume (PLV[5:0]) in 0.75dB Steps
Mute DAC Right Channel Digital Volume Output to Headphone
Right Mixer Control
0: On
1: Mute (-∞ dB)
mute_dacr2spk
Sel_dac_r_vol
6
RW
RW
1’h
Mute DAC Right Channel Digital Volume Output to Speaker Mixer
Control
0: On
1: Mute (-∞ dB)
5:0
10’h
DAC Right Channel Digital Volume (PRV[5:0]) in 0.75dB Steps
Note: For PRV/PLV: 00h: +12dB gain.
10h: 0dB attenuation.
3Fh: 35.25.5dB attenuation.
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8.6. Reg-0E: LINE3 Volume
Default: C8C8’h
Table 15. MX0E LINE3 Volume
Default Description
Name
Bits
RW
mute_li3l2hp
15
RW
1’b
Mute LINE3 Left Volume Output to Headphone Left Mixer Control
0: On 1: Mute
Mute LINE3 Left Volume Output to Speaker Mixer Control
mute_li3l2spk
14
RW
1’b
0: On
1: Mute
reserved
13
12:8
7
R
0’h
08’h
1’b
Reserved
sel_li3_l_vol
mute_li3r2hp
RW
RW
LINE_IN3 Left Volume (NL3V[4:0]) in 1.5dB Steps
Mute LINE3 Right Volume Output to Headphone Right Mixer
Control
0: On
1: Mute
mute_li3r2spk
6
RW
1’b
Mute LINE3 Right Volume Output to Speaker Mixer Control
0: On
1: Mute
reserved
5
R
0’h
Reserved
sel_li3_r_vol
4:0
RW
08’h
LINE_IN3 Right Volume (NR3V[4:0]) in 1.5dB Steps
For NL3V/NR3V: 00h: +12dB gain
08h: 0dB attenuation
1Fh: 34.5dB attenuation
8.7. Reg-16h: Soft Delay Volume Control Time
Default: 0009’h
Table 16. MX16 Soft Delay Volume Control Time
Name
Bits
15:4
3:0
RW
R
Default Description
0’h Reserved
1001’b Soft Volume Change Delay Time (Default=1001b)
Reserved
sel_sync_softvol
RW
0000: 1 SVSYNC
0010: 4 SVSYNC
0100: 16 SVSYNC
0110: 64 SVSYNC
1000: 256 SVSYNC
1010: 1024 SVSYNC
0001: 2 SVSYNC
0011: 8 SVSYNC
0101: 32 SVSYNC
0111: 128 SVSYNC
1001: 512 SVSYNC
Others: Reserved
Note: SVSYNC=1/Fs, Step: -1.5dBFS.
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8.8. Reg-1Ch: Output Mixer Control
Default: C000’h
Table 17. MX1C Output Mixer Control
Default Description
2’h
Name
Bits
RW
spkon_source
15:14
RW
Reg1C
[15:14]
Any Mixer to SPKOUT
SPK_OUT_L SPK_OUT_LN
Vol. Control
Vol. Control
Register
Config
Config
Register
00'b
01'b
VOL_LP Reg02[15:8] VOL_RN
VOL_LP Reg02[15:8] VOL_RP
Reg02[7:0]
Reg02[7:0]
10'b
11'b
VOL_LP Reg02[15:8] VOL_LN Reg02[15:8]
MUTE MUTE MUTE MUTE
Note: SPK_OUT_R dedicates VOL_RP, and SPK_OUT_RN
dedicates VOL_RN.
spk_out_sel
13
RW
1’h
SPKL and SPKR Output Select
0: Class-AB
Reserved
1: Class-D
Reserved
12
R
0’h
sel_spk_vol_in
11:10
RW
00’h
SPK Volume Output Source Select
00: VMID (No input)
10: Speaker mixer (diff out)
01: HP Mixer
11: Reserved
sel_hp_l_in
sel_hp_r_in
9
8
RW
RW
0’h
0’h
HPL Volume Output Source Select
0: VMID (No input)
1: HP Left Mixer
HPR Volume Output Source Select
0: VMID (No input)
1: HP Right Mixer
Reserved
7:2
1
R
0’b
0’b
Reserved
en_dac_hp
RW
DAC Direct Output to HP Amplifier Control
0: Normal
Reserved
1: Enable direct output
Reserved
0
R
0’b
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8.9. Reg-34h: Stereo Audio Serial Data Port Control
Default: 8000’h
Table 18. MX34 Stereo Audio Serial Data Port Control
Name
Bits
RW
Default Description
sel_i2s_mode
15
RW
1’h
Main Serial Data Port Mode Selection
0: Master
Reserved
1: Slave
Reserved
14:8
7
R
0’h
0’h
ctrl_i2s_bclk_polarity
RW
Stereo I2S BCLK Polarity Control
0: Normal
1: Invert
Reserved
6:5
4
R
0’h
0’h
Reserved
en_dac_lrck_swap
RW
DAC Data L/R Swap
0: DAC data appear at left phase of LRCK
1: DAC data appear at right phase of LRCK
Note: Supports I2S and PCM.
sel_i2s_data_len
3:2
1:0
RW
RW
0’h
0’h
Data Length Selection
00: 16 bits
10: 24 bits
01: 20 bits
11: Reserved
sel_i2s_data_format
Stereo PCM Data Format Selection
00: I2S format
01: Left justified
10: PCM Mode A (LRCK One Plus at Master Mode)
11: PCM Mode B (LRCK One Plus at Master Mode)
8.10. Reg-38h: Stereo DAC Clock Control
Default: 2000’h
Table 19. MX38 Stereo DAC Clock Control
Name
Bits
RW
Default Description
sel_i2s_pre_div
15:13
RW
1’h
I2S Pre-Divider
000b: ÷1
001b: ÷2
100b: ÷16
010b: ÷4
101b: ÷32
011b: ÷8
Others: Reserved
sel_i2s_bclk_ms
12
RW
0’b
Master Mode Clock Relative of BCLK and LRCK
0b: 32bits (64FS)
Reserved
1b: 16bits (32FS)
Reserved
11:3
2
R
0’h
0’b
sel_dac_filter_clk
RW
Stereo DAC Filter Clock Select
0b: 256Fs
Reserved
1b: 384Fs
Reserved
1:0
R
0’h
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
25
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.11. Reg-3Ah: Power Management Addition 1
Default: 0000’h
Table 20. MX3A Power Management Addition 1
Name
Bits
RW
Default Description
en_main_i2s
15
RW
0’h
I2S Digital Interface Enable
0: Disable 1: Enable
All Zero Cross Detect Power Down (Includes Digital)
pow_zcd
14
RW
0’h
0: Disable
1: Enable
Reserved
13:9
8
R
0’h
0’b
Reserved
pow_softgen
RW
Power on Softgen
1: Power on
0: Power down
Note: When pow_softgen =1, whether HP and AUXAmp can be
driven depends on the level on Cdepop (depends on depop mode
selection)
Reserved
7:6
5
R
0’h
0’h
Reserved
en_hp_out_amp
RW
1: Enable HP Output buffer for normal loading (used to drive High
Impedance)
0: Disable (DEPOP mode)
See Table 21 for details.
en_hp_enhance_amp
Reserved
4
RW
R
0’h
0’h
1: Enable HP Enhance Output buffer
0: Disable (DEPOP mode or normal loading mode)
See Table 21 for details.
3:0
Reserved
The following table describes Bit 4 & Bit 5:
Table 21. Headphone Drive Ability Selection
en_hp_enhance_amp Description
en_hp_out_amp
0’b
0’b
1’b
1’b
0’b
1’b
0’b
1’b
HP Output Off
Not Used
HP Output for High-Impedance Loading (>Kohm)
HP Output for Low-Impedance Loading (<Kohm)
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
26
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.12. Reg-3Ch: Power Management Addition 2
Default: 0000’h
Table 22. MX3C Power Management Addition 2
Name
Bits
RW
Default Description
pow_clsab
15
RW
0’b
0’b
0’h
0: Disable
1: Enable speaker amplifier Class-AB power
0: Disable
1: Enable speaker amplifier Class-D power
0: Disable
pow_clsd
pow_vref
14
13
RW
RW
1: Enable VREF for all analog circuits (passes control to Vref
pin)
pow_pll
12
11
10
9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0’h
0: Disable
1: Enable PLL
pow_thermal
pow_dac_ref
0: Disable
1: Enable thermal shutdown (temp sensor)
0: Disable
1: Enable DAC reference circuit (Vref+/Vref-)
pow_dac_l
0: Disable
1: Enable left STEREO DAC and its filter clock
pow_dac_r
8
0: Disable
1: Enable right STEREO DAC and its filter clock
pow_dacl2mixer_direct
pow_dacr2mixer_direct
pow_mix_hp_l
pow_mix_hp_r
pow_mix_spk
Reserved
7
0: Disable
1: Enable left DAC to mixer and direct path power
6
0: Disable
1: Enable Right DAC to mixer and direct path power
5
0: Disable
1: Enable left headphone mixer
0: Disable
1: Enable right headphone mixer
0: Disable
1: Enable Speaker mixer
Reserved
4
3
2:0
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.13. Reg-3Eh: Power Management Addition 3
Default: 0000’h
Table 23. MX3E Power Management Addition 3
Name
Bits
15
RW
RW
R
Default Description
pow_main_bias
Reserved
0’h
0’h
0’h
0’b
0’h
0: Disable
Reserved
0: Disable
0: Disable
0: Disable
1: Enable Main bias of analog circuit
14:13
12
pow_spkl_vol
pow_spkr_vol
pow_hp_l_vol
RW
RW
RW
1: Enable SPK_OUT Left Channel output
1: Enable SPK_OUT right channel output
11
10
1: Enable HP_OUT_L Volume control & HP_L Amplifier
pow_hp_r_vol
9
RW
0’h
0: Disable
1: Enable HP_OUT_R Volume control & HP_R Amplifier
Reserved
8
7
RW
RW
RW
RW
RW
RW
RW
R
0’b
0’h
0’h
0’h
0’h
0’b
0’b
0’h
Reserved (Must be set to 0’b)
pow_li_l_vol
pow_li_r_vol
pow_auxin_l_vol
pow_auxin_r_vol
pow_li3_l_vol
pow_li3_r_vol
Reserved
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
0: Disable
Reserved
1: Enable LINE_IN Left Volume control
1: Enable LINE_IN Right Volume control
1: Enable AUXIN Left Volume control
1: Enable AUXIN Right Volume control
1: Enable LINE_IN3 Left Volume control
1: Enable LINE_IN3 Right Volume control
6
5
4
3
2
3:0
8.14. Reg-40h: General Purpose Control
Default: 0100’h
Table 24. MX40 General Purpose Control
Name
Bits
15:13
12
RW
R
Default Description
Reserved
clsab_amp_sel
0’h
0’b
Reserved
RW
Class-AB Amplifier Low Voltage Control
0: Normal
1: SPKVDD < 3.3V
Note: This register works only when Class-AB is selected.
spk_ampd_ratio
11:9
RW
0’h
Speaker Class-AB/D Amplifier VMID Ratio Control (Output Gain
Control)
000: 2.25Vdd
010: 1.75Vdd
100: 1.25Vdd
001: 2.00Vdd
011: 1.5Vdd
101: 1Vdd
Others: Not allowed
en_dac_hpf
Reserved
8
RW
R
1’h
0’h
STEREO DAC High-Pass Filter
0: Disable
Reserved
1: Enable
7:0
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
28
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.15. Reg-42h: Global Clock Control
Default: 0000’h
Table 25. MX42 Global Clock Control
Default Description
0’h Clock Source MUX Control
Name
Bits
RW
sel_sysclk
15
RW
0: MCLK
1: PLL
sel_pll_sour
14
13
RW
RW
0’h
0’b
PLL Source Select
0: From MCLK
1: From BIT_CLK
se_btlb_clsab
Single End & BTL of Class-AB Selection
0: Differential Mode 1: Single-End Mode
Note: This register works only when Class-AB is selected.
Reserved
Reserved
12:3
2:1
R
0’h
0’b
sel_pllout_div_ratio
RW
PLL Output Division Ratio
PLL Output to GPIO Divider
00: ÷1
10: ÷4
01: ÷2
11: ÷8
sel_pll_pre_div
0
RW
0’b
PLL Pre-Divider
0b: ÷1
1b: ÷2
Reg42[2:1]
DIV
PLLOUT
BCLK
Audio SYSCLK
I2S Clock Tree
PLL
/2
MCLK
PLL & Clock Tree
Figure 17. Global Clock Control
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
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Datasheet
8.16. Reg-44h: PLL M/N Code Control
Default: 0000’h
Table 26. MX44 PLL M/N Code Control
Bits RW Default Description
Name
sel_pll_n_code
15:8 RW
00’h
N[7:0] Code for Analog PLL
00000000: Div 2
……………
00000001: Div 3
11111111: Div 257
1b: Bypass
sel_pll_m_bypass
sel_pll_k_code
7
RW
RW
0’h
0’h
Bypass PLL M
0b: No bypass
6:4
K[2:0] Code for Analog PLL
000: Div 2
…………...
001: Div 3
111: Div 9
sel_pll_m_code
3:0
RW
0’h
M[3:0] Code for Analog PLL
0000: Div 2
……………
0001: Div 3
1111: Div 17
8.17. Reg-48h: Internal Status and IRQ Control
Default: 0000’h
Table 27. MX48 Internal Status and IRQ Control
Name
Bits RW Default Description
en_irq_over_curr
15
14
13
RW
RW
RW
0’h
0’h
0’h
IRQ Output Source Configuration of Over-Current Status
0: Bypass 1: Normal
IRQ Output Source Configuration of Over-Temperature Status
0: Bypass 1: Normal
IRQ Output Source Configuration of Jack Detection Status
en_irq_over_temp
en_irq_jd_conf
0: Bypass
Reserved
1: Normal
Reserved
12:6
5
R
0’h
0’h
sel_polarity_over_temp
RW
Over-Temperature Sensor Status Polarity
0: Normal 1: Output Invert
status_over_temp
4
R
0’h
Over-Temperature Sensor Status
Read: Return status of each status pin
Reserved
Reserved
3:2
1
R
0’h
0’h
sel_polarity_over_curr
RW
Speaker Amplifier Over Current Status Polarity
0: Normal
1: Output Invert
status_over_curr
0
R
0’h
Speaker Amplifier Over Current Status
Read: Return status of each status pin
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
30
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.18. Reg-4Ah: GPIO Control
Default: 0000’h
Table 28. MX4A GPIO Control
Default Description
Name
Bits
RW
sel_gpio_o_conf
15:14
RW
0’h
GPIO Output Pin Select
00b: Logic Output (GPIO_out_logic)
10b: Reserved
01b: IRQ
11b: PLLOUT
Reserved
13:4
3
R
0’h
0’h
Reserved
sel_gpio_io
RW
GPIO Pin Configuration
0: Output
1: Input
sel_gpio_o_logic
sel_polarity_gpio
status_gpio_in
2
1
0
RW
RW
R
0’h
0’h
0’h
GPIO Output Pin Control
0: Drive Low
1: Drive High
1: Output Invert
GPIO Pin Polarity
0: Normal
GPIO Pin Status
Read: Return status of each GPIO pin
8.19. Reg-5Ah: Jack Detect Control
Default: 0004’h
Table 29. MX5A Jack Detect Control
RW Default Description
0’h
Jack Detect Select
Name
Bits
SEL_JD_SOURCE
15:14
RW
00: OFF
01: GPIO
10: JD1 and enable Line in Left Ch. pin share
11: JD2 and enable Line in Right Ch. pin share
Enable ZCD
(Power & Enable)
for Mute
Reg5A
[15:14]
lineinl_pin
_sharing
lineinr_pin
_sharing
00'b
01'b
10'b
11'b
0'b
0'b
1'b
0'b
0'b
0'b
0'b
1'b
FALSE
TRUE
TRUE
TRUE
en_jd_vref
13
12
11
10
RW
RW
RW
RW
0’b
0’b
0’h
0’h
Enable Jack Detect Trigger Vref
0: Disable
1: Enable
polarity_jd_tri_vref
en_jd_hpout
Selected Jack Detect Polarity Trigger Vref
0: Low trigger
Enable Jack Detect Trigger HPOUT
0: Disable 1: Enable
Select Jack Detect Polarity Trigger HPOUT
1: High trigger
polarity_jd_tri_hpout
0: Low trigger
1: High trigger
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
Name
Bits
RW
Default Description
en_jd_spkoutl
9
RW
0’h
0’h
0’b
0’b
Enable Jack Detect Trigger SPK_OUT_L/LN
0: Disable 1: Enable
Select Jack Detect Polarity Trigger SPK_OUT_L/LN
0: Low trigger 1: High trigger
Enable Jack Detect Trigger SPK_OUT_R/RN
0: Disable 1: Enable
Select Jack Detect Polarity Trigger SPK_OUT_R/RN
polarity_jd_tri_spkout
en_jd_spkoutr
8
7
6
RW
RW
RW
polarity_jd_tri_spkoutr
0: Low trigger
Reserved
1: High trigger
Reserved
5:3
2
R
R
0’b
0’h
status_jd_internal
Jack Detect Status
Read: Return status of Jack Detect Select output
Reserved
Reserved
1:0
R
0’b
8.20. Reg-5Ch: MISC1 Control
Default: 0000’h
Table 30. MX5C MISC1 Control
Bits RW Default Description
Name
en_sp_l_dezero
15
RW
0’h
SPK Left Volume Zero Cross Detector Control
(SPK Left Volume Zero Cross Detector when Reg1C[15:14] = 01’b)
0: Disable 1: Enable
en_sp_l_softvol
14
RW
0’h
SPK Left Soft Volume Change Enable
(SPK Left Soft Volume Change Enable when Reg1C[15:14] = 01’b)
0: Disable
1: Enable
en_sp_r_dezero
en_sp_r_softvol
en_hp_l_dezero
en_hp_l_softvol
en_hp_r_dezero
en_hp_r_softvol
13
12
11
10
9
RW
RW
RW
RW
RW
RW
0’h
0’h
0’h
0’h
SPK Right Zero Cross Detector
0: Disable
1: Enable
SPK Right Soft Volume Change Enable
0: Disable
1: Enable
HP Out Left Zero Cross Detector Control
0: Disable
HP Out Left Soft Volume Change Control
0: Disable 1: Enable
HP Out Right Zero Cross Detector Control
0: Disable 1: Enable
HP Out Right Soft Volume Control
1: Enable
0’h
0’h
8
0: Disable
1: Enable
Reserved
7:4
3
R
0’h
0’b
Reserved
en_dac_zc
RW
Enable DAC Digital Volume Zero Crossing Detect
0: Disable
1: Enable
en_dac_soft_vol
2
RW
0’b
Enable DAC Digital Soft Volume
0: Disable
Reserved
1: Enable
Reserved
1:0
R
0’h
Note: When zero cross detector is enabled, change mute volume only on zero crossing or after timeout.
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.21. Reg-5Eh: MISC2 Control
Default: 0000’h
Table 31. MX5E MISC2 Control
Default Description
Name
Bits
RW
en_vref_fastb
15
RW
0’b
Enable Fast Vref (This Bit must be Disabled in Normal Use)
0: Enable fast Vref
Thermal Shut Down Enable
0: Disable
1: Disable fast Vref
en_thermal_shutdown
14
RW
0’b
1: Enable
Reserved
13:10
9
R
0’h
0’b
Reserved
en_dp2_hp
RW
Enable De-Pop Mode 2 of HP_Out
0: Disable
1: Enable
en_dp1_hp
en_smt_hp_l
en_smt_hp_r
smt_trig
8
7
6
5
RW
RW
RW
RW
0’h
0’b
0’b
0’b
Enable De-Pop Mode 1 of HP_Out
0: Disable
1: Enable
Enable HP_L Mute-Unmute Depop
0: Disable
Enable HP_R Mute-Unmute Depop
0: Disable 1: Enable
Enable Mute-Unmute Depop
1: Enable
0: Disable
1: Enable
Reserved
4
3
R
0’b
0’h
Reserved
mute_dac_l
RW
Mute Main DAC Left Input
0: On
1: Mute (-∞ dB)
mute_dac_r
Reserved
2
RW
R
0’h
0’h
Mute Main DAC Right Input
0: On
1: Mute (-∞ dB)
1:0
Reserved
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.22. Reg-66h: EQ Control
Default: 0000’h
Table 32. MX66 EQ Control
Bits RW Default Description
Name
eq_all_en
15
RW
0’b
EQ Block Control
0b: Disable
1b: Enable
eq_hpf_mode
14
RW
0’b
EQ High-Pass Shelving Filter Mode Control
0b: High-pass shelving filter
Reserved
1b: -20dB/decade (HPF)
Reserved
13
12
R
R
0’h
0’b
eq_hpf_status
EQ High-Pass Filter (HPF) Status
0: Normal
1: Overflow
This bit is set if an overflow has occurred. Write 1 to clear it.
EQ Band-3 (BP3) Status
eq_bpf3_status
eq_bpf2_status
eq_bpf1_status
eq_lpf_status
11
10
9
R
R
0’b
0’b
0’b
0’b
0’b
0: Normal
1: Overflow
This bit is set if an overflow has occurred. Write 1 to clear it.
EQ Band-2 (BP2) Status
0: Normal
1: Overflow
This bit is set if an overflow has occurred. Write 1 to clear it.
EQ Band-1 (BP1) Status
R
0: Normal
1: Overflow
This bit is set if an overflow has occurred. Write 1 to clear it.
EQ Low-Pass Filter (LPF) Status
8
R
0: Normal
1: Overflow
This bit is set if an overflow has occurred. Write 1 to clear it.
EQ Parameter Update Control
eq_para_update
7
RW
0b: No action
1b: Update parameter
Reserved
6:5
4
R
0’h
0’b
Reserved
eq_hpf_en
RW
EQ High-Pass Filter (HPF) Control
0: Disable (bypass) and reset
EQ Band-3 (BP3) Control
0: Disable and reset
1: Enable
1: Enable
1: Enable
1: Enable
1: Enable
eq_bpf3_en
eq_bpf2_en
eq_bpf1_en
eq_lpf_en
3
2
1
0
RW
RW
RW
RW
0’b
0’b
0’b
0’b
EQ Band-2 (BP2) Control
0: Disable and reset
EQ Band-1 (BP1) Control
0: Disable and reset
EQ Low-Pass Filter (LPF) Control
0: Disable and reset
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.23. Reg-68h: AVC Control
Default: 1009’h
Table 33. MX68 AVC Control
Bits RW Default Description
Name
EN_AVC
15
14
13
RW
RW
RW
0’b
0’b
0’b
AVC Enable (Default: 00b)
0: Disable AVC
1: Enable AVC to control Digital gain
sel_avc_ref_ch
AVC Reference Channel Selection
0: Left Channel
1: Right Channel
sel_nonact_action
Gain Action of Non-active Region
0: Keep previous Gain
Reserved
1: Unit Gain
Reserved
12:5
4:0
R
80’h
09’h
sel_monitor_window
RW
Monitor Window Control (Unit: 2^(n+1) Samples) (Default: 01011b)
00000b: 2^(1) samples
00010b: 2^(3) samples
10000b: 2^(17) samples
00001b: 2^(2) samples
………
Others: Reserved
(Maximum=10000000000000000=2^17)
8.24. Reg-6Ah: Private Register Index
Default: 0000’h
Table 34. MX6A Private Register Index
Default Description
0’h Reserved
0’h Private Register Index
Name
Bits
15:7
6:0
RW
R
Reserved
private_reg_index
RW
8.25. Reg-6Ch: Private Register Data
Default: 0000’h
Table 35. MX6C Private Register Data
Default Description
0’h Private Register Data Port
Name
Bits
RW
private_reg_data
15:0
RW
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.26. Private-00h: EQ Band-0 Coefficient (LP0: a1)
Default: 0000h
Table 36. PR00h: EQ Band-0 Coefficient (LP0: a1)
Bit
Type Function
RW 2’s complement in 3.13 formats (The range is from -4~3.99; the a1 should be in -2~1.99)
15:0
Note: For low-pass filter for Bass control – LP0 has filter coefficient a1 and gain Ho must be set (see Table 37).
8.27. Private-01h: EQ Band-0 Gain (LP0: Ho)
Default: 0000h
Table 37. PR01h: EQ Band-0 Gain (LP0: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the Ho should be in -4~3.99)
15:0
8.28. Private-02h: EQ Band-1 Coefficient (BP1: a1)
Default: 0000h
Table 38. PR02h: EQ Band-1 Coefficient (BP1: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a1 should be in -2~1.99)
15:0
8.29. Private-03h: EQ Band-1 Coefficient (BP1: a2)
Default: 0000h
Table 39. PR03h: EQ Band-1 Coefficient (BP1: a2)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a1 should be in -2~1.99)
15:0
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
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Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.30. Private-04h: EQ Band-1 Gain (BP1: Ho)
Default: 0000h
Table 40. PR04h: EQ Band-1 Gain (BP1: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the Ho should be in -4~3.99)
15:0
8.31. Private-05h: EQ Band-2 Coefficient (BP2: a1)
Default: 0000h
Table 41. PR05h: EQ Band-2 Coefficient (BP2: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a1 should be in -2~1.99)
15:0
8.32. Private-06h: EQ Band-2 Coefficient (BP2: a2)
Default: 0000h
Table 42. PR06h: EQ Band-2 Coefficient (BP2: a2)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a2 should be in -2~1.99)
15:0
8.33. Private-07h: EQ Band-2 Gain (BP2: Ho)
Default: 0000h
Table 43. PR07h: EQ Band-2 Gain (BP2: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the Ho should be in -4~3.99)
15:0
8.34. Private-08h: EQ Band-3 Coefficient (BP3: a1)
Default: 0000h
Table 44. PR08h: EQ Band-3 Coefficient (BP3: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a1 should be in -2~1.99)
15:0
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
37
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.35. Private-09h: EQ Band-3 Coefficient (BP3: a2)
Default: 0000h
Table 45. PR09h: EQ Band-3 Coefficient (BP3: a2)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a2 should be in -2~1.99)
15:0
8.36. Private-0Ah: EQ Band-3 Gain (BP3: Ho)
Default: 0000h
Table 46. PR0Ah: EQ Band-3 Gain (BP3: Ho)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the Ho should be in -4~3.99)
15:0
8.37. Private-0Bh: EQ Band-4 Coefficient (HPF: a1)
Default: 0000h
Table 47. PR0Bh: EQ Band-4 Coefficient (HPF: a1)
Bit
Type Function
RW 2’s complement in 3.13 format (The range is from -4~3.99; the a1 should be in -2~1.99)
15:0
8.38. Private-0Ch: EQ Band-4 Gain (HPF: Ho)
Default: 0000h
Table 48. PR0Ch: EQ Band-4 Gain (HPF: Ho)
Bit
Type
Function
2’s complement in 3.13 format (The range is from -4~3.99; the Ho should be in -2~1.99)
15:0
RW
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
38
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.39. Private-11h: EQ Input Volume Control
Default: 0000h
Table 49. PR11h: EQ Input Volume Control
Bit
15:2
1:0
Type
-
Function
Reserved
RW
7-Bit Volume Unsigned Ratio EQIn-VOL-LR
00b: 0dB
01b: -6dB
10b: -12dB
11b: -18dB
8.40. Private-12h: EQ Output Volume Control
Default: 0001h
Table 50. PR12h: EQ Output Volume Control
Bit
15:3
2:0
Type
-
Function
Reserved
RW
7-Bit Volume Unsigned Ratio EQOut-VOL-LR
000b: -3dB
100b: 9dB
001b: 0dB
101b: 12dB
010b: 3dB
110b: 15dB
011b: 6dB
111b: 18dB
8.41. Private-21h: Auto Volume Control Register 1
Default: 2000’h
Table 51. PR21 Auto Volume Control Register 1
Name
Bits
15
RW
R
Default Description
0’h Reserved
2000’h The Maximum PCM Absolute Level After AVC, Thmax (=0~2^15-1)
Reserved
sel_avc_thmax
14:0
RW
8.42. Private-22h: Auto Volume Control Register 2
Default: 0800’h
Table 52. PR22 Auto Volume Control Register 2
Name
Bits
15
RW
R
Default Description
0’h Reserved
0800’h The Minimum PCM Absolute Level After AVC, Thmin (=0~2^15-1)
Reserved
sel_avc_thmin
14:0
RW
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
39
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
8.43. Private-23h: Auto Volume Control Register 3
Default: 0060’h
Table 53. PR23 Auto Volume Control Register 3
Name
Bits
15
RW
R
Default Description
0’h Reserved
Reserved
sel_avc_thnonact
14:0
RW
0060’h Non-Active PCM Absolute Level AVC.
Will Keep Analog Unit Gain, Thnonact (= 0~2^15-1)
8.44. Private-24h: Auto Volume Control Register 4
Default: 00FF’h
Table 54. PR24 Auto Volume Control Register 4
Name
Bits
RW
Default Description
sel_avc_cntminth
15:0
RW
00FF’h CNTMAXTH1. Controls the Sensitivity to Increased Gain (Unit: 2^1).
This value should be less than CNTMAXTH2
(Max=11111111111111110=2^17-2)
8.45. Private-25h: Auto Volume Control Register 5
Default: 0100’h
Table 55. PR25 Auto Volume Control Register 5
Name
Bits
RW
Default Description
sel_avc_cntmaxth
15:0
RW
0100’h CNTMAXTH2. Controls the Sensitivity to Increased Gain (Unit: 2^1).
This value should be less than Monitor Window (Optimal is 1/2
Monitor Window)
(Max=11111111111111110=2^17-2)
8.46. Private-39h: Digital Internal Register
Default: 8800’h
Table 56. PR39 Digital Internal Register
Name
Bits
RW
Default Description
1’h Pad Drive Capability
0b: 5mA 1b: 11mA
0800’h Reserved
sel_pad_drive
15
RW
Reserved
8:0
R
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
40
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
9. Electrical Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 57. Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Power Supplies
Digital Power for Core
DCVDD
DBVDD
AVDD
SPKVDD1/2
Ta
-0.3
-0.3
-0.3
-0.3
-20
-
-
-
-
-
-
3.63
3.63
3.63
7
V
V
V
Digital Power for IO and PLL
Analog and HP Amplifier Power
Speaker Amplifier Power
Ambient Operating Temperature
Storage Temperature
V
+85
+125
°C
°C
Ts
-40
9.1.2.
Recommended Operating Conditions
Table 58. Recommended Operating Conditions
Parameter
Symbol
DBVDD
Minimum
Typical
3.3
Maximum
Units
V
Digital IO Buffer
Digital Core
Analog
1.8
1.8
2.3
2.3
3.6
3.6
3.6
5
DCVDD
3.3
V
AVDD
3.3
V
Speaker
SPKVDD1/2*
3.3
V
Note: A 10µF Capacitor must be connected from SPKVDD to SPKGND, and should be placed as close as possible to the
SPKVDD pin of the ALC5626.
9.1.3.
Static Characteristics
DBVDD= 3.3V, Tambient=25°C, with 25pF external load.
Table 59. Threshold Voltage
Parameter
Symbol
Vin
Minimum
Typical
Maximum
Units
V
Input Voltage Range
-0.30
-
-
-
-
-
-
-
DBVDD +0.30
Low Level Input Voltage
High Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Low Level Input Voltage (JD2)
High Level Input Voltage(JD2)
VIL
-
0.33*DBVDD
V
VIH
0.66*DBVDD
-
V
VOH
VOL
VIL
0.9*DBVDD
-
V
-
0.1*DBVDD
0.33*AVDD
-
V
-
V
VIH
0.66*AVDD
V
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
41
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
9.2. Analog Performance Characteristics
• Tambient=25oC, DBVDD=DCVDD=AVDD=3.3V, SPKVDD=5V,
1kHz Input Sine Wave; Sampling Frequency=48kHz; 0dB=1Vrms,
Standard Test Conditions
10KΩ/50pF load; Test Bench Characterization BW: 10Hz~22kHz,
0dB Attenuation.
Table 60. Analog Performance Characteristics
Parameter
Minimum Typical Maximum
Units
Full Scale Input Voltage
LINE_IN/AUXIN/LINE3 Inputs (Gain=0dB)
-
1.0
-
Vrms
Full Scale Output Voltage
DAC Outputs
HP_OUT Outputs
SPK_OUT Outputs
-
-
-
1.0
1.0
1.5
-
-
-
Vrms
Vrms
Vrms
S/N (A Weighted)
DAC
-
-
100
100
-
-
dB FSA
dB FSA
Headphone Amplifier Output (RL=32Ω, PO=20mW)
THD+N
DAC
-
-
-90
-85
-
-
dB FS
dB FS
Headphone Amplifier Output (RL=32Ω, PO=20mW)
Speaker Power Supply Rejection (217Hz)
SE
BTL
-
-
55
70
-
-
dB
dB
Amplifier Gain Step
-
-
1.5
-95
600
45
-
-
-
-
-
-
dB
dB
Crosstalk (DAC to HP_OUT)
-
µA
mW
mA
W
HP Amplifier Quiescent Current (RL=32Ω @ 3.3V)
HP Amplifier Output Power (RL=16Ω)
SPK Class-AB/D Amplifier Quiescent Current (RL=8Ω @ 5V)
SPK Class-AB/D Amplifier Output Power (RL=4Ω @ 5V, 0.1%
THD+N)
25
-
4
-
1.6
-
1
-
W
SPK Class-AB/D Amplifier Output Power (RL=8Ω @ 5V, 0.1%
THD+N)
-
-
-
2
-
-
-
W
W
W
SPK Class-AB/D Amplifier Output Power (RL=4Ω @ 5V, 1% THD+N)
SPK Class-AB/D Amplifier Output Power (RL=8Ω @ 5V, 1% THD+N)
SPK Class-AB/D Amplifier Output Power (RL=4Ω @ 5V, 10%
THD+N)
1.15
2.4
-
1.4
-
W
SPK Class-AB/D Amplifier Output Power (RL=8Ω @ 5V, 10%
THD+N)
Quiescent Power Supply Current
(DAC to Headphone With 16ohm Load)
AVDD=DCVDD=DBVDD=3.3V
-
-
8
3
-
-
mA
µA
Digital Power Supply Current (Power Down Mode)
DCVDD=DBVDD=3.3V (Include POR Circuit)
Analog Power Supply Current (Power Down Mode)
AVDD=3.3V, SPKVDD=5V
-
-
-
-
0.5
-
1
-
µA
AVDD
ms
VREF Output Voltage
VREF Rising Time at Fast Mode (C=4.7µF)
50
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
42
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
9.3. AC Timing Characteristics
9.3.1.
I2C Control Interface
Table 61. I2C Control Interface Timing
Parameter
Symbol
tw(9)
tw(10)
f
Minimum
Typical
Maximum
Units
µs
ns
Clock Pulse Duration
Clock Pulse Duration
Clock Frequency
Re-Start Setup Time
Start Hold Time
Data Setup Time
Data Hold Time
Rising Time
1.3
600
0
-
-
-
-
-
-
-
-
-
-
-
-
-
400K
-
Hz
ns
tsu(6)
th(5)
tsu(7)
th(6)
tr
600
600
100
-
-
ns
-
ns
900
300
300
-
ns
-
ns
Falling Time
tf
-
ns
Stop Setup Time
tsu(8)
tsp
600
0
ns
Pulse Width of Spikes Suppressed
Input Filter
50
ns
Figure 18. I2C Control Interface Waveform
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
43
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
9.3.2.
I2S/PCM Interface Master Mode
Table 62. I2S/PCM Master Mode Timing
Parameter
Symbol
tLRD
Minimum
Typical
Maximum
Units
ns
LRCK Output to BCLK Delay
Data Input Setup Time
-
-
-
-
30
-
tDAS
10
10
ns
Data Input Hold Time
tDAH
-
ns
Figure 19. I2S/PCM Master Mode Waveform
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
44
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
9.3.3.
I2S/PCM Interface Slave Mode
Table 63. I2S/PCM Slave Mode Timing
Parameter
Symbol
tBCH
Minimum
Typical
Maximum
Units
ns
BCLK High Pulse Width
BCLK Low Pulse Width
LRCK Input Setup Time
Data Input Setup Time
Data Input Hold Time
20
20
30
10
10
-
-
-
-
-
-
-
-
-
-
tBCL
ns
tLRS
ns
tDAS
ns
tDAH
ns
Figure 20. I2S/PCM Slave Mode Waveform
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
45
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
10. Application Circuits
Application circuits are for design reference only. System designers are suggested to visit Realtek’s web
site to download the latest application circuits. To get the best compatibility in hardware design and
software driver, Realtek should confirm modifications of application circuits.
RGND1
0
Close to IC
Close to IC
RGND2
DBVDD
DCVDD
CB2
1000pF 1uF
CB1
CC2
1000pF 1uF
CC1
U1-1
BEAD
DGND
AGND
31
29
HP_OUT_L
HP_OUT_R
HP_OUT_L
HP_OUT_R
POWER / GND
LINE_IN_L
LINE_IN_R
2
7
LINE_IN_L
LINE_IN_R
Close to IC
Close to IC
6
3
19
22
23
25
SPK_OUT_RN
SPK_OUT_R
SPK_OUT_LN
SPK_OUT_L
LINE3_L
LINE3_R
LINE3_R
LINE3_L
SPK_OUT_RN
SPK_OUT_R
SPK_OUT_LN
SPK_OUT_L
AVDD
SPKVDD
CA2
CA1
CS2
CS1
10u
+
1000pF 1uF
1000pF
AUXIN_L
AUXIN_R
4
5
AUXIN_L
AUXIN_R
ALC5626
27
16
30
15
VREF
VREF
A1
MCLK
11
1
A1
C14
4.7u
MCLK
NC
PH7
Cdepop
GPIO
BCLK
LRCK
DACDAT
12
13
14
GPIO
C43
1u
5
4
3
2
1
C39
1u
LINE3_L
LINE3_R
BCLK
LRCK
SDAC
LI3_P
LI3_N
17
18
SCLK
SDA
SCLK
SDA
C40
1u
C41
C42
LINE3
C17
22p
C18
22p
220pF
220pF
Close to Phone
Jack for EMI
suppression
LINE3_IN
SPK_OUT_L
SPK_OUT_L
SPK_OUT_L
J1
SPK_OUT_R
J2
PH4
5
4
3
2
1
C21
C22
LINE_IN_L
1u
LINE_IN_R
SPK_OUT_LN SPK_CON
SPK_OUT_RN SPK_CON
LI_N
1u
C23
C24
LINE_IN
SPK-Out_L
SPK-Out_R
Close to Phone
Jack for EMI
suppression
220pF
220pF
LINE-IN
AVDD
RJ1
NC/100K
PH2
HP_R
1
2
3
4
5
HP_OUT_R
C7
C8
100u
100u
PH6
HP_L
HP_OUT_L
5
4
3
2
1
C33
C34
AUXIN_L
AUXIN_R
AXI_P
AXI_N
1u
1u
HPO
RJ2
R9
R10
C9
C10
NC/10K
C35
C36
220P
NC/4.7k
220P
GPIO
AUX_IN
NC/4.7k
Close to Phone
Jack for EMI
suppression
220pF
220pF
CJ1
NC/0.1u
HP-Out
AUX-IN
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
46
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
11. Mechanical Dimensions
QFN-32 Package; 5x5mm Outline
Symbol
Dimension in mm
Dimension in inch
Nom
Min
0.75
0.00
Nom
0.85
Max
1.00
0.05
Min
0.030
0.000
Max
0.039
0.002
A
A1
A3
b
0.034
0.02
0.001
0.20REF
0.25
0.008REF
0.010
0.18
-
0.30
0.6
0.007
-
0.012
0.024
c
-
-
D/E
D2/E2
e
5.00BSC
3.35
0.197BSC
0.132
3.10
3.60
0.122
0.012
0.142
0.020
0.50BSC
0.020BSC
0.016
L
0.30
0.40
0.50
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
47
Track ID: JATR-1076-21 Rev. 1.0
ALC5626
Datasheet
12. Ordering Information
Table 64. Ordering Information
Part Number
ALC5626-GR
ALC5626-GRT
Package
Status
QFN-32 in ‘Green’ Package (Tray)
MP
MP
QFN-32 in ‘Green’ Package (Tape & Reel)
Note: See page 6 for package and version identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
I2S Audio DAC + Headphone and Stereo Class-AB/D
Speaker Amplifier
48
Track ID: JATR-1076-21 Rev. 1.0
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