8102405VA [RENESAS]
4KX1 STANDARD SRAM, 320ns, CDIP18;
| 型号： | 8102405VA |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4KX1 STANDARD SRAM, 320ns, CDIP18 CD 静态存储器 内存集成电路 |
| 文件： | 总8页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
HM-6504
March 1997
4096 x 1 CMOS RAM
Features
Description
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max The HM-6504 is a 4096 x 1 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device uti-
lizes synchronous circuitry to achieve high performance and
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max
low power operation.
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Lead Package for High Density
• On-Chip Address Register
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
200ns
300ns
HM3-6504-9
HM1-6504-9
-
TEMP. RANGE
PACKAGE
PKG. NO.
E18.3
o
o
-
HM1-6504S-9
24501BVA
810240IVA
-
HM3-6504B-9
-40 C to +85 C
PDIP
o
o
HM1-6504B-9
-40 C to +85 C
CERDIP
JAN #
F18.3
-
-
-
F18.3
8102403VA
-
8102405VA
HM4-6504-9
SMD #
CLCC
F18.3
o
o
-40 C to+85 C
J18.B
Pinouts
HM-6504 (PDIP, CERDIP)
HM-6504 (CLCC)
TOP VIEW
TOP VIEW
PIN
DESCRIPTION
Address Input
Chip Enable
Write Enable
Data Input
A
E
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A0
A1
A2
A3
A4
A5
Q
V
CC
2
1
18 17
A6
A7
A8
A9
A10
A11
D
16
A7
3
4
5
6
7
A2
A3
A4
A5
Q
W
D
Q
15 A8
14 A9
Data Output
13
12
A10
A11
W
8
9
10 11
GND
E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
FN2994.1
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
126
HM-6504
Functional Diagram
LSB
A
A
A8
A7
A6
A0
A1
A2
6
6
LATCHED
ADDRESS
REGISTER
GATED
64 x 64
ROW
MATRIX
64
DECODER
L
G
64
G
Q
GATED COLUMN
DECODER AND
DATA I/O
D
Q
D
Q
D
LATCH
L
LATCH
L
A
A
D
Q
Q
W
LATCH
L
6
6
A
A
LATCHED
ADDRESS
REGISTER
E
L
L
D
LATCH
LSB A11 A5 A4 A3 A9 A10
NOTES:
13. All lines active high-positive logic.
14. Three-state Buffers: A high → output active.
15. Control and Data Latches: L low → Q = D and Q latches on rising edge of L.
16. Address Latches: Latch on falling edge of E.
17. Gated Decoders: Gate on rising edge of G.
127
HM-6504
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V +0.3V
Thermal Resistance (Typical)
CERDIP Package . . . . . . . . . . . . . . . . 75 C/W
PDIP Package . . . . . . . . . . . . . . . . . . . 75 C/W
CLCC Package . . . . . . . . . . . . . . . . . . 90 C/W
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C
θ
θ
JC
15 C/W
JA
o
o
CC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
N/A
o
o
33 C/W
o
o
o
o
o
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-6504S-9, HM-6504B-9, HM-6504-9 . . . . . . . .-40 C to +85 C
HM-6504B-8, HM-6504-8 . . . . . . . . . . . . . . . . . .-55 C to +125 C
o
o
o
o
o
o
DC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-6504B-9, HM-6504-9)
CC
A
o
o
T
= -55 C to +125 C (HM-6504B-8, HM-6504-8)
A
SYMBOL
PARAMETER
MIN
MAX
25
UNITS
µA
TEST CONDITIONS
ICCSB
Standby Supply Current
HM-6504-9
HM-6504-8
-
-
-
IO = 0mA, E = V -0.3V,
CC
V
= 5.5V
CC
50
µA
ICCOP
ICCDR
Operating Supply
Current (Note 1)
7
mA
E = 1MHz, IO = 0mA, VI = GND,
= 5.5V
V
CC
Data Retention Supply
Current
HM-6504-9
HM-6504-8
-
15
25
µA
µA
V
IO = 0mA, V
= 2.0V, E = V
CC
CC
-
VCCDR
II
Data Retention Supply Voltage
Input Leakage Current
Output Leakage Current
Input Low Voltage
2.0
-1.0
-1.0
-0.3
-
+1.0
+1.0
0.8
µA
µA
V
VI = V
or GND, V
= 5.5V
CC
CC
IOZ
VO = V
or GND, V
= 5.5V
CC
CC
VIL
V
V
= 4.5V
= 5.5V
CC
CC
VIH
Input High Voltage
V
V
-2.0
V
+0.3
CC
V
CC
VOL
VOH1
VOH2
Output Low Voltage
-
0.4
V
IO = 2.0mA, V
CC
= 4.5V
= 4.5V
Output High Voltage
2.4
-
-
V
IO = -1.0mA, V
CC
CC
Output High Voltage (Note 2)
-0.4
V
IO = -100µA, V
= 4.5V
CC
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
MAX
8
UNITS
TEST CONDITIONS
CI
Input Capacitance (Note 2)
Output Capacitance (Note 2)
pF
pF
f = 1MHz, All measurements are
referenced to device GND
CO
10
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
128
HM-6504
o
o
AC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-6504S-9, HM-6504B-9, HM-6504-9)
CC
A
o
o
T
= -55 C to +125 C (HM-6504B-8, HM-6504-8)
A
HM-6504S
MIN MAX
HM-6504B
MIN MAX
HM-6504
TEST
CONDITIONS
SYMBOL
PARAMETER
MIN
MAX
300
320
-
UNITS
ns
(1)
TELQV
TAVQV
TELQX
Chip Enable Access Time
Address Access Time
-
-
120
120
-
-
-
200
220
-
-
-
(Notes 1, 3)
(Notes 1, 3, 4)
(Notes 2, 3)
(2)
(3)
ns
Chip Enable Output Enable
Time
5
5
5
ns
(4) TEHQZ
Chip Enable Output Disable
Time
-
50
-
-
80
-
-
100
ns
ns
ns
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(5)
(6)
TELEH
TEHEL
Chip Enable Pulse Negative
Width
120
50
200
90
300
120
-
-
Chip Enable Pulse Positive
Width
-
-
(7) TAVEL
(8) TELAX
Address Setup Time
Address Hold Time
0
-
-
-
-
20
50
-
-
-
-
20
50
-
-
-
-
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
40
20
70
(9) TWLWH Write Enable Pulse Width
60
80
(10) TWLEH
Write Enable Pulse Setup
Time
150
200
(11)
(12)
TWLEL
TWHEL
Early Write Pulse Setup
Time
0
0
-
-
0
0
-
-
0
0
-
-
ns
ns
(Notes 1, 3)
(Notes 1, 3)
Write Enable Read Mode
Setup Time
(13) TELWH
(14) TDVWL
(15) TDVEL
(16) TWLDX
(17) TELDX
(18) TELEL
Early Write Pulse Hold Time
Data Setup Time
40
0
-
-
-
-
-
-
60
0
-
-
-
-
-
-
80
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
Early Write Data Setup Time
Data Hold Time
0
0
0
25
25
170
60
60
290
80
80
420
Early Write Data Hold Time
Read or Write Cycle Time
NOTES:
1. Input pulse levels: 0.8V to V
- 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
CC
1 TTL gate equivalent, C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pF.
L
L
2. Tested at initial design and after major design changes.
3. V = 4.5V and 5.5V.
CC
4. TAVQV = TELQV + TAVEL.
129
HM-6504
Timing Waveforms
(8)
TELAX
(7)
TAVEL
(7)
TAVEL
ADD VALID
A
E
NEXT ADD
(6)
TEHEL
TELEL (18)
TELEH
(5)
TEHEL
(6)
(1) TELQV
(4) TEHQZ
VALID DATA OUTPUT
(3)
TELQX
HIGH Z
HIGH
HIGH Z
Q
W
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 11. READ CYCLE
TRUTH TABLE
OUTPUT
INPUTS
TIME REFERENCE
E
W
X
A
X
V
X
X
X
X
V
Q
Z
Z
X
V
V
Z
Z
FUNCTION
-1
0
1
2
3
4
5
H
Memory Disabled
H
H
H
H
X
Cycle Begins, Addresses are Latched
Output Enabled
L
L
Output Valid
Read Accomplished
H
Prepare for Next Cycle (Same as -1)
H
Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on-chip registers enabled but the data is not valid until during time (T = 2). W
on the falling edge of E (T = 0). Minimum address set-up and must remain high for the read cycle. After the output data
hold time requirements must be met. After the required hold has been read, E may return high (T = 3). This will disable
time, the addresses may change state without affecting the output buffer and all input and ready the RAM for the
device operation. During time (T = 1) the output becomes
next memory cycle (T = 4).
130
HM-6504
Timing Waveforms (Continued)
(7)
(8)
(7)
TAVEL TELAX
TAVEL
NEXT ADD
A
ADD VALID
(18) TELEL
(5) TELEH
(6)
TEHEL
(6) TEHEL
E
(11)
TWLEL
(11)
(13)
TWLEL TELWH
W
(15)
(17)
(15)
TDVEL TELDX
TDVEL
D
0
DATA VALID
NEXT DATA
HIGH-Z
HIGH-Z
TIME
REFERENCE
-1
0
1
2
3
4
FIGURE 12. EARLY WRITE CYCLE
TRUTH TABLE
INPUTS
OUTPUT
TIME REFERENCE
E
W
X
L
A
X
V
X
X
X
V
D
X
V
X
X
X
V
Q
Z
Z
Z
Z
Z
Z
FUNCTION
-1
0
1
2
3
4
H
Memory Disabled
Cycle Begins, Addresses are Latched
Write in Progress Internally
L
X
X
X
L
Write Completed
H
Prepare for Next Cycle (Same as - 1)
Cycle Ends, Next Cycle Begins (Same as 0)
The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on-chip registers. The logic value of W at the
time E falls, determines the state of the output buffer for that
cycle. Since W is low when E falls, the output buffer is
latched into the high impedance state and will remain in that
131
HM-6504
state until E returns high (T = 2). For this cycle, the data returns to the high state, the output buffer and all inputs are
input is latched by E going low; therefore, data set-up and disabled and all signals are unlatched. The device is now
hold times should be referenced to E. When E (T = 2) ready for the next cycle.
Timing Waveforms (Continued)
(7)
TAVEL
(8)
(7)
TELAX
TAVEL
A
E
ADD VALID
NEXT ADD
(18) TELEL
(5) TELEH
(6)
TEHEL
(10)
(6)
TEHEL
TWLEH
(9)
TWLWH
W
(14)
(16)
TDVWL
TWLDX
DATA VALID
D
Q
(4)
TEHQZ
(3)
TELQX
HIGH Z
HIGH Z
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 13. LATE WRITE CYCLE
TRUTH TABLE
OUTPUTS
INPUTS
TIME
REFERENCE
E
W
X
A
X
V
X
X
X
X
V
D
X
X
V
X
X
X
X
Q
Z
Z
X
X
X
Z
Z
FUNCTION
-1
0
1
2
3
4
5
H
Memory Disabled
H
Cycle Begins, Addresses are Latched
Write Begins, Data is Latched
Write In Progress Internally
L
L
H
H
X
H
Write Completed
H
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
The late write cycle is a cross between the early write cycle between these two cases. With this cycle the output may
and the read-modify-write cycle.
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write the
output is guaranteed valid at access time. The late write is
132
HM-6504
Test Load Circuit
DUT
(NOTE 1) C
L
+
IOH
1.5V
IOL
-
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance includes stray and jig capacitance.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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133
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