HD66115TA3 [RENESAS]
LIQUID CRYSTAL DISPLAY DRIVER, UUC181, SLIM, TCP-181;
| 型号： | HD66115TA3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC181, SLIM, TCP-181 驱动 接口集成电路 |
| 文件： | 总21页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD66115T
(160-Channel Common Driver Packaged
in a Slim Tape Carrier Package)
ADE-207-282(Z)
'99.9
Rev. 0.0
Description
The HD66115T is a common driver for large dot matrix liquid crystal graphics displays. It features 160
channels which can be divided into two groups of 80 channels by selecting data input/output pins. The
driver is powered by about 3 V, making it suitable for the design of portable equipment which fully utilizes
the low power dissipation of liquid crystal elements. The HD66115T, packaged in a slim tape carrier
package (slim-TCP), makes it possible to reduce the size of the user area (wiring area).
Features
•
•
•
•
•
•
•
•
Duty cycle: About 1/100 to 1/480
160 LCD drive circuits
High LCD driving voltage: 14V to 40V
Output division function (2 × 80-channel outputs)
Display off function
Operating voltage: 2.5V to 5.5V
Slim-TCP
Low output impedance: 0.7 kΩ (typ)
Ordering Information
Type No.
Outer Lead Pitch (µm)
HD66115TA0
HD66115TA3
180
250
Note: The details of TCP pattern are shown in “The Information of TCP.”
1
HD66115T
Pin Arrangement
Top view
Note: This figure does not specify the tape carrier package dimensions.
Pin Assignments
181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161
2
HD66115T
Pin Descriptions
Symbol
VLCD1, 2
VCC
Pin No.
Pin Name
VLCD
Input/Output
—
Classification
177, 163
166
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
LCD drive output
VCC
—
GND1, 2
V1L, V1R
V2L, V2R
V5L, V5R
V6L, V6R
CL
176, 170
178, 165
181, 161
180, 162
179, 164
171
GND
—
V1L, V1R
V2L, V2R
V5L, V5R
V6L, V6R
Clock
Input
Input
Input
Input
Input
M
172
M
Input
CH
175
CH
Input
SHL
174
Shift left
Data
Input
DIO1
169
Input/output
Input/output
Input
DIO2
167
Data
DI
168
Data
DISPOFF
X1–X160
173
Display off
X1–X160
Input
1–160
Output
3
HD66115T
Pin Functions
Power Supply
VCC, GND: Supply power to the internal logic circuits.
VLCD, GND: Supply power to the LCD drive circuits (Figure 1).
V1L, V1R, V2L, V2R, V5L, V5R, V6L, V6R: Supply different power levels to drive the LCD. V1 and
V2 are selected levels, and V5 and V6 are non-selected levels.
Control Signals
CL: Inputs data shift clock pulses for the shift register. At the falling edge of each CL pulse, the shift
register shifts data input via the DIO pins.
M: Changes the LCD drive outputs to AC.
CH: Selects the data shift mode. (CH = high: 2 × 80-output mode, CH = low: 160-output mode)
SHL: Selects the data shift direction for the shift register and the common signal scan direction (Figure 2).
DIO1, DIO2: Input or output data. DIO1 is input and DIO2 is output when SHL is high. DIO1 is output
and DIO2 is input when SHL is low.
DI: Input data. DI is input to X81–X160 when CH and SHL are high, and to X81–X1 when SHL is low.
DISPOFF: Controls LCD output level. A low DISPOFF sets the LCD drive outputs X1–X160 to the V2
level. A high DISPOFF is normally used.
LCD Drive Outputs
X1–X160: Each X outputs one of four voltage levels V1, V2, V5, or V6, depending on the combination of
the M signal and the data level (Figure 3).
4
HD66115T
VLCD1, 2
VCC
GND1, 2
Figure 1 Power Supply for LCD Driver
SHL
Data shift direction
Shift to right
High
Low
DIO1 → SR1 → SR2 → SR3 • • • → SR160 → DIO2
Shift to left
DIO2 → SR160 → SR159 • • • → SR1 → DIO1
Note: SR1 to SR160 correspond to the outputs of X1 to X160, respectively.
Figure 2 Selection of Data Shift Direction and Common Signal Scan Direction by SHL
M
1
0
DATA
1
0
1
0
V2
V6
V1
V5
X output level
Figure 3 Selection of LCD Drive Output Level
5
HD66115T
Block Diagram
X1–X160
V1L, V2L,
V5L, V6L
V1R, V2R,
V5R, V6R
LCD drive circuit
M
VCC
GND1, 2
VLCD1, 2
Level shifter
DISPOFF
CL
Logic
Logic
Shift register
Shift register
SR
Q
Q
Q
Q
• • • • • • SR80
SR1
SR81 • • • • • •
160
D
D
D
D
Logic
DIO1
DIO2
SHL
CH
DI
6
HD66115T
Block Functions
LCD Drive Circuit
The 160-bit LCD drive circuit generates four voltage levels V1, V2, V5, and V6, which drive the LCD
panel. One of these four levels is output to the corresponding X pin, depending on the combination of the
M signal and the data in the shift register.
Level Shifter
The level shifter changes logic control signals (2.5V–5.5V) into high-voltage signals for the LCD drive
circuit.
Shift Register
The 160-bit shift register shifts the data input via the DIO pin by one bit at a time. The one bit of shifted-
out data is output from the DIO pin to the next driver IC. Both actions occur simultaneously at the falling
edge of each shift clock (CL) pulse. The SHL pin selects the data shift direction.
7
HD66115T
Absolute Maximum Ratings
Item
Symbol
VCC
Rating
Unit
V
Notes
1, 5
Power supply voltage for logic circuits
Power supply voltage for LCD drive circuits
Input voltage 1
–0.3 to +7.0
VLCD
VT1
VT2
VT3
Topr
–0.3 to +42
V
1, 5
–0.3 to VCC + 0.3
VLCD – 7.0 to VLCD + 0.3
–0.3 to +7.0
V
1, 2
Input voltage 2
V
1, 3
Input voltage 3
V
1, 4
Operating temperature
Storage temperature
–30 to +75
°C
°C
Tstg
–55 to +110
Notes: 1. The reference point is GND (0V).
2. Applies to pins CL, M, SHL, DI, DISPOFF, and CH.
3. Applies to pins V1 and V6.
4. Applies to pins V2 and V5.
5. Power should be applied to VCC–GND first, and then VLCD–GND. It should be disconnected in
the reverse order.
6. If the LSI is used beyond its absolute maximum ratings, it may be permanently damaged.
It should always be used within its specified operating range in order to prevent malfunctions or
loss of reliability.
8
HD66115T
Electrical Characteristics
DC Characteristics (VCC = 2.5 to 5.5V, GND = 0V, VLCD–GND = 14 to 40V, and Ta = –30 to +75°C,
unless otherwise noted)
Item
Symbol Pins Min
Typ Max
Unit Test Condition
Notes
Input high
voltage
VIH
1
0.8 × VCC
—
VCC
V
Input low voltage VIL
1
2
0
—
—
0.2 × VCC
V
Output high
voltage
VOH
VCC – 0.4
—
V
IOH = –0.4 mA
Output low
voltage
VOL
RON
IIL1
2
—
—
0.7
—
—
—
—
0.4
1.0
5
V
IOL = 0.4 mA
Vi–Xj on
resistance
3
—
kΩ
µA
µA
mA
mA
ION = 150 µA
1
2
Input leakage
current 1
1
–5
–25
—
VIN = VCC to GND
VIN = VLCD to GND
Input leakage
current 2
IIL2
4
25
0.5
1.0
Current
consumption 1
IGND
ILCD
—
—
fCL = 36 kHz
fM = 75 kHz
Current
—
consumption 2
Note: Pins: 1. CL, M, SHL, CH, DI, DIO1, DIO2, DISPOFF
2. DIO1, DIO2
3. X1–X160, V
4. V1, V2, V5, V6
Notes: 1. Indicates the resistance between one of the pins X1–X160 and one of the voltage supply pins
V1, V2, V5, or V6, when load current is applied to the X pin; defined under the following
conditions:
Ta = 25°C Note that RON depends on Ta (°C) (Figure 4).
VLCD–GND = 40V
V1, V6 = VLCD – {1/20 (VLCD–GND)}
V5, V2 = GND + {1/20 (VLCD–GND)}
All voltages must be within ∆V, VLCD ≥ V1 ≥ V6 ≥ VLCD – 7.0V, and 7.0V ≥ V5 ≥ V2 ≥ GND.
Note that ∆V depends on the power supply voltage VLCD–GND (Figure 6).
2. Input and output currents are excluded. When a CMOS input is left floating, excess current flows
from the power supply through the input circuit. To avoid this, VIH and VIL must be held at VCC
and GND, respectively.
9
HD66115T
1 k
800
600
400
200
0
–20
25
Ta (°C)
75
Figure 4 Relation between RON and Ta
VLCD
V1
∆V
V6
V5
V2
∆V
GND
Figure 5 Relation between Driver Output Waveform and Voltage Levels
6.4
∆V (V)
Voltage level range
2.3
14
40
VLCD–GND (V)
Figure 6 Relation between VLCD–GND and DV
10
HD66115T
AC Characteristics (VCC = 2.5 to 5.5V, GND = 0V, and Ta = –30 to +75°C, unless otherwise noted)
Item
Symbol
tCYC
tCWH
tCWL
tr
Pins
Min
400
30
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Notes
Clock cycle time
Clock high-level width
Clock low-level width
Clock rise time
CL
CL
—
CL
370
—
—
CL
30
Clock fall time
tf
CL
—
30
Data setup time
Data hold time
tDS
DI, DIO1, DIO2, CL
DI, DIO1, DIO2, CL
DIO1, DIO2, CL
M, CL
100
30
—
tDH
—
Data output delay time
M phase difference
Output delay time 1
Output delay time 2
tDD
—
350
300
1.2
1.2
1
tM
–300
—
tpd1
tpd2
X (n), CL
2
2
X (n), M
—
AC Characteristics (VCC = 5.0V ± 10%, GND = 0V, and Ta = –30 to +75°C, unless otherwise noted)
Item
Symbol
tCYC
tCWH
tCWL
tr
Pins
Min
400
30
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Notes
Clock cycle time
Clock high-level width
Clock low-level width
Clock rise time
CL
CL
—
CL
370
—
—
CL
30
Clock fall time
tf
CL
—
30
Data setup time
Data hold time
tDS
DI, DIO1, DIO2, CL
DI, DIO1, DIO2, CL
DIO1, DIO2, CL
M, CL
100
30
—
tDH
—
Data output delay time
M phase difference
Output delay time 1
Output delay time 2
tDD
—
150
300
0.7
0.7
1
tM
–300
—
tpd1
tpd2
X (n), CL
2
2
X (n), M
—
Note: 1, 2 The load circuit shown in Figure 7 is connected.
11
HD66115T
Test point
*1: 30 pF
*2: 100 pF
Figure 7 Load Circuit
tf
tr
tCWL
tCWH
tCYC
0.8 × VCC
0.2 × VCC
CL
tDD
tDS
tDH
0.8 × VCC
0.2 × VCC
DIO1, DIO2,
DI
(input)
0.8 × VCC
0.2 × VCC
DIO1, DIO2,
DL
(output)
tM
M
tpd2
X (n)
tpd1
Figure 8 LCD Controller Interface Timing
12
HD66115T
Operation Timing (1/480 Duty Cycle)
From LCD controller
HD66115T (2)
HD66115T (1)
HD66115T (3)
13
HD66115T
Connection Examples
Figures 9 and 10 show examples of how HD66115Ts can be configured to drive a 480-line LCD panel with
a 1/240 duty cycle. Figures 11 and 12 show examples of how HD66115Ts can be configured to drive a
480-line LCD panel with a 1/480 duty cycle. The HD66115T's 160 channels can be divided into two groups
of 80 channels, and its data shift direction can be changed by selecting the data output mode pin (CH) and
data shift pin (SHL), respectively.
LCD panel
DATA
(Data of lines 1 to 240)
DIO1
X1 →
Line 1
IC1
(SHL = high, CH = low)
Line 160
Line 161
→
→
DIO2 X160
DIO1
DI
X1
IC2
(SHL = high, CH = high)
X80
X81
→
→
Line 240
Line 241
DATA
(Data of lines 241 to 480)
DIO2 X160
→
→
Line 320
Line 321
DIO1
X1
IC3
(SHL = high, CH = low)
→
Line 480
DIO2 X160
↑
↑
Segment driver
Figure 9 Dual-Screen Configuration of a 480-Line LCD Panel with a 1/240 Duty Cycle (1)
14
HD66115T
LCD panel
DIO1
X1 →
Line 1
IC1
(SHL = low, CH = low)
→
Line 160
Line 161
X160
DIO2
DIO1
X1 →
IC2
(SHL = low, CH = high)
X80 →
X81 →
Line 240
Line 241
DATA
(Data of lines 1 to 240)
DI
DIO2 X160 →
Line 320
Line 321
DIO1
X1 →
IC3
(SHL = low, CH = low)
DATA
→
Line 480
DIO2 X160
(Data of lines 241 to 480)
↑
↑
Segment driver
Figure 10 Dual-Screen Configuration of a 480-Line LCD Panel with a 1/240 Duty Cycle (2)
15
HD66115T
LCD panel
DATA
(Data of lines 1 to 480)
DIO1
X1 →
Line 1
IC1
(SHL = high, CH = low)
→
→
Line 160
Line 161
DIO2 X160
DIO1
X1
IC2
(SHL = high, CH = low)
DIO2 X160 →
Line 320
Line 321
DIO1
X1 →
IC3
(SHL = high, CH = low)
X160 →
Line 480
DIO2
↑
↑
Segment driver
Figure 11 Single-Screen Configuration of a 480-Line LCD Panel with a 1/480 Duty Cycle (1)
16
HD66115T
LCD panel
DIO1
X1
→
Line 1
IC1
(SHL = low, CH = low)
Line 160
Line 161
→
→
DIO2 X160
DIO1
X1
IC2
(SHL = low, CH = low)
DIO2 X160
→
→
Line 320
Line 321
DIO1
X1
IC3
(SHL = low, CH = low)
DATA
(Data of lines 1 to 480)
→
Line 480
DIO2 X160
↑
↑
Segment driver
Figure 12 Single-Screen Configuration of a 480-Line LCD Panel with a 1/480 Duty Cycle (2)
17
HD66115T
Notes on Power-On/Off of the LCD Driver
To prevent an LCD driver display error at power on/off, the sequence for power-on signal activation must
be as follows (see Figure 13):
2.7V
2.7V
VCC
0ms
0ms
0ms
0ms
VLCD
DISP
Input signals such as
CL1, CL2, and Data
Signal non-fixed Initializing period
period
(1frame or longer)
Figure 13 Sequence of Power-On/Off
At Power On
(1) Power on VCC. At this time, input 0 to the DISP pin.
(2) Display-off function forces the LCD driver to output a V2 level (lowest level).
(3) Display-off function takes priority even if the input signal status becomes irregular immediately after
VCC power-on.
(4) Input the specified signals to initialize registers of the LCD driver. Its period must be 1 frame or longer.
(5) Set the DISP level to 1 to cancel display-off function after steps (1) to (4). At this time, VLCD and each
V pin input must be at the specified levels.
18
HD66115T
At Power Off
Basically, the power-off procedure is the reverse of the power-on procedure.
(1) Set the DISP level to 0.
(2) Lower LCD driver power supply to 0V
(3) Lower VCC and each input signals to 0V
At this time, each V pin input must be at 0V. Display-off function stops when VCC falls to 0V, and
therefore, the LCD driver may output a level other than V2 (lowest level). As a result, a display error may
be caused at power-off or power-on.
19
HD66115T
LCD Driver LSI Power Supply Pin Connection
A feature of the LCD driver is the LCD drive power supply. As the number of pixel drives per LSI
increases, so does the voltage and number of outputs.
Consequently, if multi-output CMOS circuits are switched simultaneously, a wiring voltage drop may
occurs due to transient currents, and the potential between the LCD drive circuit power supply (VLCD) and
LCD drive level power supplies (V1, V6, and V3) or GND and the LCD level power supplies (V2, V5, and
V4) may be inverted, resulting in latchup breakdown. To prevent this, it is recommended that, when
designing the LCD drive power supply and board power supply wiring, the power supply wiring be
designed as low-impedance and capacitors be inserted in the wiring between VLCD and V1, V3, V6, and
between V2, V4, V5 and GND. In set evaluation, it is recommended that a check be carried out to confirm
that there is no inversion of the LCD drive power supply and level power supplies in the period between
when the LCD drive power supply is turned on and turned off.
Example of capacitor insertion (when VLCD = V1 and GND = V2)
VLCD, V1 pins
(COM, SEG)
+
–
+
–
+
–
V6 pin (COM)
V3 pin (SEG)
V4 pin (SEG)
V5 pin (COM)
+
–
Electrolytic capacitor
Ceramic capacitor
+
–
+
–
GND, V2 pins
(COM, SEG)
Figure 14 Example of Capacitor Insertion
20
HD66115T
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
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(America) Inc.
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Harbour City, Canton Road, Tsim Sha Tsui,
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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