HD74ACT166T-ELL [RENESAS]
暂无描述;
| 型号： | HD74ACT166T-ELL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 暂无描述 移位寄存器 |
| 文件： | 总9页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74AC166/HD74ACT166
8-bit Shift Register
REJ03D0255–0200Z
(Previous ADE-205-375 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type
flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An
asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources
or one CP input can be used to trigger the other.
Features
•
•
Outputs Source/Sink 24 mA
HD74ACT166 has TTL-Compatible Inputs
•
Ordering Information: Ex. HD74AC166
Part Name
Package Type
Package Code Pabbreviation (Quantity)
HD74AC166AFPEL SOP-16 pin (JEITA) FP-16DAV
HD74AC166ARPEL SOP-16 pin (JEDEC) FP-16DNV
000 pcs/reel)
(2,500 pcs/reel)
ELL(2,000 pcs/reel)
HD74AC166TELL TSSOP-16 pin
TTP-16DA
Notes: 1. Please consult the sales office for the a
2. The packages with lead-free pins are ional products by adding V at the end of
the package code.
Pin Arrangement
4
5
6
7
8
16 VCC
2
3
2
1
15 PE
14
13
P
7
P
Q
7
P
12 P
11 P
10 P
6
CP
CP
5
4
GND
9
MR
(Top view)
Rev.2.00, Jul.16.2004, page 1 of 8
HD74AC166/HD74ACT166
Logic Symbol
15
2
3
4
5
10 11 12 14
PE P
0
P1
P
2
P3
P4
P5
P
6
P7
1
D
S
7
6
1
CP
2
MR
9
Q7
13
CC=Pin16
GND=Pin8
V
Pin Names
CP1, CP2 Clock Pulse Inputs (Active Rising Edge)
DS
Serial Data Input
PE
Parallel Enable Input (Active Low)
Parallel Data Inputs
Asynchronous Master Reset Input (Active L
Last Stage Output
P0 to P7
MR
Q7
Functional Description
Operation is synchronous (except for Master iated by the rising edge of either clock
input if the other clock input is Low. Wheas an active High clock inhibt, it should
attain the High state while the other clowing the previous operation. When the Parallel
Enable (PE) input is Low, data is loaarallel Data (P0 to P7) inputs on the next rising edge
of the clock. When PE is High, inerial Data (DS) input to Q0 and all data in the register is
shifted one bit position (i.e., Qsing edge of the clock.
Truth Table
Parallel
P0 to P7
Internal Outputs
Q0 Q6
Output
Q7
MR
PE
DS
L
X
X
L
X
L
L
L
L
H
X
X
X
H
L
X
X
L
L
L
H
H
H
H
H
QA0
a
QB0
b
QH0
h
a ··· h
H
H
X
X
X
X
H
QAn
QAn
QB0
QGn
QGn
QH0
L
X
QA0
H : High Voltage Level
L
:
:
Low Voltage Level
Immaterial
X
:
Low-to-High Clock Transition
Rev.2.00, Jul.16.2004, page 2 of 8
HD74AC166/HD74ACT166
Logic Diagram
CP
1 2
P0
DS
P1
P2
P3
P4
P5
P6
MR
P7
PE
R
CD
CP
S
R CP S
CD
Q
Q
Q7
Absolute Maximum Ratings
Item
Supply voltage
Symbol
t
Condition
VCC
DC input diode current
IIK
mA
mA
V
VI = –0.5V
VI = Vcc+0.5V
DC input voltage
V
DC output diode current
mA
mA
V
VO = –0.5V
VO = Vcc+0.5V
DC output voltage
cc+0.5
DC output source or sink current
DC VCC or ground current per
Storage temperature
mA
mA
°C
50
–65 to +150
Recommended s: HD74AC166
Item
Symbol
VCC
Ratings
Unit
Condition
Supply voltage
2 to 6
V
Input and output voltage
Operating temperature
VI, VO
Ta
0 to VCC
–40 to +85
8
V
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
tr, tf
VCC = 3.0V
VCC = 4.5 V
VCC = 5.5 V
VIN 30% to 70% VCC
Rev.2.00, Jul.16.2004, page 3 of 8
HD74AC166/HD74ACT166
DC Characteristics: HD74AC166
Item
Sym-
bol
Vcc
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.1
3.15
3.85
—
typ.
1.5
max.
—
min.
2.1
3.15
3.85
—
max.
—
Input Voltage
VIH
VIL
3.0
V
VOUT = 0.1 V or VCC –0.1 V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
—
—
0.9
1.35
1.65
—
0.9
1.35
1.65
—
VOUT = 0.1 V or VCC –0.1 V
—
—
—
—
Output voltage
VOH
2.9
4.4
5.4
2.58
3.94
4.94
—
2.9
4.4
5.4
2.48
3.80
4.80
—
V
VIN = VIL or VIH
IOUT = –50 µA
—
—
—
—
—
—
VIN = VIL or VIH
IOH = –12 mA
—
—
—
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.002 0.1
0.001 0.1
0.001 0.1
0.1
0.1
0
N = VIL or VIH
= 50 µA
—
—
—
—
—
—
—
—
—
0.32
—
VIH
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
—
0.32
0.32
±0.1
—
—
Input leakage
current
IIN
—
= VCC or GND
Dynamic output
current*
IOLD
IOHD
ICC
5.5
5.5
5.5
—
—
—
—
—
mA
µA
VOLD = 1.1 V
VOHD = 3.85 V
Quiescent supply
current
VIN = VCC or ground
*Maximum test duration 2.0 ms, one outp
Recommended OperatiACT166
Item
Ratings
Unit
Condition
Supply voltage
2 to 6
V
V
Input and output volta
Operating temperatur
0 to VCC
–40 to +85
8
°C
ns/V
Input rise and fall time
(except Schmitt inputs)
r, tf
V
V
CC = 4.5V
CC = 5.5V
VIN 0.8 to 2.0 V
Rev.2.00, Jul.16.2004, page 4 of 8
HD74AC166/HD74ACT166
DC Characteristics: HD74ACT166
Item
Sym-
bol
VCC
(V)
Ta = 25°C
Ta = –40 to
Unit
Condition
+85°C
min.
2.0
2.0
—
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
max.
—
min.
2.0
2.0
—
max.
—
Input voltage
VIH
VIL
4.5
V
V
V
V
OUT = 0.1 V or Vcc–0.1 V
OUT = 0.1 V or Vcc–0.1 V
IN = VIL or VIH
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
—
—
0.8
0.8
—
0.8
0.8
—
—
—
Output voltage
VOH
4.4
5.4
3.94
4.94
—
4.4
5.4
3.80
4.80
—
V
IOUT = –50 µA
—
—
—
—
VIN = VIL
IOH = –24 mA
IOH = –24 mA
—
—
—
VOL
0.001 0.1
0.001 0.1
0.1
0.1
0.37
0.37
±1.0
1.5
VIN = VIL or VIH
IOUT = 50 µA
—
—
—
—
—
—
0.6
—
—
—
0.32
—
VIN = VIL
IOL = 24 mA
IOL = 24 mA
—
0.32
±0.1
—
—
Input current
IIN
—
—
N = VCC or GND
VCC–2.1 V
.1 V
ICC/input current
ICCT
IOLD
IOHD
ICC
—
—
Dynamic output
current*
—
—
86
—
—
–75
—
V
Quiescent supply
current
—
8.0
r ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC166
= –40°C to +85°C
CL = 50 pF
Item
Maximum clock
frequency
Symbol VCC (
Min
Max
Unit
fmax
3.3
65
—
—
MHz
ns
.0
1.0
—
80
Propagation delay
CP1 or CP2 to Q7
Propagation delay
CP1 or CP2 to Q7
Propagation delay
MR to Q7
tPLH
10.5
9.0
9.5
6.5
14.5
11.5
14.0
11.0
12.0
9.0
1.0
1.0
1.0
1.0
1.0
1.0
15.5
12.5
15.0
12.0
13.0
10.0
Note: 1. Voltage Range 3.3 V
Voltage Range 5.0 is 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8
HD74AC166/HD74ACT166
AC Operating Requirements: HD74AC166
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
Symbol VCC (V)*1
Typ
Guaranteed Minimum
Unit
Setup time
tsu
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.0
5.5
6.0
4.5
3.0
3.0
7.0
5.0
0.0
0.0
ns
PE or Pn or DS to CPn
Hold time
2.0
4.0
3.0
3.0
5.5
4.5
0.0
0.0
th
–1.5
–0.5
2.0
CPn to PE or Pn or DS
Pulse width
tw
CPn or MR
Recovery time
2.0
trec
–2.5
–1.5
MR to CPn
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT166
Ta = +25°C
CL = 50 pF
°C
Item
Symbol VCC (V)*1
Min
100
Typ
M
Unit
Maximum clock
frequency
fmax
5.0
5.0
5.0
5.0
—
MHz
ns
Propagation delay
CPn to Q7
tPLH
tPHL
tPHL
1.0
1.0
10
5
13.0
12.0
Propagation delay
CPn to Q7
Propagation delay
MR to Q7
Note: 1. Voltage Range 5.0 is 5.0 V ±
AC Operating Require
Ta = –40°C
to +85°C
CL = 50 pF
Ta = +25°C
CL = 50 pF
Item
)*1
Typ
Guaranteed Minimum
Unit
Setup time
PE or Pn or DS to CPn
Hold time
CPn to PE or Pn or DS
Pulse width
CPn or MR
Recovery time
5.0
5.0
5.0
2.5
0.0
7.0
8.0
1.5
8.0
0.5
ns
1.5
7.0
0.5
tw
4.5
trec
–2.5
MR to CPn
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Symbol
Typ
Unit
Condition
CIN
4.5
pF
pF
VCC = 5.5 V
VCC = 5.0 V
Power dissipation capacitance
CPD
35.0
Rev.2.00, Jul.16.2004, page 6 of 8
HD74AC166/HD74ACT166
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
9
16
1
8
+ 0.20
7.80
– 0.30
0.80 Max
1.15
0˚ – 8˚
1.27
0.70 ± 0.20
*0.40 ± 0.06
0.15
M
0.12
orms
24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
+ 0.10
6.10
– 0.30
1.08
Max
0˚ – 8˚
+ 0.67
0.60
– 0.20
*0.40 ± 0.06
0.15
0.25
M
Package Code
JEDEC
JEITA
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
Mass (reference value)
Rev.2.00, Jul.16.2004, page 7 of 8
HD74AC166/HD74ACT166
As of January, 2003
Unit: mm
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
0.65 Max
1.0
*0.20 ± 0.05
6.40 ± 0.20
0˚ – 8˚
0.50 ± 0.10
0.10
Packag
JEDE
16DAV
JE
*Ni/Pd/Au plating
Rev.2.00, Jul.16.2004, page 8 of 8
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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