HIP0051IBT [RENESAS]
0.85A BUF OR INV BASED PRPHL DRVR, PDSO20;
| 型号： | HIP0051IBT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 0.85A BUF OR INV BASED PRPHL DRVR, PDSO20 驱动 光电二极管 接口集成电路 |
| 文件： | 总5页 (文件大小：30K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP0051
0.25A/50V Octal Low Side Power Driver
with Serial Bus Control
June 1996
Features
Description
• Eight Open Drain - NDMOS Low Side Drivers Each
Capable of 250mA
The HIP0051 is a logic controlled, eight channel Octal Low
Side Power Driver. As shown in the Block Diagram, the
outputs are controlled via the serial data interface which
allows the data to be shifted out, allowing control of other
cascaded serial devices.
• High Voltage Power BiMOS with Low Idle and Standby
Current
• Over-Voltage Clamp Protection
The HIP0051 is fabricated in a Power BiMOS IC process,
and is intended for use in automotive and other applications
having a wide range of temperature and electrical stress
conditions. It is particularly suited for driving lamps, displays,
relays, and solenoids in applications where low operating
power, high breakdown voltage, and high output current at
high temperature is required.
- Each Output . . . . . . . . . . . . . . . . . . . . . . . 50V Typical
• Serial Data Input, Parallel Output Power Drive
• Common Enable for Output Drivers and Data Storage
Register
o
o
• -40 C to 85 C Operating Range
Ordering Information
Applications
PART
NUMBER
TEMP.
RANGE ( C)
PKG.
NO.
o
• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
• Logic and µP Controlled Drivers
• Robotic Controls
PACKAGE
20 Ld SOIC
HIP0051IB
-40 to 85
M20.3
Pinout
Block Diagram
HIP0051
(SOIC)
TOP VIEW
OUTPUT DRIVER
(CHANNEL 1 OF 8)
(ENABLE)
(STROBE)
EN
DR#0
1
2
3
4
5
6
7
8
9
GND
GND
20
19
STR
V
LGND
CC
Q0
SI
DR0
DR1
DR2
DR3
NC
18 SO
OUTPUT
LATCH
SI
SCK
SO
8-BIT
SERIAL
(SPI)
17 DR7
16 DR6
15 DR5
14 DR4
13 SCK
Q1
Q2
Q3
Q4
Q5
Q6
Q7
INPUT
REGISTER
(DATA IS
PARALLEL
OUTPUT
LATCHED
WHEN
12
EN
STR
STROBED)
GND 10
11 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4155
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Specifications HIP0051
Absolute Maximum Ratings
Thermal Information
o
Output Voltage, V
(Note 1). . . . . . . . . . . . . . . . . . . -0.3V to 40V
. . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
Thermal Resistance (Typical, Note 3)
θJA ( C/W)
OUT
Input Voltage, V
IN
CC
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
o
Logic Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Output Clamp Energy, 25 C (5ms Pulse). . . . . . . . . . . . . . . . . 75mJ
Continuous Output Load Current, I
Continuous Output Current, I
Peak Output Current
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C
o
o
o
Maximum Storage Temperature Range, T
. . . . -55 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
(SOIC Lead Tips Only)
STG
o
(Each Output) . . . . .0.25A
LOAD
(All Outputs ON, Note 2). .1.69A
LOAD
Each Output, Other Outputs OFF . . . . . . . . . . . . . . . . . . . . . ±2A
Peak Avalanche Current (3ms duration) . . . . . . . . . . . . . . . . . . 1A
Operating Conditions
o
o
Operating Ambient Temperature Range, T . . . . . . . -40 C to 85 C
A
Operating Logic Supply Voltage Range, V
. . . . . +4.5V to +5.5V
CC
Power Output Driver Voltage Range. . . . . . . . . . . . . . . . . . 0 to V
OC
Max. Supply Current, with 100mA each Output . . . . . . . . . . . 100µA
Max. Supply Current, with No Load, Outputs OFF. . . . . . . . . 100µA
Logic Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7xV
Logic Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2xV
CC
CC
Typical Output R
Channel Resistance. . . . . . . . . . . . . . . . . 2Ω
DSON
Typical Output Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4µs
Typical Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µs
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the
Output Clamp voltage V
.
OC
o
2. The maximum continuous current with all outputs on is limited by package dissipation. At 25 C ambient temperature, the maximum equal
o
current with all outputs ON is 211mA in each output for a total of 1.69A. At a maximum ambient temperature of T = 85 C and
A
r
(Max) = 3.5Ω, each output is limited to 152mA and the total current for all 8 outputs ON is 8 x 152mA = 1.22A.
DSON
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
o
Electrical Specifications
V
= 4.5V to 5.5V, V
= 8V to 16V, T = -40 C to 85 C, Unless Otherwise Specified.
CC
BATT
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
Output Clamping Voltage
o
r
Output Current = 200mA, T = 85 C
A
2
50
190
-
3.5
58
Ω
V
DS(ON)
V
Outputs OFF
o
42
75
OC
Output Clamping Energy
E
5ms Pulse, T = 25 C
A
mJ
A
OC
Peak Output Load Currents,
Short Duration
I
100µs Duration, Each Output, all
Outputs ON, Duty Cycle ≤ 2%
0.85
-
-
PEAK
Cold Start-up Lamp Currents
I
5ms Duration, Each Output, all
0.3
-
A
LAMP
Outputs ON, Duty Cycle ≤ 17%
o
Output OFF Leakage Current
Output Rise Time
I
Output Voltage = 40V, T = 85 C
A
-
-0.2
4
10
30
30
10
µA
µs
µs
µs
OFF
t
Load = 75Ω, 0.01µF (RC in Parallel),
0.5
0.5
1
rise
V
= 18V
BATT
Output Fall Time
t
10
4
fall
Output Delay from Strobe, High to
Low Output Transition
t
t
DHL
Output Delay from Strobe, Low to
High Output Transition
0.2
2.6
10
µs
DLH
LOGIC SUPPLY
Logic Supply Current, Loaded
I
I
All Outputs ON, 200mA Load at each
Output
-
-
-
-
100
100
µA
µA
CC
Logic Supply Current, No Load
All Outputs OFF
CC
2
Specifications HIP0051
o
o
Electrical Specifications
V
= 4.5V to 5.5V, V
= 8V to 16V, T = -40 C to 85 C, Unless Otherwise Specified. (Continued)
CC
BATT
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (EN, SI, SCK, STR)
Threshold Voltage at Falling Edge
Threshold Voltage at Rising Edge
Hysteresis Voltage
V
V
V
V
V
V
= 5V ± 10%
= 5V ± 10%
0.2V
0.3V
-
V
V
T-
CC
CC
T+
CC
CC
CC
V
-
0.6V
0.7V
CC
T+
V
- V
0.85
-10
-10
1.4
-0.2
-0.1
2.25
10
V
H
T-
Leakage Current
I
I
= 5V
= 0V
µA
µA
LIN
LIN
CC
CC
Leakage Current
10
SERIAL DATA CLOCK (SCK)
Frequency
f
-
-
1.6
MHz
ns
SCK
Pulse Width High
t
175
175
27
27
-
-
W(CKH)
Pulse Width Low
t
ns
W(CKL)
SERIAL DATA IN (SI)
Input Setup Time
t
-
-
1.1
1.5
75
75
ns
ns
SUI
Input Hold Time
T
HI
STROBE (STR)
Strobe Pulse Width
t
150
75
12
5
-
-
ns
ns
W(S)
Min. Clock to Strobe Delay
SERIAL DATA OUT (SO)
Low Level Output Voltage
High Level Output Voltage
Propagation Delay
t
D(CS)
V
Sink Current = 1.6mA
-
0.2
4.4
260
0.4
V
V
OL
V
Source Current = -1.6mA
3.7
75
-
-
OH
t
ns
P(CD)
t
t
W(SCK)
W(SCK)
SCK (CLOCK)
SI (SERIAL DATA IN)
STR (STROBE)
t
t
HI
SUI
t
t
W(S)
D(CS)
t
DHL
t
DLH
90%
10%
DRx
(POWER OUTPUT DRIVER)
t
P(CD)
t
, t
fall rise
SO (SERIAL DATA OUT)
FIGURE 1. LOGIC TIMING CONTROL SPECIFICATIONS
3
HIP0051
Pin Descriptions
V
- Logic Power Supply
SO - Serial Data Out
CC
The V
pin is the positive 5V logic voltage supply input for The Serial Data Out allows other ICs to be serially
CC
the IC. The normal operating voltage range is 4.5 to 5.5V. cascaded. For example, a 10-bit LED driver may be located
When switched on, the POR forces all outputs off.
behind the HIP0051. A controlling microprocessor may then
clock out 18 bits of information and simultaneously strobe
both parts. The cascaded ICs may be the same or different
from the HIP0051.
SCK - Serial Clock
SCK is the clock input for the SPI interface. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schmitt
trigger.
DR0 to DR7 - Outputs 0 Thru 7
The Drain Output pins of the DMOS Power Drivers are
capable of sinking 250mA.
SI - Serial Data In
EN - Enable
SI is the Serial Data Input pin for the SPI interface. The eight
Power Outputs are controlled by the serial data via the The Enable pin is an active low enable function for all eight
Output Data Buffer. This input has a Schmitt trigger.
output drivers. When EN is high, drive from the Output Data
Buffer is held low and all output drivers are disabled. When
EN is low, the output drivers are enabled and data in the
8-bit shift register is transparent to the Output Data Buffer.
This input has a Schmitt trigger.
STR - Strobe for the SPI Interface
When the STR pin is high, data from the 8-bit shift register is
passed into the Output Data Buffers where it controls the
ON-OFF state of each output driver. The data is latched in
the Output Data Buffers on the trailing edge of the STR
pulse. This input has a Schmitt trigger.
LGND and GND - Ground
LGND is the logic input power supply ground pin. The GND
pins are common grounds for the Power Output Drivers. The
power supplies for the logic and power circuits require a
common ground. To minimize ground bounce at the logic
input, the external ground return path for the GND pin should
be separate from the LGND pin. LGND and GND have com-
mon substrate ground connections on the chip.
OUTPUT CONTROL TABLE
8-BIT SERIAL DATA (LATCHED)
STROBE
OUTPUT
D1
0
D2
0
D3
0
D4
0
D5
0
D6
0
D7
0
D8
0
DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8
OFF OFF OFF OFF OFF OFF OFF OFF
1
0
0
0
0
0
0
0
ON
ON
ON
ON
OFF OFF OFF OFF OFF OFF OFF
1
1
0
0
0
0
0
0
ON
ON
ON
OFF OFF OFF OFF OFF OFF
1
1
1
0
0
0
0
0
ON
ON
OFF OFF OFF OFF OFF
ON OFF OFF OFF OFF
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
OFF OFF OFF OFF
ON ON ON ON
ON
ON
ON
ON
ON
ON
ON
ON
1
1
1
1
1
1
1
1
4
HIP0051
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.4961
0.2914
0.32
-
-A-
0.5118 12.60
13.00
7.60
3
o
D
h x 45
0.2992
7.40
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
M
M
S
B
0.25(0.010)
C
A
N
α
20
20
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
5
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