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HIP2106IBT [RENESAS]

1A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, MS-012-AA, SOIC-8;
HIP2106IBT
型号： HIP2106IBT
厂家： RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述：

1A HALF BRDG BASED MOSFET DRIVER, PDSO8, PLASTIC, MS-012-AA, SOIC-8

驱动 光电二极管 接口集成电路 驱动器
文件： 总8页 (文件大小：66K)
中文：  中文翻译
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HIP2106  
Data Sheet  
August 1999  
File Number 4406.2  
100V/1A Peak, Low Cost, High Frequency  
Half Bridge Driver  
Features  
• Drives N-Channel MOSFET Half Bridge  
• Space Saving SO8 Package  
The HIP2106 is a high frequency, 100V Half Bridge  
N-Channel MOSFET driver IC, available in 8 lead plastic  
SOIC. The low-side and high-side gate drivers are  
• Bootstrap Supply Max Voltage to 116V  
DC  
independently controlled and matched to 8ns. This gives the  
user maximum flexibility in dead-time selection and driver  
protocol. Undervoltage protection on both the low-side and  
high-side supplies force the outputs low. An on-chip diode  
eliminates the discrete diode required with other driver ICs. A  
new levelshifter topology yields the low-power benefits of  
pulsed operation with the safety of DC operation. Unlike some  
competitors, the high-side output returns to its correct state  
after a momentary undervoltage of the high-side supply.  
• On-Chip 1Ω Bootstrap Diode  
• Fast Propagation Times Needed for Multi-MHz Circuits  
• Drives 1000pF Load at 500kHz with Rise and Fall Times  
of Typically 20ns  
• CMOS Input Thresholds for Improved Noise Immunity  
• Independent Inputs for Non-Half Bridge Topologies  
• No Start-Up Problems  
• Outputs Unaffected by Supply Glitches, HS Ringing Below  
Ground, or HS Slewing at High dv/dt  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
• Low Power Consumption  
• Wide Supply Range  
PART NUMBER  
HIP2106IB  
RANGE ( C)  
PACKAGE  
8 Ld SOIC  
8 Ld PDIP  
-40 to 85  
M8.15  
E8.3  
• Supply Undervoltage Protection  
• 3Ω Output Resistance  
HIP2106IP  
-40 to 85  
Pinout  
HIP2106 (SOIC, PDIP)  
Applications  
TOP VIEW  
• Telecom Half Bridge Power Supplies  
• Avionic DC-DC Converters  
• Two-Switch Forward Converters  
• Active Clamp Forward Converters  
1
2
3
4
8
7
6
5
LO  
V
V
DD  
HB  
HO  
HS  
SS  
LI  
HI  
Application Block Diagram  
+12V  
+100V  
V
DD  
HB  
SECONDARY  
CIRCUIT  
DRIVE  
HI  
HO  
HS  
LO  
HI  
LI  
PWM  
CONTROLLER  
DRIVE  
LO  
REFERENCE  
AND  
HIP2106  
ISOLATION  
V
SS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
1
HIP2106  
Functional Block Diagram  
2
3
HB  
HO  
1
5
V
UNDER  
VOLTAGE  
DD  
HI  
LEVEL SHIFT  
DRIVER  
4
HS  
UNDER  
VOLTAGE  
8
LO  
DRIVER  
6
7
LI  
V
SS  
Other Applications  
+48V  
+12V  
SECONDARY  
CIRCUIT  
HIP  
2106  
PWM  
ISOLATION  
FIGURE 1. TWO-SWITCH FORWARD CONVERTER  
+48V  
SECONDARY  
CIRCUIT  
+12V  
HIP  
2106  
PWM  
ISOLATION  
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP  
2
HIP2106  
Absolute Maximum Ratings  
Thermal Information  
o
Supply Voltage, V  
V
-V  
. . . . . . . . . . . . . . . . . . .-0.3V to 18V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
DD, HB HS  
JA  
LI and HI Voltages . . . . . . . . . . . . . . . . . . . . . . . . .-3V to V  
Voltage on LO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V  
+0.3V  
+0.3V  
+0.3V  
DD  
DD  
HB  
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
160  
100  
Voltage on HO . . . . . . . . . . . . . . . . . . . . . . V  
-0.3V to V  
HS  
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/ns  
o
Voltage on HS (Continuous) . . . . . . . . . . . . . . . . . . . . . -1V to 110V  
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V  
Maximum Power Dissipation at 25 C in Free Air. . . . . . . . . .780mW  
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Junction Temperature Range . . . . . . . . . -55 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C  
o
o
Average Current in V  
to HB Diode. . . . . . . . . . . . . . . . . . . 100mA  
DD  
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)  
(Lead Tips Only)  
Recommended Operating Conditions  
Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . . +9V to +16.5V  
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V  
Voltage on HS . . . . . . . . . . . . . . . (Repetitive Transient) -5V to 105V  
DD  
Voltage on HB. . . V +8V to V +16.5V and V  
HS HS DD  
-1V to V +100V  
DD  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTES:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
2. All Voltages Relative to Pin 4, V Unless Otherwise Specified.  
SS  
Electrical Specifications  
V
= V  
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified  
HB SS HS  
DD  
o
T = -40 C  
J
TO 125 C  
o
o
T
= 25 C  
J
PARAMETER  
SUPPLY CURRENTS  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP MAX  
MIN  
MAX UNITS  
V
V
Quiescent Current  
Operating Current  
I
LI = HI = 0V  
f = 500kHz  
LI = HI = 0V  
f = 500kHz  
-
-
-
-
-
-
0.1  
1.5  
0.15  
2.5  
0.15  
2.5  
1
-
-
-
-
-
-
0.2  
3
mA  
mA  
mA  
mA  
µA  
DD  
DD  
DD  
I
I
DDO  
Total HB Quiescent Current  
Total HB Operating Current  
I
0.1  
0.2  
3
HB  
HBO  
1.5  
HB to V Current, Quiescent  
SS  
I
V
= V  
HB  
= 116.5V  
0.05  
0.7  
10  
-
HBS  
HS  
f = 500kHz  
HB to V Current, Operating  
SS  
I
-
mA  
HBSO  
INPUT PINS  
Low Level Input Voltage Threshold  
V
4
-
5.4  
5.8  
0.4  
200  
-
8
-
3
-
9
V
V
IL  
High Level Input Voltage Threshold  
Input Voltage Hysteresis  
V
-
-
IH  
V
-
-
V
IHYS  
Input Pulldown Resistance  
R
-
-
100  
500  
kΩ  
I
UNDER VOLTAGE PROTECTION  
V
V
Rising Threshold  
V
V
V
V
7
-
7.3  
0.5  
6.9  
0.4  
8
-
6.5  
8.5  
V
V
V
V
DD  
DD  
DDR  
DDH  
HBR  
HBH  
Threshold Hysteresis  
-
6
-
-
8
-
HB Rising Threshold  
6.5  
-
7.5  
-
HB Threshold Hysteresis  
BOOT STRAP DIODE  
Low-Current Forward Voltage  
High-Current Forward Voltage  
Dynamic Resistance  
V
I
I
I
= 100µA  
-
-
-
0.45  
0.7  
0.55  
0.8  
1
-
-
-
0.7  
1
V
V
Ω
DL  
VDD-HB  
VDD-HB  
VDD-HB  
V
= 100mA  
= 100mA  
DH  
R
0.8  
1.5  
D
LO GATE DRIVER  
Low Level Output Voltage  
High Level Output Voltage  
Peak Pullup Current  
V
I
I
= 100mA  
-
-
-
-
0.25  
0.25  
1
0.3  
0.3  
-
-
-
-
-
0.4  
0.4  
-
V
V
A
A
OLL  
LO  
LO  
V
= -100mA, V  
OHL  
= V -V  
DD LO  
OHL  
I
V
V
= 0V  
OHL  
LO  
LO  
Peak Pulldown Current  
HO GATE DRIVER  
I
= 12V  
1
-
-
OLL  
Low Level Output Voltage  
High Level Output Voltage  
Peak Pullup Current  
V
I
I
= 100mA  
-
-
-
0.25  
0.25  
1
0.3  
0.3  
-
-
-
-
0.4  
0.4  
-
V
V
A
OLH  
HO  
HO  
V
= -100mA, V  
OHH  
= V -V  
HB HO  
OHH  
I
V
= 0V  
HO  
OHH  
3
HIP2106  
Electrical Specifications  
V
= V  
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)  
HB SS HS  
DD  
o
T = -40 C  
J
TO 125 C  
o
o
T
= 25 C  
J
PARAMETER  
Peak Pulldown Current  
SYMBOL  
TEST CONDITIONS  
= 12V  
HO  
MIN  
TYP MAX  
MIN  
MAX UNITS  
I
V
-
1
-
-
-
A
OLH  
Switching Specifications V = V = 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified  
DD  
HB  
SS  
HS  
o
T
= - 40 C  
J
o
o
T
= 25 C  
TO 125 C  
J
TEST  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN TYP MAX MIN MAX UNITS  
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)  
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)  
Lower Turn-On Propagation Delay (LI Rising to LO Rising)  
Upper Turn-On Propagation Delay (HI Rising to HO Rising)  
Delay Matching: Lower Turn-On and Upper Turn-Off  
Delay Matching: Lower Turn-Off and Upper Turn-On  
Either Output Rise/Fall Time  
t
-
-
-
-
-
-
-
-
-
-
-
-
40  
40  
40  
40  
4
70  
70  
70  
70  
16  
16  
-
-
-
-
-
-
-
-
-
-
-
-
-
90  
90  
90  
90  
20  
20  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
ns  
ns  
ns  
ns  
LPHL  
t
HPHL  
t
LPLH  
HPLH  
t
t
MON  
t
4
MOFF  
, t  
t
C = 1000pF  
20  
1.0  
40  
20  
-
RC FC  
L
Either Output Rise/Fall Time (3V to 9V)  
t , t  
C = 0.1µF  
1.2  
-
1.6  
-
R
F
L
Either Output Rise Time Driving DMOS  
t
C = IRFR120  
L
RD  
Either Output Fall Time Driving DMOS  
t
C = IRFR120  
L
-
-
FD  
Minimum Input Pulse Width that Changes the Output  
Bootstrap Diode Turn-On or Turn-Off Time  
t
-
100  
-
PW  
t
20  
-
BS  
Pin Descriptions  
PIN  
NUMBER  
SYMBOL  
DESCRIPTION  
1
2
V
Positive Supply to lower gate drivers. De-couple this pin to V (Pin 7). Bootstrap diode connected to HB (pin 2).  
SS  
DD  
HB  
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to  
this pin. Bootstrap diode is on-chip.  
3
4
HO  
HS  
High-Side Output. Connect to gate of High-Side power MOSFET.  
High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap  
capacitor to this pin.  
5
6
7
8
HI  
LI  
High-Side input.  
Low-Side input.  
V
Chip negative supply, generally will be ground.  
Low-Side Output. Connect to gate of Low-Side power MOSFET.  
SS  
LO  
Timing Diagrams  
LI  
HI,  
LI  
HI  
t
t
,
t
t
,
HPLH  
HPHL  
LPHL  
LO  
HO  
LPLH  
t
t
MOFF  
MON  
HO,  
LO  
FIGURE 3.  
FIGURE 4.  
4
HIP2106  
Typical Performance Curves  
10  
10  
1
0.1  
1
o
T = 150 C  
o
o
T = -40 C  
T = 150 C  
0.1  
o
T = 125 C  
o
T = 25 C  
o
T = -40 C  
o
T = 25 C  
o
T = 125 C  
0.01  
0.01  
10  
50  
100  
500  
10  
100  
1000  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
FIGURE 5. OPERATING CURRENT vs FREQUENCY  
500  
FIGURE 6. LEVEL SHIFTER CURRENT vs FREQUENCY  
500  
V
= V  
= 9V  
V
= V  
= 9V  
DD  
HB  
DD  
HB  
V
= V  
= 12V  
= 14V  
V
= V  
= 12V  
= 14V  
400  
300  
200  
100  
400  
300  
200  
100  
HB  
DD  
HB  
HB  
DD  
DD  
V
= V  
V
= V  
HB  
DD  
V
= V  
= 16.5V  
V
= V  
= 16.5V  
DD  
HB  
DD  
HB  
-50  
0
50  
TEMPERATURE ( C)  
100  
150  
-50  
0
50  
TEMPERATURE ( C)  
100  
150  
o
o
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE  
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE  
7.6  
7.4  
0.54  
0.5  
V
DDH  
V
V
DDR  
HBR  
0.46  
0.42  
0.38  
0.34  
0.3  
7.2  
7.0  
6.8  
6.6  
V
HBH  
-50  
0
50  
100  
150  
-50  
0
50  
TEMPERATURE ( C)  
100  
150  
o
o
TEMPERATURE ( C)  
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs  
TEMPERATURE  
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs  
TEMPERATURE  
5
HIP2106  
Typical Performance Curves (Continued)  
60  
2.5  
2.0  
1.5  
1.0  
0.5  
0
t
t
HPHL  
HPLH  
t
LPHL  
LPLH  
50  
40  
30  
t
0
2
4
6
8
10  
12  
-50  
0
50  
TEMPERATURE ( C)  
100  
150  
o
V
, V  
(V)  
HO LO  
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE  
FIGURE 12. PULLUP CURRENT vs OUTPUT VOLTAGE  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1
0.1  
0.01  
0.001  
-4  
1•10  
-5  
1•10  
-6  
0.3  
1•10  
0
2
4
6
8
10  
12  
0.4  
0.5  
0.6  
0.7  
0.8  
V
, V (V)  
LO HO  
FORWARD VOLTAGE (V)  
FIGURE 13. PULLDOWN CURRENT vs OUTPUT VOLTAGE  
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS  
60  
50  
I
vs V  
HB  
HB  
40  
30  
20  
10  
0
I
vs V  
DD  
DD  
0
5
10  
(V)  
15  
V
, V  
DD HB  
FIGURE 15. BIAS CURRENT vs VOLTAGE  
6
HIP2106  
Dual-In-Line Plastic Packages (PDIP)  
E8.3 (JEDEC MS-001-BA ISSUE D)  
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
E1  
INDEX  
AREA  
INCHES  
MILLIMETERS  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.210  
-
MIN  
-
MAX  
5.33  
-
NOTES  
-B-  
-C-  
A
A1  
A2  
B
-
4
-A-  
D
E
0.015  
0.115  
0.014  
0.045  
0.008  
0.355  
0.005  
0.300  
0.240  
0.39  
2.93  
0.356  
1.15  
0.204  
9.01  
0.13  
7.62  
6.10  
4
BASE  
PLANE  
0.195  
0.022  
0.070  
0.014  
0.400  
-
4.95  
0.558  
1.77  
0.355  
10.16  
-
-
A2  
A
-
SEATING  
PLANE  
L
C
L
B1  
C
8, 10  
D1  
B1  
eA  
-
A
1
D1  
e
D
5
eC  
C
B
eB  
D1  
E
5
0.010 (0.25) M  
C
A B S  
0.325  
0.280  
8.25  
7.11  
6
NOTES:  
E1  
e
5
1. Controlling Dimensions: INCH. In case of conflict between  
0.100 BSC  
0.300 BSC  
2.54 BSC  
7.62 BSC  
-
English and Metric dimensions, the inch dimensions control.  
e
e
6
A
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
-
0.430  
0.150  
-
10.92  
3.81  
7
3. Symbols are defined in the “MO Series Symbol List” in Section  
2.2 of Publication No. 95.  
B
L
0.115  
2.93  
4
9
4. Dimensions A, A1 and L are measured with the package seated  
N
8
8
in JEDEC seating plane gauge GS-3.  
Rev. 0 12/93  
5. D, D1, and E1 dimensions do not include mold flash or  
protrusions. Mold flash or protrusions shall not exceed 0.010  
inch (0.25mm).  
e
6. E and  
perpendicular to datum  
7. e and e are measured at the lead tips with the leads  
are measured with the leads constrained to be  
A
-C-  
.
B
C
unconstrained. e must be zero or greater.  
C
8. B1 maximum dimensions do not include dambar protrusions.  
Dambar protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,  
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch  
(0.76 - 1.14mm).  
7
HIP2106  
Small Outline Plastic Packages (SOIC)  
M8.15 (JEDEC MS-012-AA ISSUE C)  
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC  
PACKAGE  
N
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
E
INCHES  
MILLIMETERS  
-B-  
SYMBOL  
MIN  
MAX  
MIN  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
NOTES  
A
A1  
B
C
D
E
e
0.0532  
0.0040  
0.013  
0.0688  
0.0098  
0.020  
-
1
2
3
L
-
9
SEATING PLANE  
A
0.0075  
0.1890  
0.1497  
0.0098  
0.1968  
0.1574  
-
-A-  
o
h x 45  
D
3
4
-C-  
α
0.050 BSC  
1.27 BSC  
-
e
A1  
H
h
0.2284  
0.0099  
0.016  
0.2440  
0.0196  
0.050  
5.80  
0.25  
0.40  
6.20  
0.50  
1.27  
-
C
B
0.10(0.004)  
5
0.25(0.010) M  
C
A M B S  
L
6
N
α
8
8
7
NOTES:  
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication Number 95.  
Rev. 0 12/93  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate burrs.  
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006  
inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions.  
Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)  
per side.  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater  
above the seating plane, shall not exceed a maximum value of  
0.61mm (0.024 inch).  
10. Controlling dimension: MILLIMETER. Converted inch dimensions  
are not necessarily exact.  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (407) 724-7000  
FAX: (407) 724-7240  
8

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