HIP6004BCVZA-T [RENESAS]
Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor HIP6004B; SOIC20, TSSOP20; Temp Range: 0° to 70°;
| 型号： | HIP6004BCVZA-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor HIP6004B; SOIC20, TSSOP20; Temp Range: 0° to 70° 输入元件 开关 光电二极管 |
| 文件： | 总15页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
HIP6004B
FN4567
Rev 3.00
November 9, 2004
Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
The HIP6004B provides complete control and protection for
a DC-DC converter optimized for high-performance
Features
• Drives Two N-Channel MOSFETs
• Operates from +5V or +12V Input
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004B integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004B includes a fully
TTL-compatible 5-input digital-to-analog converter (DAC)
that adjusts the output voltage from 1.3V
to 2.05V
in
DC
• Excellent Output Voltage Regulation
DC
in 0.1V increments steps.
0.05V and from 2.1V
to 3.5V
- 1% Over Line Voltage and Temperature
DC
DC
The precision reference and voltage-mode regulator hold the
selected output voltage to within 1% over temperature and
line voltage variations.
• TTL-Compatible 5-Bit Digital-to-Analog Output
Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . . 1.3V
- 0.1V Binary Steps . . . . . . . . . . . . . . 2.1V
to 3.5V
to 3.5V
DC
DC
DC
DC
DC
The HIP6004B provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/s slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
- 0.05V Binary Steps . . . . . . . . . . . . 1.3V
to 2.05V
DC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element,
Uses MOSFET’s r
DS(ON)
• Small Converter Size
The HIP6004B monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within 10%. The HIP6004B
protects against over-current and overvoltage conditions by
inhibiting PWM operation. Additional built-in overvoltage
protection triggers an external SCR to crowbar the input
supply. The HIP6004B monitors the current by using the
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
r
of the upper MOSFET which eliminates the need for
DS(ON)
a current sensing resistor.
• Pb-Free Available (RoHS Compliant)
Applications
• Power Supply for Pentium®, Pentium Pro, Pentium II,
PowerPC™, K6™, 6X86™ and Alpha™ Microprocessors
•
•
High-Power 5V to 3.xV DC-DC Regulators
Low-Voltage Distributed Power Supplies
FN4567 Rev 3.00
November 9, 2004
Page 1 of 15
HIP6004B
HIP6004B
Pinouts
HIP6004B (SOIC, TSSOP)
HIP6004B (QFN)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
RT
V
20
19
SEN
OCSET
SS
OVP
20 19 18 17 16
18 V
CC
VID0
VID1
VID2
VID3
VID4
VCC
1
2
3
4
5
15
14
13
12
11
VID0
VID1
VID2
VID3
VID4
COMP
17 LGATE
16 PGND
LGATE
PGND
BOOT
UGATE
15
BOOT
GND
21
14 UGATE
13 PHASE
12
PGOOD
FB 10
11 GND
6
7
8
9
10
Ordering Information
TEMP.
PKG.
PART NUMBER
RANGE (°C)
PACKAGE
DWG. #
HIP6004BCB*
0 to 70
20 Ld SOIC
M20.3
HIP6004BCBZ*
(See Note)
0 to 70
20 Ld SOIC
(Pb-free)
M20.3
HIP6004BCV*
0 to 70
0 to 70
20 Ld TSSOP
M20.173
M20.173
HIP6004BCVZ*
(See Note)
20 Ld TSSOP
(Pb-free)
HIP6004BCVZA*
(See Note)
20 Ld TSSOP Tape and Reel
(Pb-free)
M20.173
HIP6004BCR*
0 to 70
0 to 70
20 Ld 5x5 QFN
L20.5x5
L20.5x5
HIP6004BCRZ*
(See Note)
20 Ld 5x5 QFN
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020C.
FN4567 Rev 3.00
November 9, 2004
Page 2 of 15
HIP6004B
HIP6004B
Typical Application
+12V
V
= +5V OR +12V
IN
VCC
PGOOD
OCSET
EN
MONITOR AND
PROTECTION
SS
OVP
BOOT
RT
OSC
UGATE
PHASE
VID0
VID1
VID2
VID3
VID4
+V
HIP6004B
OUT
D/A
LGATE
PGND
-
+
+
-
FB
COMP
GND
VSEN
Block Diagram
V
CC
V
SEN
POWER-ON
110%
RESET (POR)
+
-
PGOOD
90%
+
-
OVER-
VOLTAGE
10A
115%
+
-
OVP
SS
SOFT-
START
+
-
OCSET
OVER-
CURRENT
BOOT
REFERENCE
UGATE
200A
4V
PHASE
PWM
COMPARATOR
VID0
VID1
VID2
VID3
VID4
TTL D/A
CONVERTER
(DAC)
DACOUT
GATE
CONTROL
LOGIC
INHIBIT
PWM
+
-
+
-
ERROR
AMP
LGATE
PGND
GND
FB
COMP
RT
OSCILLATOR
FN4567 Rev 3.00
November 9, 2004
Page 3 of 15
HIP6004B
HIP6004B
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Thermal Resistance
JA ( C/W) JC ( C/W)
CC
Boot Voltage, V
- V
. . . . . . . . . . . . . . . . . . . . . . . .+15V
BOOT
PHASE
SOIC Package (Note 1) . . . . . . . . . . . .
TSSOP Package (Note 1) . . . . . . . . . .
QFN Package (Notes 2, 3). . . . . . . . . .
65
85
33
NA
NA
5
Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.3V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
+0.3V
CC
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
Operating Conditions
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
CC
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
(Lead Tips Only)
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
SUPPLY CURRENT
CC
Nominal Supply
I
UGATE and LGATE Open
-
5
-
mA
CC
POWER-ON RESET
Rising V
Threshold
Threshold
V
V
= 4.5V
-
8.2
-
-
-
10.4
V
V
V
CC
OCSET
OCSET
Falling V
= 4.5V
-
-
CC
Rising V
Threshold
1.26
OCSET
OSCILLATOR
Free Running Frequency
Total Variation
185
-15
-
200
-
215
+15
-
kHz
%
RT = OPEN
6k < RT to GND < 200k
Ramp Amplitude
V
OSC
RT = Open
1.9
V
P-P
REFERENCE AND DAC
DAC (VID0-VID4) Input Low Voltage
DAC (VID0-VID4) Input High Voltage
DACOUT Voltage Accuracy
ERROR AMPLIFIER
DC Gain
-
-
-
-
0.8
-
V
V
2.0
-1.0
+1.0
%
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/s
COMP = 10pF
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
I
V
- V
= 12V, V = 6V
UGATE
350
500
5.5
450
3.5
-
10
-
mA
UGATE
BOOT
PHASE
R
I
= 0.3A
-
300
-
UGATE
LGATE
Lower Gate Source
Lower Gate Sink
I
V
= 12V, V
= 6V
mA
LGATE
CC
LGATE
R
I
= 0.3A
6.5
LGATE
LGATE
PROTECTION
Over-Voltage Trip (V
/DACOUT)
-
170
60
-
115
200
-
120
%
µA
mA
µA
SEN
OCSET Current Source
OVP Sourcing Current
Soft Start Current
I
V
V
= 4.5V
230
OCSET
OCSET
DC
I
= 5.5V, V
= 0V
-
-
OVP
SEN
OVP
I
10
SS
FN4567 Rev 3.00
November 9, 2004
Page 4 of 15
HIP6004B
HIP6004B
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
POWER GOOD
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Upper Threshold (V
Lower Threshold (V
/DACOUT)
/DACOUT)
V
V
Rising
Falling
106
-
-
111
%
%
%
V
SEN
SEN
SEN
89
-
94
-
SEN
Hysteresis (V
/DACOUT)
Upper and Lower Threshold
2
SEN
PGOOD Voltage Low
V
I
= -5mA
-
0.5
-
PGOOD
PGOOD
Typical Performance Curves
80
70
60
50
40
C
= 3300pF
GATE
1000
R
PULLUP
TO +12V
T
C
= C
= C
LOWER GATE
UPPER
100
10
C
= 1000pF
GATE
30
20
10
0
R
PULLDOWN TO V
SS
T
C
= 10pF
800
GATE
100 200
300
400
500
600
700
900 1000
10
100
SWITCHING FREQUENCY (kHz)
1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
T
the converter over-current (OC) trip point according to the
following equation:
Functional Pin Descriptions
1
2
3
4
5
6
7
8
9
RT
V
20
19
SEN
I
x R
OCSET
OCSET
I
= ----------------------------------------------------
OCSET
SS
OVP
PEAK
r
DSON
18 VCC
VID0
VID1
VID2
VID3
VID4
COMP
17 LGATE
16 PGND
15 BOOT
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10A current source, sets the soft-
start interval of the converter.
14
UGATE
13 PHASE
12
PGOOD
VID0-4 (Pins 4-8)
FB 10
11 GND
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the all combinations of DAC inputs.
V
(Pin 1)
SEN
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
COMP (Pin 9) and FB (Pin 10)
OCSET (Pin 2)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
Connect a resistor (R
upper MOSFET. R
(I
OCS
) from this pin to the drain of the
, an internal 200A current source
OCSET
OCSET
), and the upper MOSFET on-resistance (r
) set
DS(ON)
FN4567 Rev 3.00
November 9, 2004
Page 5 of 15
HIP6004B
HIP6004B
GND (Pin 11)
Functional Description
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
Initialization
The HIP6004B automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the V
pin and the input voltage (V ) on the OCSET pin. The level on
OCSET is equal to V less a fixed voltage drop (see over-current
IN
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the status
of the converter output voltage. This pin is pulled low when the
converter output is not within 10%of the DACOUT reference
voltage. Exception to this behavior is the ‘11111’ VID pin
combination which disables the converter; in this case PGOOD
asserts a high level.
CC
IN
protection). The POR function initiates soft start operation after
both input supply voltages exceed their POR thresholds. For
operation with a single +12V power source, V and V are
IN CC
equivalent and the +12V power source must exceed the rising
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET for
over-current protection. This pin also provides the return path
for the upper gate drive.
V
threshold before POR initiates operation.
CC
Soft Start
The POR function initiates the soft start sequence. An internal
10µA current source charges an external capacitor (C ) on the
SS pin to 4V. Soft start clamps the error amplifier output (COMP
pin) and reference input (+ terminal of error amp) to the SS pin
SS
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin provides
the gate drive for the upper MOSFET.
voltage. Figure 3 shows the soft start interval with C = 0.1µF.
SS
Initially the clamp on the error amplifier (COMP pin) controls the
BOOT (Pin 15)
converter’s output voltage. At t in Figure 3, the SS voltage
1
This pin provides bias voltage to the upper MOSFET driver. A
bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
reaches the valley of the oscillator’s triangle wave. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitor(s). This interval of increasing pulse
PGND (Pin 16)
width continues to t . With sufficient output voltage, the clamp on
2
This is the power ground connection. Tie the lower MOSFET
source to this pin.
the reference input controls the output voltage. This is the interval
between t and t in Figure 3. At t the SS voltage exceeds the
2
3
3
LGATE (Pin 17)
DACOUT voltage and the output voltage is in regulation. This
method provides a rapid and controlled output voltage rise. The
Connect LGATE to the lower MOSFET gate. This pin provides
the gate drive for the lower MOSFET.
PGOOD signal toggles ‘high’ when the output voltage (V
pin)
SEN
is within 5% of DACOUT. The 2% hysteresis built into the power
good comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
V
(Pin 18)
CC
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
PGOOD
(2V/DIV)
0V
RT (Pin 20)
SOFT-START
(1V/DIV)
This pin provides oscillator switching frequency adjustment. By
placing a resistor (R ) from this pin to GND, the nominal
T
200kHz switching frequency is increased according to the
following equation:
OUTPUT
VOLTAGE
(1V/DIV)
0V
6
5 x 10
Fs 200kHz + --------------------
(R to GND)
T
R k
0V
T
t
t
t
3
1
2
Conversely, connecting a pull-up resistor (R ) from this pin to
T
TIME (5ms/DIV)
V
reduces the switching frequency according to the
CC
following equation:
FIGURE 3. SOFT START INTERVAL
7
4 x 10
Fs 200kHz – --------------------
(R to 12V)
T
R k
T
FN4567 Rev 3.00
November 9, 2004
Page 6 of 15
HIP6004B
HIP6004B
where I
is the internal OCSET current source (200A
Over-Current Protection
OCSET
typical). The OC trip point varies mainly due to the
MOSFET’s r variations. To avoid over-current
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
DS(ON)
tripping in the normal operating load range, find the R
resistor from the equation above with:
OCSET
r
to monitor the current. This method enhances the
DS(ON)
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
1. The maximum r
2. The minimum I
at the highest junction temperature.
DS(ON)
from the specification table.
OCSET
3. Determine I
for I
I
+ I 2 ,
OUTMAX
PEAK
where I is the outputPinEdAuKctor ripple current.
4V
2V
0V
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across R in the
OCSET
OCSET
15A
10A
presence of switching noise on the input voltage.
Output Voltage Program
5A
0A
The output voltage of a HIP6004B converter is programmed
to discrete levels between 1.8V
and 3.5V . The voltage
DC
DC
identification (VID) pins program an internal voltage reference
(DACOUT) with a TTL-compatible 5-bit digital-to-analog
converter (DAC). The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage
for the 32 different combinations of connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exercise
the overvoltage protection.
TIME (20ms/DIV)
FIGURE 4. OVER-CURRENT OPERATION
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the over-current trip level. An internal 200µA current
sink develops a voltage across R that is referenced to
OCSET
. When the voltage across the upper MOSFET (also
V
IN
referenced to V ) exceeds the voltage across R
over-current function initiates a soft-start sequence. The soft-
start function discharges C with a 10µA current sink and
SS
inhibits PWM operation. The soft-start function recharges
, the
IN OCSET
‘11111’ VID pin combination resulting in a 0V output setting
activates the Power-On Reset function and disables the gate
drives circuitry. For this specific VID combination, though,
PGOOD asserts a high level. This unusual behavior has been
implemented in order to allow for operation in dual-
C
, and PWM operation resumes with the error amplifier
SS
clamped to the SS voltage. Should an overload occur while
recharging C , the soft start function inhibits PWM operation
microprocessor systems where AND-ing of the PGOOD signals
from two individual power converters is implemented.
SS
while fully charging C to 4V to complete its cycle. Figure 4
SS
shows this operation with an overload condition. Note that the
Application Guidelines
inductor current increases to over 15A during the C
SS
Layout Considerations
charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
The over-current function will trip at a peak inductor current
(I
determined by:
PEAK)
I
x R
OCSET
OCSET
I
= ----------------------------------------------------
PEAK
r
DSON
FN4567 Rev 3.00
November 9, 2004
Page 7 of 15
HIP6004B
HIP6004B
TABLE 1. OUTPUT VOLTAGE PROGRAM
PIN NAME
PIN NAME
NOMINAL OUTPUT
VOLTAGE DACOUT
NOMINAL OUTPUT
VOLTAGE DACOUT
VID4
0
VID3
VID2
1
VID1
1
VID0
1
VID4
1
VID3
1
VID2
1
VID1
1
VID0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
0
0
1
1
0
1
1
1
1
0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
0
1
0
1
1
1
1
0
1
0
1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
NOTE: 0 = connected to GND or V , 1 = connected to V
SS
through pull-up resistors.
DD
the SS PIN and locate the capacitor, C close to the SS pin
SS
because the internal current source is only 10µA. Provide local
V
IN
HIP6004B
V
decoupling between V
and GND pins. Locate the
CC
CC
as close as practical to the BOOT and
capacitor, C
BOOT
PHASE pins.
UGATE
Q
Q
1
L
O
V
OUT
PHASE
+V
IN
BOOT
C
D
1
C
Q
1
IN
2
L
O
BOOT
C
LGATE
PGND
O
D
2
V
OUT
PHASE
HIP6004B
V
CC
C
+12V
SS
Q
2
O
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
C
VCC
C
SS
GND
Figure 5 shows the critical power components of the converter. To
minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power plane
in a printed circuit board. The components shown in Figure 5
should be located as close together as possible. Please note that
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
the capacitors C and C each represent numerous physical
IN
O
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V ) is regulated to the Reference voltage level. The error
capacitors. Locate the HIP6004B within 3 inches of the
MOSFETs, Q and Q . The circuit traces for the MOSFETs’ gate
1
2
and source connections from the HIP6004B must be sized to
OUT
amplifier (Error Amp) output (V ) is compared with the
handle up to 1A peak current.
E/A
oscillator (OSC) triangular wave to provide a pulse-width
Figure 6 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
modulated (PWM) wave with an amplitude of V at the
IN
PHASE node.
FN4567 Rev 3.00
November 9, 2004
Page 8 of 15
HIP6004B
HIP6004B
6. Check Gain against Error Amplifier’s Open-Loop Gain.
V
DRIVER
DRIVER
IN
OSC
7. Estimate Phase Margin - Repeat if Necessary.
PWM
L
O
COMPARATOR
V
OUT
Compensation Break Frequency Equations
-
PHASE
+
C
1
1
V
OSC
O
F
= ------------------------------------
2 x R x C
F
= --------------------------------------------------------
Z1
P1
C
x C
2
1
1
2
2 x R
x
---------------------
ESR
(PARASITIC)
2
C
+ C
1
2
Z
FB
1
1
F
= ------------------------------------------------------
2 x R + R x C
F
= ------------------------------------
2 x R x C
V
E/A
Z2
P2
1
3
3
3
3
Z
-
IN
+
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
REFERENCE
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
Z
FB
V
OUT
C
2
Z
IN
C
C
R
R
Check the compensation gain at F with the capabilities of
3
1
3
2
P2
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
R
1
COMP
FB
-
+
compensation transfer function and plotting the gain.
HIP6004B
DACOUT
The compensation gain uses external impedance networks
Z
and Z to provide a stable, high bandwidth (BW)
FB
IN
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
The PWM wave is smoothed by the output filter (L and C ).
O
O
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
100
OUT E/A
Gain and the output filter (L and C ), with a double pole
F
F
P1
F
F
Z2
Z1
P2
O
O
80
60
40
20
0
break frequency at F and a zero at F
. The DC Gain of
LC ESR
OPEN LOOP
ERROR AMP GAIN
the modulator is simply the input voltage (V ) divided by the
IN
peak-to-peak oscillator voltage V
OSC
.
20LOG
(R /R )
Modulator Break Frequency Equations
2
1
20LOG
(V /V
)
IN OSC
1
1
F
= ------------------------------------------
F
= -------------------------------------------
MODULATOR
GAIN
LC
ESR
2 x ESR x C
2 x
L
x C
COMPENSATION
GAIN
O
O
O
-20
-40
-60
CLOSED LOOP
GAIN
The compensation network consists of the error amplifier
(internal to the HIP6004B) and the impedance networks Z
F
LC
F
IN
ESR
100K
FREQUENCY (Hz)
and Z . The goal of the compensation network is to provide
FB
10
100
1K
10K
1M
10M
a closed loop transfer function with the highest 0dB crossing
frequency (f
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f and
0dB
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0dB
180degrees The equations below relate the compensation
network’s poles, zeros and gain to the components (R , R ,
Component Selection Guidelines
1
2
R , C , C , and C ) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
3
1
2
3
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
1. Pick Gain (R /R ) for desired converter bandwidth.
2
1
ST
2. Place 1 Zero Below Filter’s Double Pole (~75% F ).
LC
ND
3. Place 2
Zero at Filter’s Double Pole.
ST
4. Place 1 Pole at the ESR Zero.
ND
5. Place 2
Pole at Half the Switching Frequency.
FN4567 Rev 3.00
November 9, 2004
Page 9 of 15
HIP6004B
HIP6004B
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating requirements
rather than actual capacitance requirements.
The response time to a transient is different for the application
of load and the removal of load. The following equations give
the approximate response time interval for application and
removal of a transient load:
L x I
L x I
TRAN
OUT
TRAN
V
OUT
t
=
t
=
FALL
RISE
V
- V
IN
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1µF ceramic
capacitors in the 1206 surface-mount package.
where: I
is the transient load current step, t
is the
is the
TRAN
RISE
response time to the application of load, and t
FALL
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application
or removal of load and dependent upon the DACOUT setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time. With
a +12V input, and output voltage level equal to DACOUT,
t
is the longest response time.
FALL
Use only specialized low-ESR capacitors intended for switching-
regulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor’s ESR value is related to the case size with
lower ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately, ESL
is not a specified parameter. Work with your capacitor supplier
and measure the capacitor’s impedance with frequency to select
a suitable component. In most cases, multiple electrolytic
capacitors of small case size perform better than a single large
case capacitor.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors
for high frequency decoupling and bulk capacitors to supply the
current needed each time Q turns on. Place the small ceramic
capacitors physically close to the MOSFETs and between the
1
drain of Q and the source of Q .
1
2
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum input
voltage and a voltage rating of 1.5 times is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC load
current.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function of
the ripple current. The ripple voltage and current are
approximated by the following equations:
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or
equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be exercised
with regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up. The
TPS series available from AVX, and the 593D series from
Sprague are both surge current tested.
V
- V
V
OUT
IN
OUT
DV
= DI x ESR
DI =
x
OUT
Fs x L
V
IN
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
MOSFET Selection/Considerations
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The HIP6004B requires 2 N-Channel power MOSFETs. These
should be selected based upon r
, gate supply
DS(ON)
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design factors.
The power dissipation includes two loss components; conduction
loss and switching loss. The conduction losses are the largest
component of power dissipation for both the upper and the lower
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor (see the equations below).
FN4567 Rev 3.00
November 9, 2004
Page 10 of 15
HIP6004B
HIP6004B
Only the upper MOSFET has switching losses, since the
Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004B
and don't heat the MOSFETs. However, large gate-charge
Figure 10 shows the upper gate drive supplied by a direct
connection to V . This option should only be used in
CC
converter systems where the main input voltage is +5V
or
DC
less. The peak upper gate-to-source voltage is approximately
V
less the input supply. For +5V main power and +12V
CC
DC
for the bias, the gate-to-source voltage of Q is 7V. A logic-
1
level MOSFET is a good choice for Q and a logic-level
1
increases the switching interval, t
which increases the upper
MOSFET can be used for Q if its absolute gate-to-source
SW
2
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
voltage rating exceeds the maximum voltage applied to V
.
CC
+12V
+5V OR LESS
V
CC
1
2
2
BOOT
P
= Io x r
x D +
Io x V x t x F
IN SW S
UPPER
LOWER
DS(ON)
DS(ON)
HIP6004B
2
P
= Io x r
x (1 - D)
Q
Q
1
UGATE
PHASE
Where: D is the duty cycle = V
/ V ,
IN
OUT
NOTE:
G-S V -5V
t
is the switch ON time, and
SW
V
CC
F
is the switching frequency.
S
D
2
LGATE
PGND
2
-
+
Standard-gate MOSFETs are normally recommended for
use with the HIP6004B. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
NOTE:
V
G-S V
CC
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT V
DRIVE OPTION
CC
Schottky Selection
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V . The boot capacitor, C
Rectifier D is a clamp that catches the negative inductor
2
CC
BOOT
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum
input voltage.
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V ) when the lower MOSFET, Q
D
2
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V
.
CC
+12V
D
BOOT
+5V OR +12V
+ V
-
D
V
CC
BOOT
HIP6004B
C
BOOT
Q1
UGATE
PHASE
NOTE:
G-S V -V
V
CC
D
Q2
D2
LGATE
PGND
-
+
NOTE:
G-S V
V
CC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
FN4567 Rev 3.00
November 9, 2004
Page 11 of 15
HIP6004B
HIP6004B
HIP6004B DC-DC Converter Application Circuit
Figure 11 shows an application circuit of a DC-DC Converter
for an Intel Pentium Pro microprocessor. Detailed information
on the circuit, including a complete
Application Note AN9672. Although the Application Note
details the HIP6004, the same evaluation platform can be used
to evaluate the HIP6004B.
Bill-of-Materials and circuit board description, can be found in
L
- 1µHµ
+5V
OR
+12V
2x 1µF
1
F
2N6394
C
1
IN
V
=
IN
5x 1000µF
+12V
2K
D
1
0.1µF
1000pF
1K
OVP
19
V
CC
18
2
12
15
OCSET
PGOOD
MONITOR
AND
PROTECTION
SS
3
BOOT
1
V
0.1µF
SEN
RT
20
0.1µF
OSC
14
13
UGATE
PHASE
Q
Q
L
3µH
1
2
4
5
6
7
8
VID0
VID1
VID2
VID3
VID4
HIP6004B
+V
O
D/A
D
2
17 LGATE
16 PGND
C
-
2
OUT
+
+
-
9x 1000µF
FB
10
9
11
COMP
GND
2.2nF
8.2nF
20K
0.1µF
15
1.33K
Component Selection Notes:
C
Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent.
OUT -
Each 330µF 25W VDC, Sanyo MV-GX or Equivalent.
C
IN -
L - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG.
2
L
D
D
- Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.
- 1N4148 or Equivalent.
- 3A, 40V Schottky, Motorola MBR340 or Equivalent.
1
1
2
Q , Q - Intersil MOSFET; RFP70N03.
1
2
FIGURE 11. PENTIUM PRO DC-DC CONVERTER
FN4567 Rev 3.00
November 9, 2004
Page 12 of 15
HIP6004B
HIP6004B
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES MILLIMETERS
INDEX
M
M
B
0.25(0.010)
H
AREA
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.35
0.23
MAX
2.65
NOTES
E
A
A1
B
C
D
E
e
0.0926
0.0040
0.014
0.1043
0.0118
0.019
-
-B-
0.30
-
0.49
9
1
2
3
L
0.0091
0.4961
0.2914
0.0125
0.32
-
SEATING PLANE
A
0.5118 12.60
13.00
7.60
3
-A-
0.2992
7.40
4
o
D
h x 45
0.050 BSC
1.27 BSC
-
-C-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
µ
5
e
A1
C
L
6
B
0.10(0.004)
N
20
20
7
M
M
S
B
0.25(0.010)
C
A
o
o
o
o
0
8
0
8
-
Rev. 1 1/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN4567 Rev 3.00
November 9, 2004
Page 13 of 15
HIP6004B
HIP6004B
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
M20.173
INDEX
AREA
0.25(0.010)
M
B M
E
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
E1
-B-
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.260
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
6.60
4.50
NOTES
1
2
3
A
A1
A2
b
-
-
L
0.002
0.031
0.0075
0.0035
0.252
0.169
0.05
0.80
0.19
0.09
6.40
4.30
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
-
-A-
D
9
c
-
-C-
D
3
A2
e
A1
E1
e
4
c
b
0.10(0.004)
0.026 BSC
0.65 BSC
-
0.10(0.004) M
C
A M B S
E
0.246
0.256
6.25
0.45
6.50
0.75
-
L
0.0177
0.0295
6
NOTES:
N
20
20
7
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
o
o
o
o
0
8
0
8
-
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
© Copyright Intersil Americas LLC 1999-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4567 Rev 3.00
November 9, 2004
Page 14 of 15
HIP6004B
HIP6004B
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
2.95
2.95
0.28
0.38
3.25
3.25
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7, 8
0.65 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
20
5
5
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
-
9
Rev. 3 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN4567 Rev 3.00
November 9, 2004
Page 15 of 15
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