ISL22343UFR20Z [RENESAS]
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C;型号: | ISL22343UFR20Z |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C 转换器 电阻器 |
文件: | 总19页 (文件大小:1138K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
ISL22343
FN6423
Rev 2.00
August 17, 2015
Data Sheet
August 17, 2015
2
Quad Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, I C
Bus, 256 Taps
The ISL22343 integrates four digitally controlled
potentiometers (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
Features
• Four potentiometers in one package
• 256 resistor taps
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2
• I C serial interface
- Three address pins, up to eight devices per bus
• Non-volatile EEPROM storage of wiper position
• 11 General Purpose non-volatile registers
2
I C bus interface. The potentiometer has an associated
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
corresponding wiper. At power up the device recalls the
contents of the DCP’s IVRi to the correspondent WRi.
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T 55°C
The ISL22343 also has 11 general purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
• Wiper resistance: 70 typical @ 1mA
• Standby current <4µA max
• Shutdown current <4µA max
The ISL22343 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
• Dual power supply
- VCC = 2.25V to 5.5V
- V- = -2.25V to -5.5V
Each DCP can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 10k 50kor 100k total resistance
• Extended industrial temperature range: -40°C to +125°C
• 20 Ld TSSOP or 20 Ld QFN
• Pb-free (RoHS compliant)
Ordering Information
RESISTANCE
OPTION
(k)
TEMP.
RANGE
(°C)
PART NUMBER
(Notes 1, 2)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL22343TFV20Z
22343 TFVZ
22343 TFRZ
22343 UFVZ
22343 UFRZ
100
100
50
-40 to +125 20 Ld TSSOP M20.173
(No longer available, recommended replacement: ISL22343WFR20Z-TK)
ISL22343TFR20Z
-40 to +125 20 Ld QFN
L20.5x5
(No longer available, recommended replacement: ISL22343WFR20Z-TK
ISL22343UFV20Z
-40 to +125 20 Ld TSSOP M20.173
(No longer available, recommended replacement: ISL22343WFR20Z-TK
ISL22343UFR20Z
50
-40 to +125 20 Ld QFN
L20.5x5
(No longer available, recommended replacement: ISL22343WFR20Z-TK
ISL22343WFV20Z
ISL22343WFR20Z
NOTES:
22343 WFVZ
22343 WFRZ
10
10
-40 to +125 20 Ld TSSOP M20.173
-40 to +125 20 Ld QFN L20.5x5
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications
FN6423 Rev 2.00
August 17, 2015
Page 1 of 19
ISL22343
Block Diagram
VCC
V-
RH3
RW3
WR3
WR2
SCL
SDA
A0
POWER-UP,
CONTROL
AND
STATUS
LOGIC
RL3
RH2
2
I C
INTERFACE
A1
A2
RW2
RL2
RH1
WR1
WR0
RW1
RL1
RH0
NON-VOLATILE
REGISTERS
RW0
RL0
GND
Pinouts
ISL22343
ISL22343
(20 LEAD TSSOP)
(20 LEAD QFN)
TOP VIEW
TOP VIEW
1
RW0
RL0
RH3
20
19
RL3
RW3
A2
2
3
4
5
6
7
8
9
20 19 18 17 16
18 RH0
17 V-
RW3
1
2
3
4
5
15
14
13
12
11
V-
A2
SCL
SDA
GND
VCC
A1
SCL
SDA
GND
RW2
RL2
16 VCC
15 A1
14 A0
A0
13 RH1
12
RH1
RL1
RH2 10
11 RW1
6
7
8
9
10
FN6423 Rev 2.00
August 17, 2015
Page 2 of 19
ISL22343
Pin Descriptions
TSSOP PIN
QFN PIN
SYMBOL
RH3
RL3
RW3
A2
DESCRIPTION
1
2
19
20
1
“High” terminal of DCP3
“Low” terminal of DCP3
“Wiper” terminal of DCP3
3
2
4
2
Device address input for the I C interface
2
5
3
SCL
SDA
GND
RW2
RL2
RH2
RW1
RL1
RH1
A0
Open drain I C interface clock input
2
6
4
Open drain Serial data I/O for the I C interface
7
5
Device ground pin
8
6
“Wiper” terminal of DCP2
“Low” terminal of DCP2
“High” terminal of DCP2
“Wiper” terminal of DCP1
“Low” terminal of DCP1
“High” terminal of DCP1
9
7
10
11
12
13
14
15
16
17
18
19
20
8
9
10
11
12
13
14
15
16
17
18
EPAD*
2
Device address input for the I C interface
2
A1
Device address input for the I C interface
VCC
V-
Positive power supply pin
Negative power supply pin
“High” terminal of DCP0
RH0
RL0
RW0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
Exposed Die Pad internally connected to V-
NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
FN6423 Rev 2.00
August 17, 2015
Page 3 of 19
ISL22343
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical, Note 3)
(°C/W)
(°C/W)
JC
JA
20 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . .95
20 Lead QFN (Note 4) . . . . . . . . . . . . . . . . . . .32
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
N/A
3.0
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V
Voltage at any DCP Pin with
respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V
CC
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Recommended Operating Conditions
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125°C
Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
ESD
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V
Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Analog Specifications Over recommended operating conditions unless otherwise stated.
MIN
TYP
MAX
SYMBOL
PARAMETER
RHi to RLi Resistance
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
k
R
W option
U option
T option
10
50
TOTAL
k
100
k
RHi to RLi Resistance tolerance
-20
V-
+20
%
End-to-End Temperature Coefficient
W option
±85
±45
ppm/°C
ppm/°C
V
U, T option
V
, V
RHi RLi
DCP Terminal Voltage
Wiper Resistance
V
and V to GND
RL
V
RH
CC
R
RH - floating, V = V-, force Iw current to
RL
the wiper, I = (V
70
10/10/25
0.1
250
W
- V )/R
W
CC
RL TOTAL
C /C /C
W
(Note 19)
Potentiometer Capacitance
Leakage on DCP pins
See Macro Model below.
pF
µA
H
L
I
Voltage at pin from V- to V
@ RHi; measured at RWi, unloaded)
W option
1
LkgDCP
CC
VOLTAGE DIVIDER MODE (V- @ RLi; V
CC
INL
Integral Non-linearity
-1.5
-1.0
-1.0
-0.5
±0.5
±0.2
1.5
1.0
1.0
0.5
LSB
(Note 6)
(Note 10)
U, T option
LSB
(Note 6)
DNL
Differential Non-linearity
Monotonic over all tap positions,
W option
±0.4
LSB
(Note 6)
(Note 9)
U, T option
±0.15
LSB
(Note 6)
ZSerror
(Note 7)
Zero-scale Error
Full-scale Error
W option
0
0
1
5
2
0
0
LSB
(Note 6)
U, T option
W option
0.1
-2
FSerror
(Note 8)
-5
-2
LSB
(Note 6)
U, T option
-0.2
FN6423 Rev 2.00
August 17, 2015
Page 4 of 19
ISL22343
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
V
DCP-to-DCP Matching
Wipers at the same tap position, the same
voltage at all RH terminals and the same
voltage at all RL terminals
-2
2
LSB
(Note 6)
MATCH
(Note 11)
TC (Note 12) Ratiometric Temperature Coefficient
DCP register set to 80 hex
±4
1000
250
120
ppm/°C
kHz
V
f
-3dB Cut Off Frequency
Wiper at midpoint (80hex) W option (10k)
Wiper at midpoint (80hex) U option (50k)
Wiper at midpoint (80hex) T option (100k)
cutoff
(Note 19)
kHz
kHz
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected)
RINL
(Note 16)
Integral Non-linearity
Differential Non-linearity
Offset
W option
-3
±1
±0.3
±0.5
±0.04
1
3
MI
(Note 13)
U, T option
W option
-1
1
MI
(Note 13)
RDNL
(Note 15)
-1.5
-0.5
0
1.5
0.5
5
MI
(Note 13)
U, T option
W option
MI
(Note 13)
Roffset
MI
(Note 14)
(Note 13)
U, T option
0
0.25
2
MI
(Note 13)
R
DCP-to-DCP matching
Wipers at the same tap position with the
same terminal voltages
-3
3
MI
(Note 13)
MATCH
(Note 17)
TC
Resistance Temperature Coefficient
DCP register set between 32 hex and FFhex
±40
ppm/°C
R
(Notes 18, 19)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
2
I
V
Supply Current
V
= 5.5V, f
= 400kHz; (for I C Active, Read and
0.006
0.003
-0.012
-0.045
1.0
0.5
mA
CC1
CC
CC
SCL
(Volatile Write/Read)
Volatile Write states only)
2
V
= 2.25V, f = 400kHz; (for I C Active, Read and
0.25
mA
mA
mA
mA
mA
mA
mA
CC
SCL
Volatile Write states only)
2
I
V- Supply Current (Volatile V- = -5.5V, V
Write/Read)
= 5.5V, f
= 400kHz; (for I C Active,
Read and Volatile Write states only)
-0.5
V-1
CC
SCL
2
V- = -2.25V, V = 2.25V, f = 400kHz; (for I C
Active, Read and Volatile Write states only)
-0.25
CC
SCL
2
I
V
Supply Current (Non-
V = 5.5V, V- = 5.5V, f
CC SCL
= 400kHz; (for I C Active,
Read and Non-volatile Write states only)
2.0
1.0
CC2
CC
volatile Write/Read)
2
V
= 2.25V, V- = -2.25V, f = 400kHz; (for I C
Active, Read and Non-volatile Write states only)
0.3
CC
SCL
2
I
V- Supply Current
V- = -5.5V, V
= 5.5V, f = 400kHz; (for I C Active,
SCL
(Non-Volatile Write/Read) Read and Non-volatile Write states only)
-2.0
-1.0
-1.2
V-2
CC
2
V- Supply Current V- = -2.25V, V = 2.25V, f = 400kHz; (for I C
-0.4
CC
SCL
(Non-Volatile Write/Read) Active, Read and Non-volatile Write states only)
FN6423 Rev 2.00
August 17, 2015
Page 5 of 19
ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
2
I
V
Current (Standby)
V
= +5.5V, V- = -5.5V @ +85°C, I C interface in
0.5
1.0
2.0
4.0
1.0
2.0
µA
SB
CC
CC
standby state
2
V
= +5.5V, V- = -5.5V @ +125°C, I C interface in
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
CC
standby state
2
V
= +2.25V, V- = -2.25V @ +85°C, I C interface in
0.2
CC
standby state
2
V
= +2.25V, V- = -2.25V @ +125°C, I C interface in
0.5
CC
standby state
2
I
V- Current (Standby)
V- = -5.5V, V
CC
standby state
= +5.5V @ +85°C, I C interface in
-4.0
-5.0
-2.0
-3.0
-0.7
-1.5
-0.3
-0.4
0.5
V-SB
2
V- = -5.5V, V
standby state
= +5.5V @ +125°C, I C interface in
CC
2
V- = -2.25V, V
standby state
= +2.25V @ +85°C, I C interface in
CC
CC
2
V- = -2.25V, V
standby state
= +2.25V @ +125°C, I C interface in
2
I
V
Current (Shutdown)
V
= +5.5V, V- = -5.5V @ +85°C, I C interface in
2.0
4.0
1.0
2.0
SD
CC
CC
standby state
2
V
= +5.5V, V- = -5.5V @ +125°C, I C interface in
1.0
CC
standby state
2
V
= +2.25V, V- = -2.25V @ +85°C, I C interface in
0.2
CC
standby state
2
V
= +2.25V, V- = -2.25V @ +125°C, I C interface in
0.5
CC
standby state
2
I
V- Current (Shutdown)
V- = -5.5V, V
= +5.5V @ +85°C, I C interface in
-4.0
-5.0
-2.0
-3.0
-1
-0.7
-1.5
-0.3
-0.4
V-SD
CC
standby state
2
V- = -5.5V, V
CC
standby state
= +5.5V @ +125°C, I C interface in
2
V- = -2.25V, V
standby state
= +2.25V @ +85°C, I C interface in
CC
CC
2
V- = -2.25V, V
standby state
= +2.25V @ +125°C, I C interface in
I
Leakage Current, at Pins Voltage at pin from GND to V
A0, A1, A2, SDA, and SCL
1
LkgDig
CC
t
DCP Wiper Response
SCL falling edge of last bit of DCP data byte to wiper
new position
1.5
1.5
WRT
(Note 19) Time
t
DCP Recall Time from
SCL falling edge of last bit of ACR data byte to wiper
stored position and RH connection
µs
ShdnRec
(Note 19) Shutdown Mode
Vpor
Power-on Recall Voltage
Ramp Rate
Minimum V
at which memory recall occurs
1.9
0.2
2.1
5
V
CC
VCCRamp
V
V/ms
ms
CC
t
Power-up Delay
V
above Vpor, to DCP Initial Value Register recall
2
D
CC
completed, and I C Interface in standby state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T +55°C
t
Non-volatile Write Cycle
12
20
WC
(Note 20) Time
FN6423 Rev 2.00
August 17, 2015
Page 6 of 19
ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
SERIAL INTERFACE SPECS
V
A1, A0, A2, SDA, and SCL
Input Buffer LOW Voltage
0.3*V
V
V
IL
CC
V
A1, A0, A2, SDA, and SCL
Input Buffer HIGH Voltage
0.7*V
CC
IH
Hysteresis SDA and SCL Input Buffer
(Note 19) Hysteresis
0.05*V
0
V
CC
V
SDA Output Buffer LOW
0.4
10
V
OL
(Note 19) Voltage, Sinking 4mA
Cpin
A1, A0, A2, SDA, and SCL
pF
(Note 19) Pin Capacitance
f
SCL Frequency
400
50
kHz
ns
SCL
t
Pulse Width Suppression Any pulse narrower than the max spec is suppressed
sp
Time at SDA and SCL
Inputs
t
SCL Falling Edge to SDA SCL falling edge crossing 30% of V , until SDA exits
CC
900
ns
ns
AA
(Note 19) Output Data Valid
the 30% to 70% of V
window
CC
t
Time the Bus Must be Free SDA crossing 70% of V
CC
during a STOP condition, to
during the following START
1300
BUF
(Note 19) Before the Start of a New SDA crossing 70% of V
CC
Transmission
condition
t
Clock LOW Time
Clock HIGH Time
Measured at the 30% of V
Measured at the 70% of V
crossing
crossing
1300
600
ns
ns
ns
LOW
CC
CC
t
HIGH
t
START Condition Setup
Time
SCL rising edge to SDA falling edge; both crossing 70%
of V
600
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
HD:STO
CC
From SDA falling edge crossing 30% of V
t
t
START Condition Hold
Time
to SCL
600
100
0
ns
ns
ns
ns
ns
CC
falling edge crossing 70% of V
CC
Input Data Setup Time
From SDA exiting the 30% to 70% of V
SCL rising edge crossing 30% of V
window, to
CC
CC
t
Input Data Hold Time
From SCL rising edge crossing 70% of V
entering the 30% to 70% of V
to SDA
CC
window
CC
t
STOP Condition Setup
Time
From SCL rising edge crossing 70% of V , to SDA
rising edge crossing 30% of V
600
1300
CC
CC
t
STOP Condition Hold
From SDA rising edge to SCL falling edge; both
Time for Read, or Volatile crossing 70% of V
Only Write
CC
t
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
From SCL falling edge crossing 30% of V , until SDA
CC
0
ns
ns
ns
DH
(Note 19)
enters the 30% to 70% of V
window
CC
t
From 30% to 70% of V
From 70% to 30% of V
20 +
0.1*Cb
250
250
R
CC
CC
(Note 19)
t
20 +
F
(Note 19)
0.1*Cb
FN6423 Rev 2.00
August 17, 2015
Page 7 of 19
ISL22343
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 21) (Note 5) (Note 21)
UNIT
Cb
CapacitiveLoadingofSDA Total on-chip and off-chip
10
1
400
pF
(Note 19) or SCL
Rpu
SDA and SCL Bus Pull-up Maximum is determined by t and t
k
R
F
(Note 19) Resistor Off-chip
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
t
A1 and A0 Setup Time
A1 and A0 Hold Time
Before START condition
After STOP condition
600
600
ns
ns
SU:A
t
HD:A
NOTES:
5. Typical values are for T = +25°C and 3.3V supply voltage.
A
6. LSB: [V(R
)
– V(R ) ]/255. V(R
)
and V(R ) are V(R ) for the DCP register set to FF hex and 00 hex respectively. LSB is the
W 0
W 255
W 0 W 255
W
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW) /LSB.
0
8. FS error = [V(RW)
255
– V ]/LSB.
CC
9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.
i-1
i
10. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255.
i
0
11. V
= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3, y = 0 to 3.
MATCH
MaxVRW – MinVRW
6
10
i
i
12.
for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
MaxVRW + MinVRW 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
--------------------------------------------------------------------------------------------- ----------------
TC
=
V
+
i
i
13. MI = |RW
– RW |/255. MI is a minimum increment. RW
and RW are the measured resistances for the DCP register set to FF hex and
255 0
255
0
00 hex respectively.
14. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
255
15. RDNL = (RW – RW )/MI -1, for i = 16 to 255.
i
i-1
16. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.
i
0
17. R
18.
= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 3, y = 0 to 3.
6
MATCH
for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
the minimum value of the resistance over the temperature range.
MaxRi – MinRi
10
--------------------------------------------------------------- ----------------
TC
=
R
165°C
MaxRi + MinRi 2 +
19. This parameter is not 100% tested.
2
20. t
is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal non-
WC
volatile write cycle.
21. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
FN6423 Rev 2.00
August 17, 2015
Page 8 of 19
ISL22343
DCP Macro Model
R
TOTAL
RH
RL
C
L
C
H
C
W
10pF
10pF
25pF
RW
SDA vs SCL Timing
t
sp
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
t
t
BUF
AA
DH
SDA
(OUTPUT TIMING)
A2, A1 and A0 Pin Timing
STOP
START
SCL
CLK 1
SDA
t
t
HD:A
SU:A
A2, A1, A0
FN6423 Rev 2.00
August 17, 2015
Page 9 of 19
ISL22343
Typical Performance Curves
80
2.0
1.5
1.0
0.5
0
T = +125°C
70
60
50
40
30
20
10
0
T = +25°C
T = -40°C
I
CC
-0.5
-1.0
-1.5
-2.0
I
V-
0
50
100
150
200
250
-40
0
40
TEMPERATURE (°C)
80
120
TAP POSITION (DECIMAL)
FIGURE 2. STANDBY I
and I vs TEMPERATURE
V-
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10k (W)
CC
CC TOTAL
0.50
0.50
0.25
0
V
= 5.5V
CC
T = +25°C
T = +25°C
V
= 2.25V
CC
0.25
0
-0.25
-0.50
-0.25
-0.50
V
= 5.5V
V
= 2.25V
100
CC
100
TAP POSITION (DECIMAL)
CC
0
50
150
200
250
0
50
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
MODE FOR 10k (W)
2.0
0
10k
1.6
1.2
-1
V
= 2.25V
CC
50k
V
= 5.5V
CC
-2
0.8
-3
-4
50k
10k
V
= 2.25V
V
= 5.5V
CC
CC
0.4
0
-5
-40
0
40
80
120
-40
0
40
TEMPERATURE (ºC)
80
120
TEMPERATURE (ºC)
FIGURE 6. FS ERROR vs TEMPERATURE
FIGURE 5. ZS ERROR vs TEMPERATURE
FN6423 Rev 2.00
August 17, 2015
Page 10 of 19
ISL22343
Typical Performance Curves (Continued)
0.5
2.0
T = +25°C
T = +25°C
V
= 5.5V
1.5
1.0
CC
V
= 2.25V
0.25
0
CC
0.5
0
-0.25
-0.50
V
= 2.25V
100
CC
V
= 5.5V
CC
-0.5
0
50
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
10k (W)
200
160
1.60
10k
1.20
10k
120
0.80
5.5V
80
0.40
0.00
50k
40
0
50k
2.25V
-0.40
-40
16
66
116
166
216
266
0
40
80
120
TAP POSITION (DECIMAL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END R
% CHANGE vs
TOTAL
TEMPERATURE
500
400
300
INPUT
OUTPUT
10k
200
100
50k
WIPER AT MID POINT (POSITION 80h)
R
= 10k
TOTAL
0
16
66
116
166
216
TAP POSITION (DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (1MHz)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FN6423 Rev 2.00
August 17, 2015
Page 11 of 19
ISL22343
Typical Performance Curves (Continued)
CS
SCL
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
WIPER
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
2
maximum of eight ISL22343 devices may occupy the I C serial
bus (See Table 3).
Pin Description
Potentiometers Pins
RHI AND RLI
Principles of Operation
The ISL22343 is an integrated circuit incorporating four DCPs
with its associated registers, non-volatile memory and an I C
The high (RHi) and low (RLi) terminals of the ISL22343 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest to
RLi.
2
serial interface providing direct communication between a host
and the potentiometer and memory. The resistor arrays are
comprised of individual resistors connected in a series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to the
wiper.
RWI
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
When the device is powered down, the last value stored in IVRi
will be maintained in the non-volatile memory. When power is
restored, the contents of the IVRi are recalled and loaded into
the corresponding WRi to set the wipers to their initial
positions.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
2
The SDA is a bidirectional serial data input/output pin for I C
interface. It receives device address, operation code, wiper
address and data from an I C external master device at the
DCP Description
2
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position of
the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is
closest to its “Low” terminal (RLi). When the WRi register of a
DCP contains all ones (WRi[7:0] = FFh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the
WRi increases from all zeroes (0) to all ones (255 decimal), the
wiper moves monotonically from the position closest to RLi to
the position closest to RHi. At the same time, the resistance
SERIAL CLOCK (SCL)
2
This input is the serial clock of the I C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set three least significant bits of
2
the 7-bit I C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL22343. A
FN6423 Rev 2.00
August 17, 2015
Page 12 of 19
ISL22343
between RWi and RLi increases monotonically, while the
resistance between RHi and RWi decreases monotonically.
The VOL bit (ACR[7]) determines whether the access to wiper
registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
While the ISL22343 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage becomes
large enough for reliable non-volatile memory reading, the WRi
will be reloaded with the value stored in corresponding non-
volatile Initial Value Register (IVRi).
BIT #
7
6
5
4
0
3
0
2
0
1
0
0
0
NAME
VOL
SHDN WIP
If VOL bit is 0, the non-volatile IVRi registers are accessible. If
VOL bit is 1, only the volatile WRi are accessible.
Note: value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The WRi and IVRi can be read or written to directly using the
I C serial interface as described in the following sections.
2
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
When this bit is 0, DCPs are in Shutdown mode. Default value of
the SHDN bit is 1.
Memory Description
The ISL22343 contains four non-volatile 8-bit Initial Value Register
(IVRi), eleven General Purpose non-volatile 8-bit registers and
five volatile 8-bit registers: four Wiper Registers (WRi) and Access
Control Register (ACR). Memory map of ISL22343 is in Table 1.
The non-volatile registers (IVRi) at address 0, 1, 2 and 3 contain
initial wiper position and volatile registers (WRi) contain current
wiper position.
RHi
RWi
TABLE 1. MEMORY MAP
RLi
ADDRESS
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
(hex)
10
F
NON-VOLATILE
VOLATILE
N/A
ACR
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. It is impossible to write to
the WRi or ACR while WIP bit is 1.
Reserved
E
D
C
B
A
9
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
IVR3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WR3
WR2
WR1
WR0
2
I C Serial Interface
2
The ISL22343 supports an I C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL22343 operates as a slave device
in all applications.
8
7
6
2
All communication over the I C interface is conducted by
5
sending the MSB of each byte of data first.
4
Protocol Conventions
3
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22343, the SDA pin is
in the input mode.
2
IVR2
1
IVR1
0
IVR0
2
All I C interface operations must begin with a START
The non-volatile IVRi and volatile WRi registers are accessible
with the same address.
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The ISL22343 continuously monitors the SDA and
SCL lines for the START condition and does not respond to
any command until this condition is met (See Figure 16). A
START condition is ignored during the power-up of the device.
The Access Control Register (ACR) contains information and
control bits described below in Table 2.
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL
is HIGH (see Figure 16). A STOP condition at the end of a read
FN6423 Rev 2.00
August 17, 2015
Page 13 of 19
ISL22343
operation, or at the end of a write operation places the device
in its standby mode.
A valid Identification Byte contains 1010 as four MSBs, and the
following three bits matching the logic values present at pins
A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1”
for a Read operation and “0” for a Write operation (See Table
3).
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits of
data (see Figure 17).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
The ISL22343 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22343 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
1
0
1
0
A2
A1
A0
R/W
(MSB)
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE
CHANGE STABLE
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
SIGNALS FROM
THE MASTER
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
SIGNAL AT SDA
1 0 1 0 A2A1A0 0
0 0 0 0
SIGNALS FROM
THE SLAVE
A
C
K
A
C
K
A
C
K
FIGURE 18. BYTE WRITE SEQUENCE
FN6423 Rev 2.00
August 17, 2015
Page 14 of 19
ISL22343
S
T
A
R
T
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
ADDRESS
BYTE
SIGNAL AT SDA
1 0 1 0 A2 A1A0 0
0 0 0 0
1 0 1 A2A1A0 1
0
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE
circuit, thus this may not be a good solution for some
Write Operation
applications. It may be a good idea, in that case, to use fast
amplifiers in a signal chain for fast recovery.
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte, and
a STOP condition. After each of the three bytes, the ISL22343
responds with an ACK. At this time, the device enters its
standby state (see Figure 18).
Application Example
Figure 20 shows an example of using ISL22343 for gain setting
and offset correction in a high side current measurement
application. DCP0 applies a programmable offset voltage of
±25mV to the FB+ pin of the Instrumentation Amplifier
ISL28272 to adjust output offset to zero voltages. DCP1
programs the gain of the ISL28272 from 90 to 110 with 5V
output for 10A current through current sense resistor. DCP2
and DCP3 are used for another channel of dual ISL28272
correspondently (not shown in Figure 20).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next non-
volatile write. Thus, non-volatile registers must be written
individually.
Read Operation
A Read operation consist of a three byte instruction followed by
one or more Data Bytes (see Figure 19). The master initiates
the operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte,
a second START, and a second Identification byte with the R/W
bit set to “1”. After each of the three bytes, the ISL22343
responds with an ACK. Then the ISL22343 transmits Data
Bytes as long as the master responds with an ACK during the
SCL cycle following the eighth bit of each byte. The Data Bytes
are from the registers indicated by an internal pointer. This
pointers initial value is determined by the Address Byte in the
Read operation instruction, and increments by one during
transmission of each Data Byte. After reaching the memory
location 0Fh, the pointer “rolls over” to 00h, and the device
continues to output data for each ACK received.The master
terminates the read operation issuing a NACK (ACK) and a
STOP condition following the last bit of the last Data Byte (See
Figure 19).
More application examples can be found at
http://www.intersil.com/data/an/AN1145.pdf
Applications Information
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients (or overshoot/undershoot) resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break within an extremely short period of time
(<50ns). Two such code transitions are EFh to F0h, and 0Fh to
10h. Note that all switching transients will settle well within the
settling time as stated on the datasheet. A small capacitor can
be added externally to reduce the amplitude of these voltage
transients, but that will also reduce the useful bandwidth of the
FN6423 Rev 2.00
August 17, 2015
Page 15 of 19
ISL22343
1.2V
DC/DC CONVERTER
OUTPUT
PROCESSOR LOAD
10A, MAX
0.005
+5V
10k
10k
0.1µF
16
V+
1/2 ISL28272
7
6
5
3
4
IN+
EN
IN-
2
V
V
= 0V TO +5V TO ADC
OUT
OUT
FB+
+5V
R
4
FB-
V-
150k, 1%
R
1
8
50k, 1%
RH1
RL1
RH0
RW1
R
5
309, 1%
R
2
1k, 1%
RW0
RL0
50k
50k
DCP0 (1/4 ISL22343U)
PROGRAMMABLE OFFSET ±25mV
DCP1 (1/4 ISL22343U)
PROGRAMMABLE GAIN 90 TO 110
R
6
R
3
1.37k, 1%
50k, 1%
-5V
ISL22343UFV20Z
16
18
19
20
+5V
I C bus
VCC
RH0
RL0
RW0
DCP0
DCP1
5
6
4
15
SCL
SDA
A2
A1
A0
2
13
12
11
RH1
RL1
RW1
14
10
9
8
7
RH2
RL2
RW2
GND
DCP2
DCP3
17
-5V
V-
1
2
3
RH3
RL3
RW3
FIGURE 20. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
FN6423 Rev 2.00
August 17, 2015
Page 16 of 19
ISL22343
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN6423.2
CHANGE
August 17, 2015
Updated Ordering Information Table on page 1.
Added Revision History and About Intersil sections.
Updated POD M20.173 to current revision. Changes: Converted to new POD format and added land pattern.
No dimension changes.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2007-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6423 Rev 2.00
August 17, 2015
Page 17 of 19
ISL22343
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
0.02
-
0.65
9
0.20 REF
9
0.23
2.95
2.95
0.30
0.38
3.25
3.25
5, 8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7, 8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7, 8
0.65 BSC
-
k
0.20
0.35
-
0.60
20
5
-
-
L
0.75
8
N
2
Nd
Ne
P
3
5
3
-
-
-
0.60
12
9
-
9
Rev. 4 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"
dimension.
FN6423 Rev 2.00
August 17, 2015
Page 18 of 19
ISL22343
Package Outline Drawing
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
6.50 ±0.10
SEE DETAIL "X"
10
20
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
9
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN6423 Rev 2.00
August 17, 2015
Page 19 of 19
相关型号:
ISL22343UFR20Z-TK
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C
RENESAS
ISL22343UFV20Z
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C
RENESAS
ISL22343UFV20Z-TK
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C
RENESAS
ISL22343WFR20Z-TK
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C
RENESAS
ISL22343WFV20Z
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C
RENESAS
ISL22343WFV20Z-TK
Quad Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, I2C® Bus, 256 Taps; QFN20, TSSOP20; Temp Range: -40° to 125°C
RENESAS
ISL22346
Quad Digitally Controlled Potentiometers (XDCPâ¢) Low Noise, Low Power I2C⢠Bus, 128 Taps
RENESAS
©2020 ICPDF网 联系我们和版权申明