ISL28127FUZ-T7 [RENESAS]
IC OPAMP GP 10MHZ LN 8MSOP;
| 型号： | ISL28127FUZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC OPAMP GP 10MHZ LN 8MSOP 放大器 |
| 文件： | 总26页 (文件大小：2007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Single and Dual Low Noise Operational
Amplifiers
ISL28127, ISL28227
Features
The ISL28127 and ISL28227 are very high precision amplifiers
featuring very low noise, low offset voltage, low input bias
current and low temperature drift making them the ideal
choice for applications requiring both high DC accuracy and AC
performance. The combination of precision, low noise, and
small footprint provides the user with outstanding value and
flexibility relative to similar competitive parts.
• Very Low Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . .2.5nV/Hz
• Low Input Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70µV, Max.
• Superb Offset Drift. . . . . . . . . . . . . . . . . . . . . . 0.5µV/°C, Max.
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA, Max.
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V
• Gain-bandwidth Product . . . . . . . . . 10MHz Unity Gain Stable
• No Phase Reversal
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
Applications
The ISL28127 single and ISL28227 dual are available in an 8
Ld SOIC, TDFN and MSOP packages. All devices are offered in
standard pin configurations and operate over the extended
temperature range to -40°C to +125°C.
• Precision Instruments
• Medical Instrumentation
• Industrial Controls
• Active Filter Blocks
• Data Acquisition
• Power Supply Control
Related Literature
• AN1508: ISL281x7SOICEVAL1Z Evaluation Board User’s
Guide
• AN1509: ISL282x7SOICEVAL1Z Evaluation Board User’s
Guide
C
100
1
VS = ±19V
AV = 1
1.5nF
V
+
-
10
OUTPUT
R
R
V
2
1
IN
+
95.3
232
68.3nF
C
2
V
-
1
0.1
1
10
100
1k
10k
100k
Sallen-Key Low Pass Filter (1MHz)
FREQUENCY (Hz)
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FIGURE 1. TYPICAL APPLICATION
December 16, 2010
FN6633.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL28127, ISL28227
.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOS (MAX)
(µV)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28127FBZ
28127 FBZ
70
8 Ld SOIC
M8.15E
L8.3x3A
L8.3x3A
M8.118
M8.118
M8.15E
L8.3x3A
L8.3x3A
M8.118
M8.118
ISL28127FRTBZ
ISL28127FRTZ
8127
75 (B Grade)
150 (C Grade)
70 (B Grade)
150 (C Grade)
75
8 Ld TDFN
8 Ld TDFN
-C 8127
ISL28127FUBZ
8127Z
8 Ld MSOP
8 Ld MSOP
8 Ld SOIC
8 Ld TDFN
8 Ld TDFN
8 Ld MSOP
8 Ld MSOP
ISL28127FUZ
8127Z -C
28227 FBZ
8227
ISL28227FBZ
ISL28227FRTBZ
ISL28227FRTZ
75 (B Grade)
150 (C Grade)
75 (B Grade)
150 (C Grade)
-C 8227
ISL28227FUBZ
8227Z
ISL28227FUZ
8227Z -C
Evaluation Board
Evaluation Board
Evaluation Board
ISL28127SOICEVAL1Z
ISL28127MSOPEVAL1Z
ISL28227SOICEVAL2Z
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28127, ISL28227. For more information on MSL please see techbrief
TB363.
FN6633.6
December 16, 2010
2
ISL28127, ISL28227
Pin Configurations
ISL28127
(8 LD SOIC, MSOP)
TOP VIEW
ISL28227
(8 LD SOIC, MSOP)
TOP VIEW
NC
-IN_A
+IN_A
V -
1
2
3
4
8
7
6
5
NC
V+
V
A
1
2
3
4
8
7
6
5
V+
OUT
-IN_A
+IN_A
V -
V
B
-
+
OUT
- +
V
A
-IN_B
OUT
+
-
NC
+IN_B
ISL28127
(8 LD TDFN)
TOP VIEW
ISL28227
(8 LD TDFN)
TOP VIEW
V A
OUT
V+
8
NC
NC
1
1
8
-IN_A
+IN_A
V-
V
B
-IN
+IN
V-
V+
V
2
3
4
7
6
2
3
4
7
6
5
OUT
- +
- +
-IN_B
OUT
+ -
PD
PD
5 +IN_B
NC
Pin Descriptions
ISL28127
(8 LD SOIC,
8 LD MSOP)
ISL28227
(8 LD SOIC,
8 LD MSOP)
ISL28127
(8 LD TDFN)
ISL28227
(8 LD TDFN)
PIN
NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
3
4
2
6
7
+IN
+IN_A
V-
Circuit 1
Circuit 1
Circuit 3
Circuit 1
Circuit 1
Circuit 1
Circuit 2
Circuit 2
Circuit 3
Circuit 2
Circuit 1
-
Amplifier non-inverting input
Amplifier A non-inverting input
Negative power supply
Amplifier B non-inverting input
Amplifier inverting input
Amplifier B inverting input
Amplifier output
3
4
3
4
5
3
4
5
+IN_B
-IN
6
6
-IN_B
VOUT
7
8
1
2
7
8
1
2
VOUTB
Amplifier B output
7
6
V+
Positive power supply
VOUTA
Amplifier A output
2
-IN_A
NC
Amplifier A inverting input
1, 5, 8
1, 5, 8
PD
Not Connected – This pin is not
electrically connected internally.
PD
-
Thermal Pad. Pad should be connected to
lowest potential source in the circuit.
V+
V-
V+
V+
OUT
V-
CAPACITIVELY TRI
GGERED ESD
CLAMP
IN-
IN+
V-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
FN6633.6
December 16, 2010
3
ISL28127, ISL28227
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for
Thermal Resistance (Typical)
8 Ld SOIC (Note 5, 7)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . .
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld TDFN (Notes 4, 6)
θ
JA (°C/W)
θ
JC (°C/W)
120
110
60
55
Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration
(1 Output at a Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Tolerance
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . .
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP (Note 5, 7)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . .
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . .
48
47
7
6
155
150
50
45
Human Body Model (Tested per JESD22-A114F)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0kV
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 500V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . .1.5kV
Di-electrically Isolated PR40 process . . . . . . . . . . . . . . . . . . . Latch-up free
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over
S
CM
O
L
A
the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
VOS
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
Offset Voltage; SOIC Package
ISL28127
ISL28227
-70
10
70
120
75
-120
-75
-
10
-150
-70
-
150
70
Offset Voltage;
MSOP Grade B Package
ISL28127
ISL28127
ISL28227
-10
-150
-75
-
150
75
Offset Voltage;
TDFN Grade B Package
-10
-160
-75
-
-10
-
160
75
Offset Voltage;
MSOP, TDFN Grade B Package
-150
-150
-250
150
150
250
Offset Voltage;
MSOP, TDFN Grade C Package
ISL28127
ISL28227
-10
-
FN6633.6
December 16, 2010
4
ISL28127, ISL28227
Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over
S
CM
O
L
A
the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
TCVOS
DESCRIPTION
Offset Voltage Drift;
CONDITIONS
(Note 8)
TYP
0.1
0.1
0.1
(Note 8)
UNIT
ISL28127
ISL28227
ISL28127
-0.5
0.5
µV/°C
µV/°C
µV/°C
SOIC Package
-0.75
-0.80
0.75
0.80
Offset Voltage Drift;
MSOP, Grade B
Offset Voltage Drift;
TDFN, Grade B
ISL28127
ISL28227
-0.90
-0.75
-1
0.1
0.1
0.1
0.90
0.75
1
µV/°C
µV/°C
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade B
Offset Voltage Drift;
MSOP, TDFN, Grade C
ISL28127
ISL28227
IOS
Input Offset Current
-10
-12
1
10
nA
nA
nA
nA
V
-
12
IB
Input Bias Current
-10
1
10
-12
-
12
VCM
Input Voltage Range
Guaranteed by CMRR
-13
-
13
-12
-
12
V
CMRR
PSRR
Common-Mode Rejection Ratio
V
CM = -13V to +13V
115
115
115
115
110
110
1000
120
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
V/mV
VCM = -12V to +12V
VS = ±2.25V to ±20V
VS = ±3V to ± 20V
VS = ±2.25V to ±20V
VS = ±3V to ± 20V
-
125
-
Power Supply Rejection Ratio
ISL28127
Power Supply Rejection Ratio
ISL28227
117
-
AVOL
VOH
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
1500
Output Voltage High
RL = 10kΩ to ground
RL = 2kΩ to ground
RL = 10kΩ to ground
RL = 2kΩ to ground
13.5
13.65
-
-
V
V
13.2
-
13.4
13.5
-
V
13.1
-
-
V
VOL
Output Voltage Low
-
-13.65
-13.5
-13.2
-13.4
-13.1
2.8
3.7
-
V
-
-
V
-
-13.5
V
-
-
V
IS
Supply Current/Amplifier
-
2.2
mA
mA
mA
V
-
-
±45
-
ISC
Short-Circuit
RL = 0Ω to ground
-
VSUPPLY
Supply Voltage Range
Guaranteed by PSRR
±2.25
±20
AC SPECIFICATIONS
GBW
enp-p
en
Gain Bandwidth Product
-
-
-
-
10
85
3
-
-
-
-
MHz
Voltage Noise
0.1Hz to 10Hz
f = 10Hz
nVP-P
Voltage Noise Density
Voltage Noise Density
nV/√Hz
nV/√Hz
en
f = 100Hz
2.8
FN6633.6
December 16, 2010
5
ISL28127, ISL28227
Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over
S
CM
O
L
A
the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
Voltage Noise Density
CONDITIONS
(Note 8)
TYP
2.5
(Note 8)
UNIT
nV/√Hz
nV/√Hz
pA/√Hz
%
en
en
f = 1kHz
-
-
-
-
-
-
-
-
Voltage Noise Density
f = 10kHz
f = 10kHz
2.5
in
Current Noise Density
0.4
THD + N
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS
,
0.00022
RL = 2kΩ
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 2kΩ, VO = 4VP-P
AV = -1, VOUT = 100mVP-P
-
-
±3.6
36
-
-
V/µs
ns
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
AV = -1, VOUT = 100mVP-P
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
AV = -1 VOUT = 10VP-P
Rg = Rf =10k, RL = 2kΩ to VCM
AV = -1, VOUT = 10VP-P
L = 2kΩ to VCM
Fall Time
90% to 10% of VOUT
,
-
-
-
-
38
3.4
3.8
1.7
-
-
-
-
ns
µs
µs
µs
ts
Settling Time to 0.1%
10V Step; 10% to VOUT
,
Settling Time to 0.01%
10V Step; 10% to VOUT
,
R
tOL
Output Overload Recovery Time
AV = 100, VIN = 0.2V
RL = 2kΩ to VCM
Electrical Specifications V ±5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the
S
CM
O
A
operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
VOS
DESCRIPTION
CONDITIONS
(Note 8)
TYP
10
-
(Note 8)
UNIT
µV
Offset Voltage; SOIC Package
ISL28127
ISL28227
-70
70
-120
120
µV
-75
10
-
75
µV
µV
-150
150
Offset Voltage;
MSOP Grade B Package
ISL28127
ISL28127
ISL28227
-70
-150
-75
-10
70
150
75
µV
µV
µV
µV
µV
µV
µV
µV
-
Offset Voltage;
TDFN Grade B Package
-10
-160
-75
-
-10
-
160
75
Offset Voltage;
MSOP, TDFN Grade B Package
-150
-150
-250
150
150
250
Offset Voltage;
MSOP, TDFN Grade C Package
ISL28127
ISL28227
-10
-
TCVOS
Offset Voltage Drift;
SOIC Package
ISL28127
ISL28227
ISL28127
-0.5
-0.75
-0.80
0.1
0.1
0.1
0.5
µV/°C
µV/°C
µV/°C
0.75
0.80
Offset Voltage Drift;
MSOP, Grade B
Offset Voltage Drift;
TDFN, Grade B
ISL28127
ISL28227
-0.90
-0.75
-1
0.1
0.1
0.1
0.90
0.75
1
µV/°C
µV/°C
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade B
Offset Voltage Drift;
MSOP, TDFN, Grade C
ISL28127
ISL28227
FN6633.6
December 16, 2010
6
ISL28127, ISL28227
Electrical Specifications V ±5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the
S
CM
O
A
operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
IOS
DESCRIPTION
CONDITIONS
(Note 8)
TYP
1
(Note 8)
UNIT
nA
Input Offset Current
-10
-12
10
-12
-3
10
12
10
12
3
-
1
-
nA
nA
nA
V
IB
Input Bias Current
VCM
Common Mode Input Voltage Range
Guaranteed by CMRR
-
-2
-
2
V
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
V
CM = -3V to +3V
115
115
120
-
-
-
dB
dB
VCM = -2V to +2V
VS = ±2.25V to ±5V
VS = ±3V to ±5V
115
115
125
-
-
-
dB
dB
AVOL
VOH
Open-Loop Gain
VO = -3V to +3V
RL = 10kΩ to ground
1000
1500
-
V/mV
Output Voltage High
RL = 10kΩ to ground
RL = 2kΩ to ground
RL = 10kΩ to ground
RL = 2kΩ to ground
3.5
3.65
-
-
V
V
3.2
-
3.4
3.5
-
3.1
-
-
V
V
V
VOL
Output Voltage Low
-
-
-
-
-
-
-
-3.65
-3.5
-3.2
-3.4
-3.1
2.8
3.7
-
-
-3.5
-
V
IS
Supply Current/Amplifier
Short-Circuit
2.2
-
mA
mA
mA
ISC
±45
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
Total Harmonic Distortion + Noise
-
-
10
-
-
MHz
%
THD + N
1kHz, G = 1, Vo = 2.5VRMS
,
0.0034
RL = 2kΩ
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 2kΩOH
-
-
±3.6
36
-
-
V/µs
ns
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
,
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
,
-
-
-
38
1.6
4.2
-
-
-
ns
µs
µs
ts
Settling Time to 0.1%
AV = -1, VOUT = 4VP-P
,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
Settling Time to 0.01%
AV = -1, VOUT = 4VP-P
,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6633.6
December 16, 2010
7
ISL28127, ISL28227
Typical Performance Curves V = ±15V, VCM = 0V, R = Open, unless otherwise specified.
S
L
100
100
80
VS = ±19V
V = 1
60
A
40
20
0
10
-20
-40
-60
-80
-100
V
R
L
R
A
= 38V
= 10k
+
L
C
= 3.5pF
= 10, R = 100k
= 10,000
g
V
f
1
0.1
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1k
10k
100k
TIME (s)
FREQUENCY (Hz)
FIGURE 3. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
FIGURE 4. INPUT NOISE VOLTAGE SPECTRAL DENSITY
130
120
110
100
90
80
70
60
50
100
10
1
PSRR+ and PSRR- V = ±5V
S
VS = ±19V
AV = 1
R
C
= INF
= 5.25pF
= +1
L
L
A
V
V
S
= 1V
P-P
40 PSRR+ and PSRR- V = ±15V
S
30
20
10
0
-10
0.1
10M
10
100
1k
10k
100k
1M
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 6. PSRR vs FREQUENCY, VS = ±5V, ±15V
FIGURE 5. INPUT NOISE CURRENT SPECTRAL DENSITY
100
50
130
V
= ±5V
S
120
110
100
90
80
70
60
50
40
30
20
10
0
V
= ±2.25V
S
V = ±5
S
V
= ±15V
S
0
V
= ±15
S
R
C
= INF
L
= 5.25pF
= +1
-50
-100
L
A
V
V
= 1V
CM
P-P
-10
10M
-50
0
50
TEMPERATURE (°C)
100
150
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 8. VOS vs TEMPERATURE vs VSUPPLY
FIGURE 7. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V
FN6633.6
December 16, 2010
8
ISL28127, ISL28227
Typical Performance Curves V = ±15V, VCM = 0V, R = Open, unless otherwise specified. (Continued)
S
L
5000
4000
3000
2000
1000
0
5000
4000
3000
2000
1000
0
V
= ±15
S
V
= ±15
S
-1000
-2000
-3000
-4000
-5000
-1000
-2000
-3000
-4000
-5000
V = ±5
S
V = ±5
S
-50
0
50
100
150
-50
-25
0
25
50
75
100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. IB+ vs TEMPERATURE vs SUPPLY VOLTAGE
FIGURE 10. IB- vs TEMPERATURE vs SUPPLY VOLTAGE
60
5000
29 UNITS
4000
3000
2000
1000
0
AVERAGE
40
20
+25°C
V
= ±15
S
0
+125°C
V = ±5
S
-1000
-2000
-3000
-4000
-5000
-20
-40°C
-40
-60
-15
-10
-5
0
5
10
15
-50 -25
0
25
50
75
100 125 150
INPUT COMMON MODE VOLTAGE
TEMPERATURE (°C)
FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
FIGURE 11.
IOS vs TEMPERATURE vs SUPPLY VOLTAGE
600
500
400
300
200
100
0
600
V
= ±15V
V = ±5V
S
S
500
400
300
200
100
0
-70 -55 -40 -25 -10
5
20 35
50 65
-70 -55 -40 -25 -10
5
20 35
50
65
V
(µV)
V
(µV)
OS
OS
FIGURE 13. INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V
FIGURE 14. INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V
FN6633.6
December 16, 2010
9
ISL28127, ISL28227
Typical Performance Curves V = ±15V, VCM = 0V, R = Open, unless otherwise specified. (Continued)
S
L
30
25
20
15
30
Vs = ±5V
Vs = ±15V
25
20
15
10
5
10
5
0
0
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
-0.7 -0.5 -0.3 -0.1
0.1
0.3
0.5
0.7
V
TC (µV/°C)
V
TC (µV/°C)
OS
OS
FIGURE 15. OFFSET VOLTAGE DRIFT DISTRIBUTION, VS = ±15V
FIGURE 16. OFFSET VOLTAGE DRIFT DISTRIBUTION, VS = ±5V
35
40
V = ±5V
s
V = ±15V
s
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-22.5
-15
-7.5
I
0
7.5
15
22.5
-25 -20 -15 -10 -5
0
5
10 15 20 25
I
TC (pA/°C)
TC (pA/°C)
B+
B+
FIGURE 18. IB+ INPUT BIAS CURRENT DRIFT DISTRIBUTION,
S = ±5V
FIGURE 17. IB+ INPUT BIAS CURRENT DRIFT DISTRIBUTION,
V
V
S = ±15V
45
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V = ±15V
V
= ±5V
s
s
0
0
-27
-18
-9
0
9
18
27
-30 -24 -18 -12 -6
0
6
12 18 24 30
I
TC (pA/°C)
B-
I
B-
TC (pA/°C)
FIGURE 19. IB- INPUT BIAS CURRENT DRIFT DISTRIBUTION,
S = ±15V
FIGURE 20. IB- INPUT BIAS CURRENT DRIFT DISTRIBUTION,
S = ±5V
V
V
FN6633.6
December 16, 2010
10
ISL28127, ISL28227
Typical Performance Curves V = ±15V, VCM = 0V, R = Open, unless otherwise specified. (Continued)
S
L
70
60
50
40
30
20
10
0
50
V
= ±15V
V = ±5V
S
S
45
40
35
30
25
20
15
10
5
0
-27
-18
-9
0
9
18
27
-30 -24 -18 -12 -6
0
6
12 18 24 30
I
TC (pA/°C)
I
OS
TC (pA/°C)
OS
FIGURE 22. INPUT OFFSET CURRENT DISTRIBUTION, VS = ±5V
FIGURE 21. INPUT OFFSET CURRENT DISTRIBUTION, VS = ±15V
14.2
-13.1
50 UNITS
-13.2
-13.3
-13.4
-13.5
-13.6
-13.7
-13.8
-13.9
-14.0
-14.1
-14.2
MEDIAN
RL = 2k
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
50 UNITS
MEDIAN
RL = 100k
R
= 100k
L
RL = 2k
-40
-20
0
20
40
60
80
100 120
-40
-20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 24. VOL vs TEMPERATURE, VS = ±15V
FIGURE 23. VOH vs TEMPERATURE, VS = ±15V
200
180
160
140
120
100
80
200
180
160
140
120
100
80
PHASE
PHASE
60
60
40
20
40
20
GAIN
GAIN
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
RL = 10k
RL = 10k
CL = 10pF
CL = 100pF
SIMULATION
SIMULATION
0.1m1m 10m100m 1 10 100 1k 10k100k1M10M100M
FREQUENCY (Hz)
0.1m1m 10m100m 1 10 100 1k 10k100k1M10M100M
FREQUENCY (Hz)
FIGURE 25. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
FIGURE 26. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL = 10kΩ, CL = 10pF
RL = 10kΩ, CL = 100pF
FN6633.6
December 16, 2010
11
ISL28127, ISL28227
Typical Performance Curves V = ±15V, VCM = 0V, R = Open, unless otherwise specified. (Continued)
S
L
70
60
50
40
30
20
10
0
15
13
11
9
Rf = Rg = 100k
A
V = 1000
Rg = 100, Rf = 100k
Rg = 1k, Rf = 100k
Rf = Rg = 10k
Rf = Rg = 1k
A
V = 100
VS = ±15V
CL = 3.5pF
RL = INF
7
5
VOUT = 100mVP-P
AV = 10
3
VS = ±15V
L = 10k
Rf = Rg = 100
R
Rg = 10k, Rf = 100k
AV = 1
1
CL = 3.5pF
AV = +2
-1
-3
-5
V
OUT = 100mVP-P
Rg = OPEN, Rf = 0
1k
10k
FREQUENCY (Hz)
-10
100
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 27. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 28. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
Rf/Rg
2
7
RL = 10k
VS = ±15V
6
1
RL = 10k
RL = 1k
5
4
AV = +1
VOUT = 100mVP-P
CL = 1000pF
CL = 220pF
0
3
-1
RL = 499
CL = 100pF
2
-2
-3
-4
-5
RL = 100
RL = 49.9
CL = 25.5pF
1
VS = ±15V
CL = 3.5pF
0
AV = +1
-1
-2
-3
CL = 3.5pF
VOUT = 100mVP-P
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
FIGURE 29. GAIN vs FREQUENCY vs RL
FIGURE 30. GAIN vs FREQUENCY vs CL
1
0
6
VS = ±2.25V
5
4
VS = ±15V
3
C
L = 3.5pF
2
AV = 1
Rf = 0 Rg = inf
VS = ±5V
1
-1
-2
-3
VOUT = 10VP-P
0
VS = ±15V
1
CL = 3.5pF
L = 10k
AV = +1
-2
-3
-4
-5
-6
RL = 2k
R
RL = 10k
VOUT = 100mVP-P
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
0
5
10
15
20
25
30
TIME (µs)
FIGURE 31. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 32. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
FN6633.6
December 16, 2010
12
ISL28127, ISL28227
Typical Performance Curves V = ±15V, VCM = 0V, R = Open, unless otherwise specified. (Continued)
S
L
80
60
40
20
0
2.4
2.0
1.6
1.2
0.8
0.4
0
VS = ±15V, RL = 2k, 10k
VS = ±5V, RL = 2k, 10k
VS = ±5V, ±15V
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
20
40
60
80
RL = 2k
CL = 3.5pF
V = 1
VOUT = 100mVP-P
CL = 3.5pF
AV = 1
A
V
OUT = 4VP-P
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (ms)
0
5
10
15
20
25
30
35
40
TIME (µs)
FIGURE 34. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V,
±15V
FIGURE 33. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS =
±5V, ±15V
0.26
0.22
0.08
0.04
0.10
0.06
0.02
-0.02
-0.06
2
0
0.06
0.02
15
13
11
9
OUTPUT
INPUT
-2
-0.02
-0.06
-0.10
-0.14
-0.18
-0.20
-0.26
VS = ±15V
L = 10k
CL = 3.5pF
V = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
R
-4
VS = ±15V
L = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
IN = 200mVP-P
R
A
-6
7
-8
5
V
-10
-12
INPUT
3
1
OUTPUT
25
-14
40
-1
0
5
10
15
20
25
30
35
0
5
10
15
20
30
35
40
TIME (µs)
TIME (µs)
FIGURE 36. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS
= ±15V
FIGURE 35. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS =
±15V
90
80
VS = ±15V
R
L = 10k
V = 1
70
60
50
40
30
20
10
0
A
VOUT = 100mVP-P
10
100
1000
10000
CAPACITANCE (pF)
FIGURE 37. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
FN6633.6
December 16, 2010
13
ISL28127, ISL28227
Applications Information
Functional Description
V+
The ISL28127 and ISL28227 are single and dual, low noise
10MHz BW precision op amps. Both devices are fabricated in a
new precision 40V complementary bipolar DI process. A super-
beta NPN input stage with input bias current cancellation
provides low input bias current (1nA typical), low input offset
voltage (10µV typ), low input noise voltage (3nV/√Hz), and low
1/f noise corner frequency (5Hz). These amplifiers also feature
high open loop gain (1500V/mV) for excellent CMRR (120dB)
and THD+N performance (0.0002% @ 3.5VRMS, 1kHz into 2kΩ).
A complimentary bipolar output stage enables high capacitive
load drive without external compensation.
R
-
IN
-
V
-
V
IN
OUT
R
+
IN
+
V
+
R
IN
L
V-
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING -
DIFFERENTIAL INPUT
Output Current Limiting
The output current is internally limited to approximately ±45mA
at +25°C and can withstand an short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the dual op amp. Continuous
operation under these conditions may degrade long term
reliability.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). Parameter variation with operating voltage is shown
in the “Typical Performance Curves” beginning on page 8.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, and an additional
anti-parallel diode pair across the inputs (see Figures 38 and 39).
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28127 and ISL28227 are immune to output
phase reversal, even when the input voltage is 1V beyond the
supplies.
V+
Power Dissipation
-
V
OUT
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
R
IN
+
V
R
IN
L
V-
FIGURE 38. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
For unity gain applications (see Figure 38) where the output is
connected directly to the non-inverting input a current limiting
resistor (RIN) will be needed under the following conditions to
protect the anti-parallel differential input protection diodes.
(EQ. 1)
T
= T
+ θ xPD
MAX JA MAXTOTAL
JMAX
where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
• The amplifier input is supplied from a low impedance source.
each amplifier in the package (PDMAX
)
• The input voltage rate-of-rise (dV/dt) exceeds the maximum
slew rate of the amplifier (±3.6V/µs).
• PDMAX for each amplifier can be calculated using Equation 2:
V
OUTMAX
If the output lags far enough behind the input, the anti-parallel
input diodes can conduct. For example, if an input pulse ramps
from 0V to +10V in 1µs, then the output of the ISL28x27 will reach
only +3.6V (slew rate = 3.6V/µs) while the input is at 10V, The
input differential voltage of 6.4V will force input ESD diodes to
conduct, dumping the input current directly into the output stage
and the load. The resulting current flow can cause permanent
damage to the ESD diodes. The ESD diodes are rated to 20mA,
and in the previous example, setting RIN to 1k resistor (see Figure
38) would limit the current to < 6.4mA, and provide additional
protection up to ±20V at the input.
------------------------
PD
= V × I
+ (V - V ) ×
OUTMAX
MAX
S
qMAX
S
(EQ. 2)
R
L
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
In applications where one or both amplifier input terminals are at
risk of exposure to high voltage, current limiting resistors may be
needed at each input terminal (see Figure 39 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
FN6633.6
December 16, 2010
14
ISL28127, ISL28227
LICENSE STATEMENT
ISL28127 and ISL28227 SPICE Model
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
Figure 40 shows the SPICE model schematic and Figure 41 shows
the net list for the ISL28127 and ISL28227 SPICE model. The
model is a simplified version of the actual device and simulates
important AC and DC parameters. AC parameters incorporated
into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain
and Phase. The DC parameters are VOS, IOS, total supply current
and output voltage swing. The model does not model input bias
current. The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is adjusted
for 128dB with the dominate pole at 5Hz. The CMRR is set higher
than the “Electrical Specifications” Table to better match design
simulations (150dB, f = 50Hz). The input stage models the actual
device to present an accurate AC representation. The model is
configured for ambient temperature of +25°C.
The Licensee may not sell, loan, rent, or license the macro-
model, in whole, in part, or in modified form, to anyone outside
the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macro-model for use within
their company only.
Figures 42 through 57 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Closed Loop Gain vs Rf/Rg, Closed Loop Gain vs RL, Closed Loop
Gain vs CL, Large Signal 10V Step Response, Open Loop Gain
Phase and Simulated CMRR vs Frequency.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FN6633.6
December 16, 2010
15
ISL28127, ISL28227
.
V++
V++
R3
R4
IEE1
4
5
96E-6
4.45k
4.45k
4
5
CASCODE
CASCODE
6
7
Q4
Q5
3
D1
DX
C4
2
2.5pF
SUPERB
SUPERB
Vin-
V5
V
-
Q1 Q2
IN
C5
2.5pF
R1
8
5E11
24
25
EOS
C6
2pF
1
IOS
Mirror
Vc
D12
DN
0.1V
R17
VCM
+
-
+
Vmid
Q3
-
1E-9
9
IEE
R2
200E-6
377.4
In+
+
VOS
5E11
En
10E-6
-
V
+
IN
V--
VCM
Voltage Noise
Input Stage
V++
V++
D2
DX
D4
DX
G1
G3
G5
L1
13
10
4
3.18E-3
+
+
+
-
+
-
+
-
R5
1
R7
C2
R9
1
V1
V3
17
55.55pF
R11
1
1.86V
1.86V
572.9E6
-
-
5
11
Vc
Vg
Vmid
Vg
Vc
R12
1
R6
1
R8
R10
1
C3
Vmid
G4
G6
G2
572.9E6
55.55pF
18
+
-
+
-
-
+
-
+
-
+
V4
V2
L2
1.86V
1.86V
12
14
VCM
3.18E-3
D5
DX
D3
DX
V--
V--
VCM
ST Gain Stage
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
1
V++
D8
DX
D9
DX
G7
V+
V+
+
-
+
E2
R15
90
-
-
+
22
23
V5
DX
DX
D6
D7
20
21
ISY
V
OUT
VOUT
1.12V
2.2mA
Vg
V6
1.12V
R16
90
V-
G8
-
+
+
-
+
-
-
+
D10
DY
D11
DY
-
E3
V-
+
V--
G9
G10
Supply Isolation Stage
Output Stage
FIGURE 40. SPICE SCHEMATIC
FN6633.6
December 16, 2010
16
ISL28127, ISL28227
* source ISL28127_SPICEmodel
R_R7
VG V++ 572.958E6 TC=0,0
V-- VG 572.958E6 TC=0,0
VG V++ 55.55e-12 TC=0,0
V-- VG 55.55e-12 TC=0,0
13 V++ DX
* Revision C, August 8th 2009 LaFontaine
* Model for Noise, supply currents, 150dB f=50Hz
CMRR, *128dB f=5Hz AOL
R_R8
C_C2
C_C3
D_D4
D_D5
V_V3
V_V4
*
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
V-- 14 DX
13 VG 1.86
VG 14 1.86
*
*
*
*
*
|
|
|
|
|
-input
*Mid supply Ref
|
|
|
|
+Vsupply
R_R9
R_R10
I_ISY
E_E2
E_E3
*
VMID V++ 1 TC=0,0
V-- VMID 1 TC=0,0
V+ V- DC 2.2E-3
|
|
|
-Vsupply
|
|
output
|
V++ 0 V+ 0 1
V-- 0 V- 0 1
.subckt ISL28127subckt Vin+ Vin-V+ V- VOUT
* source ISL28127_SPICEMODEL_0_0
*
*Common Mode Gain Stage with Zero
*Voltage Noise
G_G5
G_G6
R_R11
R_R12
L_L1
L_L2
*
V++ VC VCM VMID 31.6228e-9
V-- VC VCM VMID 31.6228e-9
VC 17 1 TC=0,0
E_En
IN+ VIN+ 25 0 1
25 0 377.4 TC=0,0
24 25 DN
R_R17
D_D12
V_V7
18 VC 1 TC=0,0
24 0 0.1
17 V++ 3.183e-3
*
18 V-- 3.183e-3
*Input Stage
I_IOS
C_C6
IN+ VIN- DC 1e-9
IN+ VIN- 2E-12
*Output Stage with Correction Current Sources
G_G7
G_G8
G_G9
G_G10
D_D6
D_D7
D_D8
D_D9
D_D10
D_D11
V_V5
V_V6
R_R15
R_R16
*
VOUT V++ V++ VG 1.11e-2
V-- VOUT VG V-- 1.11e-2
22 V-- VOUT VG 1.11e-2
23 V-- VG VOUT 1.11e-2
VG 20 DX
R_R1
VCM VIN- 5e11 TC=0,0
IN+ VCM 5e11 TC=0,0
2 VIN- 1 SuperB
3 8 1 SuperB
R_R2
Q_Q1
Q_Q2
Q_Q3
V-- 1 7 Mirror
21 VG DX
Q_Q4
4 6 2 Cascode
V++ 22 DX
Q_Q5
5 6 3 Cascode
V++ 23 DX
R_R3
4 V++ 4.45e3 TC=0,0
5 V++ 4.45e3 TC=0,0
V-- 22 DY
R_R4
V-- 23 DY
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
20 VOUT 1.12
VOUT 21 1.12
D_D1
I_IEE
I_IEE1
V_VOS
E_EOS
*
6 7 DX
VOUT V++ 9E1 TC=0,0
V-- VOUT 9E1 TC=0,0
1 V-- DC 200e-6
V++ 6 DC 96e-6
9 IN+ 10e-6
8 9 VC VMID 1
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
*1st Gain Stage
G_G1
G_G2
R_R5
R_R6
D_D2
D_D3
V_V1
V_V2
*
V++ 11 4 5 0.0487707
.model Cascode npn
V-- 11 4 5 0.0487707
11 V++ 1 TC=0,0
V-- 11 1 TC=0,0
10 V++ DX
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
.model Mirror pnp
V-- 12 DX
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
10 11 1.86
11 12 1.86
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
*2nd Gain Stage
G_G3
G_G4
V++ VG 11 VMID 4.60767E-3
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28127subckt
V-- VG 11 VMID 4.60767E-3
FIGURE 41. SPICE NET LIST
FN6633.6
December 16, 2010
17
ISL28127, ISL28227
Characterization vs Simulation Results
100
10
1
100
10
1
V
= ±19V
= 1
S
A
V
V(INOISE)
1
0.1
1
10
100
1k
10k
100k
0.1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 43. SIMULATED INPUT NOISE VOLTAGE
FIGURE 42. CHARACTERIZED INPUT NOISE VOLTAGE
70
60
50
40
30
20
10
0
70
A
= 1000
= 100
= 10
R
= 100, R = 100k
f
A
= 1000
= 100
= 10
R
= 100, R = 100k
f
V
g
V
g
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
R
= 1k, R = 100k
f
g
g
A
A
V
V
V
= ±15V
= 3.5pF
= INF
S
L
C
R
L
V
= 100mV
OUT
P-P
A
A
V
V
R
= 10k, R = 100k
f
R
= 10k, R = 100k
f
g
g
A
= 1
A
= 1
V
V
R
= OPEN, R = 0
f
R
= OPEN, R = 0
f
g
g
-10
-10
10k
FREQUENCY (Hz)
100
1k
100k
1M
10M
100M
10k
FREQUENCY (Hz)
100
1k
100k
1M
10M
100M
FIGURE 44. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
FIGURE 45. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
15
15
R = R = 100k
R = R = 100k
f
g
f
g
13
11
9
13
11
9
R = R = 10k
f
g
R = R = 10k
f
g
7
R = R = 1k
7
f
g
R = R = 1k
f
g
5
5
3
V
= ±15V
= 10k
3
V
= ±15V
= 10k
S
R = R = 100
S
R = R = 100
f
g
f
g
R
C
A
R
C
A
L
L
L
L
1
1
= 3.5pF
= +2
= 3.5pF
= +2
-1
-3
-5
-1
-3
-5
V
V
V
= 100mV
V
= 100mV
OUT
P-P
OUT
P-P
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 47. SIMULATED CLOSED LOOP GAIN vs Rf/Rg
FIGURE 46. CHARACTERIZED CLOSED LOOP GAIN vs Rf/Rg
FN6633.6
December 16, 2010
18
ISL28127, ISL28227
Characterization vs Simulation Results(Continued)
2
2
R
R
= 10k
= 1k
L
L
1
1
R
= 10k
L
0
0
R
= 1k
L
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
R
R
= 499
= 100
L
R
= 499
L
L
R
= 100
L
V
= ±15V
= 3.5pF
= +1
V
= ±15V
= 3.5pF
= +1
S
S
R
= 49.9
L
C
A
C
A
L
L
V
V
R
= 49.9
L
V
= 100mV
V
= 100mV
OUT
P-P
OUT
P-P
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
FIGURE 48. CHARACTERIZED CLOSED LOOP GAIN vs RL
FIGURE 49. SIMULATED CLOSED LOOP GAIN vs RL
7
7
6
V
R
A
= ±15V
= 10k
= +1
V
R
= ±15V
= 10k
= +1
S
6
5
S
C
= 1000pF
L
L
L
5
C
= 1000pF
A
V
L
V
V
= 100mV
P-P
4
OUT
V
= 100mV
4
OUT P-P
C
= 220pF
L
3
3
C
= 100pF
L
2
2
C
= 220pF
= 100pF
L
C
= 25.5pF
1
L
1
0
C
0
L
C
= 25.5pF
L
-1
-2
-3
-1
-2
-3
C
= 3.5pF
L
C
= 3.5pF
1M
L
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
10k
1k
100k
10M
100M
FREQUENCY (Hz)
FIGURE 50. CHARACTERIZED CLOSED LOOP GAIN vs CL
FIGURE 51. SIMULATED CLOSED LOOP GAIN vs CL
6
5
4
6
5
4
V
C
= ±15V
= 3.5pF
= 1
S
L
3
V
C
= ±15V
= 3.5pF
= 1
S
L
3
2
2
1
A
V
A
V
R = 0, R = INF
f
g
R = 0, R = INF
1
f
g
V
= 10V
OUT
P-P
V
= 10V
0
OUT
P-P
0
1
1
-2
-3
-4
-5
-6
R
= 10k
L
-2
-3
-4
-5
-6
R
= 2k
L
R
= 10k
L
0
5
10
15
TIME (µs)
20
25
30
0
5
10
15
TIME (µs)
20
25
30
FIGURE 53. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
FIGURE 52. CHARACTERIZED LARGE SIGNAL 10V STEP
RESPONSE
FN6633.6
December 16, 2010
19
ISL28127, ISL28227
Characterization vs Simulation Results(Continued)
200
150
100
50
200
180
160
140
120
100
80
60
40
20
0
PHASE
PHASE
GAIN
GAIN
0
R
C
= 10k
= 10pF
-20
-40
-60
-80
-100
L
L
R
C
= 10k
L
L
-50
-100
= 10pF
MODEL V SET TO ZERO
OS
SIMULATION
FOR THIS TEST
0.1Hz
10Hz
1.0k
100k
10M
0.1m 1m 10m100m
1
10 100 1k 10k 100k 1M 10M100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 54. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
150
100
50
130
V
= ±5V
S
120
110
100
90
80
70
60
50
40
30
20
10
0
V
= ±2.25V
S
V
= ±15V
S
R
C
A
= INF
L
L
GENERATED USING FULL
MODEL. CMRR DELTA INPUT
0
= 5.25pF
= +1
BASE VOLTAGE/V
V
CM
V
= 1V
INPUT VOLTAGE
-50
10m
CM
P-P
-10
10M
1.0Hz 100Hz 10k
1.0M
100M 10G 1.0T
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 56. CHARACTERIZED CMRR vs FREQUENCY
FIGURE 57. SIMULATED CMRR vs FREQUENCY
FN6633.6
December 16, 2010
20
ISL28127, ISL28227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
REVISION
FN6633.6
DATE
CHANGE
12/13/10 page 3: The ISL28227 8 LD TDFN Pin configuration: Vout_A and Vout_B labels on pins 1 and 7 changed to VoutA and VoutB
Figure 8: labeled red curve Vs = ±5V and blue curve Vs = ±15V.
12/10/10 -Converted to New Intersil Template
-Added AN1509 in Related Literature on page 1
-Removed Titles from Graphics on page 1 and replaced with Figure names
-Changed copyright to legal's suggested verbiage on page 1
-Updated Ordering Information table on page 2. Removed Coming Soon for ISL28127FRTBZ and ISL28127FUBZ parts.
Added in the Vos (MAX) numbers in those rows (75 and 70 respectively).
-Changed Tape and Reel Note in ordering information to "Add T*…" to include all Tape and Reel additions
-Updated Electrical Spec Table page 4 and page 5 for Vos and TCVos
oAdded data row for Offset Voltage; MSOP Grade B Package; ISL28127
oAdded data row for Offset Voltage; TDFN Grade B Package; ISL28127
oAdded data row for Offset Voltage Drift; MSOP Grade B Package; ISL28127
oAdded data row for Offset Voltage Drift; TDFN Grade B Package; ISL28127
oRemoved - Temperature data established by characterization from conditions (New standard note covers this verbiage)
oChanged Note: "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested". TO: Compliance to datasheet limits is
assured by one or more methods: production test, characterization and/or design.
-Updated Typical Performance Curves
oUpdated typical plot of Vos vs Temp for Figure 8.
oAdded: IB+ vs Temp vs Vsupply plot; IB- vs Temp vs Vsupply plot; Ios vs Temp vs Vsupply plot; Figures 9, 10, 11
oAdded: Vos distribution Vs=15V plot; Vos distribution Vs=5V plot; TCVos distribution Vs=15V plot; TCVos distribution Vs=5V
plot; TCIB+ distribution Vs=15V plot; TCIB+ distribution Vs=5V plot; TCIB- distribution Vs=15V plot; TCIB- distribution Vs=5V
plot; TCIos distribution Vs=15V plot; TCIos distribution Vs=5V plot (Figures 13 thru 22)
FN6633.5
FN6633.4
9/10/10 - Updated ordering information by removing Note 2, which referenced “-T13” tape and reel option and revised Note 1 to
include ”-T7A” tape and reel option. Removed Note reference next to part numbers and placed under part number in table
head indicating that it references all parts. Change shows that all parts now have -T7, -T7A, and -T13 tape and reel options.
7/2/10 In “Ordering Information” on page 2:
Removed “Coming Soon” from ISL28127FRTZ, ISL28227FRTBZ, ISL28227FRTZ, ISL28227FUBZ & ISL28227FUZ.
Updated the part marking for ISL28127FRTBZ from “127Z” to “8127”
Updated the part marking for ISL28127FRTZ from “-C 127Z” to “-C 8127”
Updated the part marking for ISL28227FRTBZ from “227Z” to “8227”
Updated the part marking for ISL28227FRTZ from “-C 227Z” to “-C 8227”
Added VOS of 75µV for ISL28227FRTBZ
Added VOS of 75µV for ISL28227FUBZ
Added Evaluation Boards ISL28127MSOPEVAL1Z and ISL28227SOICEVAL2Z
In “Thermal Information” on page 4, for 8 Ld TDFN, corrected Theta JA note from Note 5 to Note 4.
In VS ±15V “Electrical Specifications” table on page 4, added VOS specs for ISL28227 MSOP, TDFN Grade B Packages. Added
TCVOS specs for ISL28227 MSOP, TDFN Grade B Packages
Changed TYP for “Offset Voltage; MSOP, TDFN Grade C Package” from 10µV to -10µV
In VS ±5V “Electrical Specifications” table on page 6, added VOS specs for SOIC ISL28227. Added VOS specs for MSOP, TDFN
Grade B and C Packages. Added TCVOS specs for SOIC ISL28227. Added TCVOS specs for MSOP, TDFN Grade B and C
Packages
FN6633.3
3/11/10 PODs M8.118 and L8.3x3A - Updated to new intersil format by adding land pattern and moving dimensions from table onto
drawing.
3/3/10 On page 2:
Under "Ordering Information”
ISL28227FBZ: Changed Vos max from 80µV to 75µV
On page 4:
Changed:
1. ISL28227 SOIC Room Temp limit for Vos from 80µV (MAX) and -80µV (MIN) to 75µV (MAX) and -75µV (MIN).
2. ISL28227 SOIC Full Temp limit for Vos from 160µV (MAX) and -160µV (MIN) to 150µV (MAX) and -150µV (MIN)
3. ISL28227 SOIC limit for TCVos from 0.8µV (MAX) and -0.8µV (MIN) to 0.75µV (MAX) and -0.75µV (MIN)
FN6633.6
December 16, 2010
21
ISL28127, ISL28227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
REVISION
DATE
CHANGE
FN6633.3
(Continued)
3/2/10 In “Absolute Maximum Ratings” on page 4, HBM for ISL28227 changed from “4kV” to “6kV”
In “Thermal Information” on page 4, Tjc values for ISL28227 changed:
For MSOP from “50” to “45”
For SOIC from “60” to “55”
2/25/10 In the “Ordering Information” (page 2):
Part Number
Part Marking
Vos (Max) (uV)
ISL28127FRTBZ
ISL28127FRTZ
ISL28127FUBZ
ISL28127FUZ
TBD instead of 70
-C 127Z instead of 127Z C
TBD instead of 70
150 instead of 70
8127Z -C instead of 8127Z
Removed “Coming Soon) for ISL28127FUZ package
ISL28227FBZ
Removed “Coming Soon) for ISL28227FBZ package
ISL28227FRTBZ
80 instead of 70
TBD instead of 70
150 instead of 70
ISL28227FRTZ
ISL28227FUZ
-C 227Z instead of 227Z C
8227Z -C instead of 8227Z
Added the following row of data
ISL28227FUBZ 8227Z
TBD
In the “Electrical specifications” on page 4 and page 6 the following changes were made. The change applies to the same
spec found on page 4 and page 6.
VOS Offset Voltage; SOIC Package, ISL28127: Added -70 to MIN across room temp and -120 MIN across full temp
VOS Offset Voltage; SOIC Package, ISL28227: Added -80 to MIN across room temp and -160 MIN across full temp
VOS Offset Voltage; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -150 to MIN across room temp and -
250 MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28127: Added -0.5 to MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28227: Added -0.8 to MIN across full temp
TCVOS Offset Voltage Drift; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -1 to MIN across full temp
IOS Input Offset Current: Added -10 to MIN across room temp and -12 to MIN across full temp
IB Input Bias Current:Added -10 to MIN across room temp and -12 to MIN across full temp
2/19/10 In the “Ordering Information” (page 2), added differentiated part numbers for B-grade and C-grade for TDFN and MSOP.
In “Absolute Maximum Ratings” on page 4, added ESD and latch-up information.
In “Thermal Information” on page 4, broke out Theta JA to list the single and dual and added Theta JC.
FN6633.2
1/29/10 Added license statement for P-Spice Model.
Updated Spice Schematic by adding capacitors
C4, C5 and C6
Updated Spice Net List as follows:
From:
Revision B, July 23 2009
To:
Revision C, August 8th 2009 LaFontaine
From:
source ISL28127_SPICEMODEL_7_9
To:
source ISL28127_SPICEMODEL_0_0
Added after I_IOS:
C_C6
IN+ VIN- 2E-12
Added after R_R4:
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
From:
.ends ISL28127
To:
.ends ISL28127subckt
Replaced POD MDP0027 with M8.15E to match ASYD in Intrepid (no dimension changes; the PODs are the same. The
change was to update to the Intersil format, moving dimensions from table onto drawing and adding land pattern)
FN6633.6
December 16, 2010
22
ISL28127, ISL28227
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
REVISION
FN6633.1
DATE
CHANGE
9/14/09 “Functional Description” on page 14. Corrected low 1/f noise corner frequency from 3Hz to 5Hz to match Figure 2 on page 1.
Corrected high open loop gain from 1400V/mV to 1500V/mV to match “Open-Loop Gain” on page 5 spec table.
“Operating Voltage Range” on page 14. Removed following 2 sentences since there are no graphs illustrating common
mode voltage sensitivity vs temperature or VOS as a function of supply voltage and temperature:
“The input common mode voltage sensitivity to temperature is shown in Figure 3 (±15V). Figure 20 shows VOS as a function
of supply voltage and temperature with the common mode voltage at 0V for split supply operation.”
9/2/09 Added Theta JC in “Thermal Information” on page 4 for TDFN package
7/21/09 Updated Features to show only key features and updated applications section. Added Typical Application Circuit and
performance graph, Updated Ordering Information to match Intrepid and added POD's L8.3x3A and M8.118, also added
MSL level as part of new format. Added TDFN pinouts, updated pin descriptions to include TDFN pinouts, Added Theta Ja in
Thermal information for TDFN and MSOP packages. Added Revision History and Products Text with device info links. Added
SPICE Model with referencing text and Net List.
FN6633.0
5/28/09 Techdocs Issued File Number FN6633. Initial release of Datasheet with file number FN6633 making this a Rev 0.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL28127, ISL28227
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6633.6
December 16, 2010
23
ISL28127, ISL28227
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6633.6
December 16, 2010
24
ISL28127, ISL28227
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN6633.6
December 16, 2010
25
ISL28127, ISL28227
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.036
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN6633.6
December 16, 2010
26
相关型号：
ISL28130CBZ-T
IC OP-AMP, 46.8 uV OFFSET-MAX, 0.4 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012, SOIC-8, Operational Amplifier
RENESAS
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