ISL28407FRZ-T13 [RENESAS]
QUAD OP-AMP, 1MHz BAND WIDTH, PQCC16, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-16;
| 型号： | ISL28407FRZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | QUAD OP-AMP, 1MHz BAND WIDTH, PQCC16, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-16 放大器 |
| 文件： | 总32页 (文件大小：1564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Single, Dual and Quad Low Noise
Operational Amplifiers
ISL28107, ISL28207, ISL28407 Features
• Low Input Offset . . . . . . . . . . . . . . . . 75µV, Max.
• Input Bias Current . . . . . . . . . . . . . . . . . . . .15pA
• Superb Temperature Drift
- Voltage Offset . . . . . . . . . . . . . 0.65µV/°C, Max.
- Input Current . . . . . . . . . . . . . . . 0.9pA/°C, Max
• Outstanding ESD performance
- Human Body Model . . . . . . . . . . . . . . . . . 4.5kV
- Machine Model . . . . . . . . . . . . . . . . . . . . .500V
- Charged Device Model . . . . . . . . . . . . . . . 1.5kV
• Very Low Voltage Noise, 10Hz . . . . . . . . 14nV/√Hz
• Low Current Consumption (per amp). . . . 0.29mA, Max.
• Gain-bandwidth Product . . . . . . . . . . . . . . . 1MHz
• Wide Supply Range. . . . . . . . . . . . . . . 4.5V to 40V
• Operating Temperature Range . . . -40°C to +125°C
• No Phase Reversal
The ISL28107, ISL28207 and ISL28407 are single, dual
and quad amplifiers featuring low noise, low input bias
current, and low offset and temperature drift. This makes
them the ideal choice for applications requiring both high
DC accuracy and AC performance. The combination of
precision, low noise, and small footprint provides the
user with outstanding value and flexibility relative to
similar competitive parts.
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL28107 is available in an 8 Ld SOIC, MSOP and
TDFN package. The ISL28207 is available in the 8 Ld
SOIC and MSOP packages. The ISL28407 will be offered
in an 14 Ld SOIC, TSSOP and 16 Ld QFN packages. All
devices are offered in standard pin configurations and
operate over the extended temperature range to -40°C
to +125°C.
• Pb-Free (RoHS Compliant)
Related Literature*(see page 26)
Applications*(see page 26)
• Precision Instruments
• See AN1508 “ISL281X7SOICEVAL1Z Evaluation
Board User’s Guide”
• Medical Instrumentation
• Spectral Analysis Equipment
• Active Filter Blocks
• See AN1509 “ISL282X7SOICEVAL2Z Evaluation
Board User’s Guide”
• Microphone Pre-amplifier
• Thermocouples and RTD Reference Buffers
• Data Acquisition
• Power Supply Control
Typical Application
Input Noise Voltage Spectral
Density
C1
1000
8.2nF
V
= ±19V
= 1
+
A
V
V+
-
OUTPUT
100
V
R
R
2
IN
1
+
19.1k 48.7k
3.3nF
C2
V-
10
0.1
Sallen-Key Low Pass Filter (1kHz)
1
10
100
1k
10k
100k
FREQUENCY (Hz)
September 9, 2010
FN6631.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL28107, ISL28207, ISL28407
Ordering Information
PART NUMBER
PART
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 2, 3)
MARKING
ISL28107FBZ
28107 FBZ
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld SOIC
M8.15E
ISL28107FBZ-T7 (Note 1)
ISL28107FBZ-T13 (Note 1)
ISL28107FBZ-T7A (Note 1)
ISL28107FUZ
28107 FBZ
28107 FBZ
28107 FBZ
8107Z
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
8 Ld TDFN
14 Ld SOIC
M8.15E
M8.15E
M8.15E
M8.118
M8.118
M8.118
M8.118
L8.3x3A
L8.3x3A
L8.3x3A
L8.3x3A
M8.15E
M8.15E
M8.15E
M8.15E
L8.3x3A
L8.3x3A
L8.3x3A
L8.3x3A
M14.15
ISL28107FUZ-T7 (Note 1)
ISL28107FUZ-T13 (Note 1)
ISL28107FUZ-T7A (Note 1)
ISL28107FRTZ
8107Z
8107Z
8107Z
107Z
ISL28107FRTZ-T7 (Note 1)
ISL28107FRTZ-T13 (Note 1)
ISL28107FRTZ-T7A (Note 1)
ISL28207FBZ
107Z
107Z
107Z
28207 FBZ
28207 FBZ
28207 FBZ
28207 FBZ
207Z
ISL28207FBZ-T7 (Note 1)
ISL28207FBZ-T13 (Note 1)
ISL28207FBZ-T7A (Note 1)
ISL28207FRTZ
ISL28207FRTZ-T7 (Note 1)
ISL28207FRTZ-T13 (Note 1)
ISL28207FRTZ-T7A (Note 1)
207Z
207Z
207Z
Coming Soon
28407
ISL28407FBZ
Coming Soon
ISL28407FBZ-T7A (Note 1)
28407
28407
28407
28407
28407
28407
28407
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
14 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
16 Ld QFN
M14.15
Coming Soon
ISL28407FVZ (Note 1)
M14.173
M14.173
M14.173
L16.4x4
L16.4x4
L16.4x4
Coming Soon
ISL28407FVZ-T13 (Note 1)
Coming Soon
ISL28407FVZ-T7A (Note 1)
Coming Soon
ISL28407FRZ
Coming Soon
ISL28407FRZ-T13 (Note 1)
16 Ld QFN
Coming Soon
16 Ld QFN
ISL28407FRZ-T7A (Note 1)
ISL28107SOICEVAL1Z
ISL28207SOICEVAL2Z
NOTES:
Evaluation Board
Evaluation Board
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28107, ISL28207 and ISL28407. For more
information on MSL please see techbrief TB363.
FN6631.3
September 9, 2010
2
ISL28107, ISL28207, ISL28407
Pin Configurations
ISL28107
ISL28107
(8 LD TDFN)
TOP VIEW
(8 LD SOIC, MSOP)
TOP VIEW
NC
-IN
+IN
V -
1
2
3
4
8
7
6
5
NC
V+
V
NC
NC
1
2
3
4
8
7
6
5
-IN
+IN
V-
V+
V
- +
- +
OUT
OUT
NC
NC
ISL28207
(8 LD SOIC)
TOP VIEW
ISL28207
(8 LD TDFN)
TOP VIEW
V
_A
V+
V
1
8
OUT
V
A
1
8
V+
OUT
-IN_A
_B
2
3
4
7
6
OUT
-IN_A
2
3
4
7
6
5
V
B
- +
- +
OUT
+IN_A
V-
-IN_B
+ -
+IN_A
V -
-IN_B
+ -
5 +IN_B
+IN_B
ISL28407
(14 LD SOIC, TSSOP)
ISL28407
(16 LD QFN)
TOP VIEW
TOP VIEW
V
_A
14 V
_D
1
2
3
4
OUT
OUT
A
D
-IN_A
13
12
-IN_D
- + + -
15
14
13
16
+IN_A
V +
+IN_D
-IN_D
-IN_A
1
2
3
12
11
10
9
11 V -
A
D
+IN_C
+IN_D
10
9
5
6
7
+IN_B
-IN_B
+IN_A
- + + -
-IN_C
V _C
OUT
B
C
V -
V +
8
V
_B
OUT
B
C
4
+IN_B
+IN_C
6
7
8
5
FN6631.3
September 9, 2010
3
ISL28107, ISL28207, ISL28407
Pin Descriptions
ISL28107
ISL28207
ISL28407
(8 LD SOIC, (8 LD SOIC, (14 LD SOIC,
ISL28407
(16 LD QFN)
PIN
NAME
EQUIVALENT
CIRCUIT
MSOP, TDFN)
TDFN)
TSSOP)
DESCRIPTION
3
-
3
5
-
-
3
-
2
+IN
+IN_A
+IN_B
+IN_C
+IN_D
V-
Circuit 1
Amplifier non-inverting input
-
-
5
4
-
10
12
11
-
9
-
-
11
10
-
4
4
-
Circuit 3
Circuit 1
Negative power supply
Amplifier inverting input
2
-IN
-
2
6
-
2
1
-IN_A
-IN_B
-IN_C
-IN_D
V+
-
6
5
-
9
8
-
-
13
4
12
3
7
8
-
Circuit 3
Circuit 2
Positive power supply
Amplifier output
6
-
-
VOUT
-
1
7
-
1
15
6
VOUT_A
VOUT_B
VOUT_C
VOUT_D
NC
-
7
-
-
8
7
-
14
-
14
13, 16
PD
1, 5, 8
PD
-
-
-
No internal connection
PD
-
PD
Thermal Pad - TDFN and QFN
packages only. Connect thermal pad
to ground or most negative
potential.
V+
V+
V+
500Ω
500Ω
CAPACITIVELY
TRIGGERED
OUT
IN-
IN+
V-
V-
V-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
FN6631.3
September 9, 2010
4
ISL28107, ISL28207, ISL28407
Table of Contents
Absolute Maximum Ratings ................................................................................................................ 6
Thermal Information .......................................................................................................................... 6
Operating Conditions.......................................................................................................................... 6
Electrical Specifications...................................................................................................................... 6
Electrical Specifications...................................................................................................................... 8
Typical Performance Curves ............................................................................................................. .10
Applications Information................................................................................................................... 19
Functional Description...................................................................................................................... 19
Operating Voltage Range.................................................................................................................. 19
Input ESD Diode Protection .............................................................................................................. 19
Output Current Limiting ................................................................................................................... 19
Output Phase Reversal..................................................................................................................... 19
Using Only One Channel................................................................................................................... 19
Power Dissipation............................................................................................................................ 19
ISL28107, ISL28207, ISL28407 SPICE Model...................................................................................... 20
License Statement........................................................................................................................... 20
Characterization vs Simulation Results.............................................................................................. 23
Revision History ................................................................................................................................ 25
Products............................................................................................................................................ 26
Package Outline Drawing ................................................................................................................. 27
Package Outline Drawing ................................................................................................................. 28
Package Outline Drawing ................................................................................................................. 29
Package Outline Drawing ................................................................................................................. 30
Package Outline Drawing ................................................................................................................. 31
Package Outline Drawing ................................................................................................................. 32
FN6631.3
September 9, 2010
5
ISL28107, ISL28207, ISL28407
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . (V-) - 0.5V to (V+) + 0.5V
Min/Max Input Voltage . . . . . . . . (V-) - 0.5V to (V+) + 0.5V
Max/Min Input Current for Input Voltage >V+ or <V- . . . . ±20mA
Output Short-Circuit Duration (1 Output at a Time) . . . Indefinite
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . 4.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Typical)
θ
JA (°C/W)
θJC (°C/W)
8 Ld SOIC (ISL28107, Notes 4, 5) . . .
8 Ld SOIC (ISL28207, Notes 4, 5) . . .
8 Ld MSOP (ISL28107, Notes 4, 5) . .
8 Ld TDFN (ISL28107, Notes 6, 7) .
8 Ld TDFN (ISL28207, Notes 6, 7) .
14 Ld SOIC (ISL28407) . . . . . . . .
14 Ld TSSOP (ISL28407) . . . . . . .
16 Ld QFN (ISL28407). . . . . . . . .
120
105
155
48
60
50
50
7
2
TBD
TBD
TBD
43
TBD
TBD
TBD
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range. . . . -40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θJC, the “case temp” location is taken at the package top center.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless
otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNIT
VOS
Offset Voltage Magnitude;
SOIC Package
-75
5
75
140
100
180
100
190
100
175
0.65
µV
µV
-140
-100
-180
-100
-190
-100
-175
-0.65
Offset Voltage Magnitude;
MSOP Package
5
µV
µV
Offset Voltage Magnitude;
TDFN Package
ISL28107
ISL28207
10
10
µV
µV
µV
µV
TCVOS
Offset Voltage Drift; SOIC
Package
0.1
0.1
µV/°C
Offset Voltage Drift; MSOP
Package
-0.85
0.85
µV/°C
Offset Voltage Drift; TDFN
Package
ISL28107
ISL28207
-0.9
-0.75
-300
0.1
0.1
15
0.9
0.75
300
µV/°C
µV/°C
pA
IB
TA = -40°C to +85°C
TA = -40°C to +125°C
Input Bias Current
-600
600
pA
FN6631.3
September 9, 2010
6
ISL28107, ISL28207, ISL28407
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
TA = -40°C to +85°C
(Note 8)
TYP
0.19
0.26
15
(Note 8) UNIT
TCIB
Input Bias Current Drift
-0.9
-3.5
-300
-600
-0.9
-3.5
-13
0.9
3.5
300
600
0.9
3.5
13
pA/°C
pA/°C
pA
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
Guaranteed by CMRR test
IOS
Input Offset Current
Input Offset Current Drift
Input Voltage Range
pA
TCIOS
0.19
pA/°C
pA/°C
V
0.26
VCM
CMRR
Common-Mode Rejection
Ratio
V
CM = -13V to +13V
115
145
dB
PSRR
AVOL
VOH
Power Supply Rejection Ratio VS = ±2.25V to ±20V
115
3,000
13.5
13.2
13.3
13.1
145
40,000
13.7
dB
V/mV
V
Open-Loop Gain
VO = -13V to +13V, RL = 10kΩ to ground
Output Voltage High
RL = 10kΩ to ground
RL = 2kΩ to ground
RL = 10kΩ to ground
RL = 2kΩ to ground
RL = Open
V
13.55
-13.7
-13.55
0.21
V
V
VOL
Output Voltage Low
-13.5
-13.2
-13.3
-13.1
0.29
V
V
V
V
IS
Supply Current/Amplifier
mA
mA
mA
V
0.35
ISC
Output Short-Circuit Current (Note 9)
Supply Voltage Range Guaranteed by PSRR
±40
VSUPPLY
±2.25
±20
AC SPECIFICATIONS
GBW
enp-p
en
Gain Bandwidth Product
1
340
14
MHz
nVP-P
Voltage Noise
0.1Hz to 10Hz, VS = ±19V
f = 10Hz, VS = ±19V
f = 100Hz, VS = ±19V
f = 1kHz, VS = ±19V
f = 10kHz, VS = ±19V
f = 10kHz, VS = ±19V
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Current Noise Density
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
%
en
13
en
13
en
13
in
53
THD + N
Total Harmonic Distortion + 1kHz, G = 1, VO = 3.5VRMS
,
0.0035
Noise RL = 2kΩ
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 10kΩ, VO = 10VP-P
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
±0.32
355
V/µs
ns
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
RL = 2kΩ to VCM
Fall Time
AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2k
Ω
365
ns
90% to 10% of VOUT
to VCM
FN6631.3
September 9, 2010
7
ISL28107, ISL28207, ISL28407
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits
apply over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNIT
ts
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1 VOUT = 10VP-P, Rg = Rf =10k,
29
µs
µs
µs
RL = 2kΩ to VCM
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, Rg = Rf =10k,
31.2
6
RL = 2kΩ to VCM
tOL
Output Overload Recovery
Time
AV = 100, VIN = 0.2V, RL = 2kΩ to VCM
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 8)
TYP
(Note 8) UNIT
VOS
Offset Voltage Magnitude;
SOIC Package
-75
5
75
140
100
180
100
190
100
175
0.65
µV
µV
-140
-100
-180
-100
-190
-100
-175
-0.65
Offset Voltage Magnitude;
MSOP Package
5
µV
µV
Offset Voltage Magnitude;
TDFN Package
ISL28107
ISL28207
10
10
µV
µV
µV
µV
TCVOS
Offset Voltage Drift; SOIC
Package
0.1
0.1
µV/°C
Offset Voltage Drift; MSOP
Package
-0.85
0.85
µV/°C
Offset Voltage Drift; TDFN
Package
ISL28107
ISL28207
-0.9
-0.75
-300
-600
-0.9
0.1
0.1
15
0.9
0.75
300
600
0.9
µV/°C
µV/°C
pA
IB
Input Bias Current
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
TA = -40°C to +85°C
TA = -40°C to +125°C
pA
TCIB
IOS
0.19
0.26
15
pA/°C
pA/°C
pA
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
-3.5
-300
-600
-0.9
3.5
300
600
0.9
pA
TCIOS
0.19
pA/°C
pA/°C
V
-3.5
-3
0.26
3.5
3
VCM
Common Mode Input Voltage Guaranteed by CMRR test
Range
CMRR
Common-Mode Rejection
Ratio
VCM = -3V to +3V
115
145
dB
PSRR
AVOL
Power Supply Rejection Ratio VS = ±2.25V to ±5V
115
145
dB
Open-Loop Gain
VO = -3V to +3V, RL = 10kΩ to ground
3,000
40,000
V/mV
FN6631.3
September 9, 2010
8
ISL28107, ISL28207, ISL28407
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
RL = 10kΩ to ground
(Note 8)
TYP
(Note 8) UNIT
VOH
Output Voltage High
3.5
3.2
3.3
3.1
3.7
V
V
V
V
RL = 2kΩ to ground
RL = 10kΩ to ground
RL = 2kΩ to ground
RL = Open
3.55
-3.7
VOL
Output Voltage Low
-3.5
-3.2
-3.3
V
V
-3.55
0.21
± 40
V
-3.1
0.29
0.35
V
IS
Supply Current/Amplifier
mA
mA
mA
ISC
Output Short-Circuit Current (Note 9)
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
1
MHz
%
THD + N
Total Harmonic Distortion +
Noise
1kHz, G = 1, VO = 2.5VRMS, RL = 2kΩ
0.0053
TRANSIENT RESPONSE
SR
Slew Rate
AV = 10, RL = 2kΩ
0.32
355
V/µs
ns
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
R
L = 2kΩ to VCM
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
370
12.4
22
ns
µs
µs
R
L = 2kΩ to VCM
ts
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, Rf = Rg = 2kΩ,
R
L = 2kΩ to VCM
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, Rf = Rg = 2kΩ,
R
L = 2kΩ to VCM
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Output Short Circuit Current is the minimum current (source or sink) when the output is driven into the supply rails with
RL = 0Ω to ground.
FN6631.3
September 9, 2010
9
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified.
30
20
30
20
V = ±5V
S
V
= ±15V
S
10
10
0
0
-10
-20
-30
-10
-20
-30
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 2. INPUT OFFSET VOLTAGE vs
TEMPERATURE, VS = ±5V
FIGURE 1. INPUT OFFSET VOLTAGE vs
TEMPERATURE, VS = ±15V
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
V
= ±15V
V
= ±5V
S
S
-100 -80 -60 -40 -20
V
0
(µV)
20
40
60
80 100
-100 -80 -60 -40 -20
0
20
(µV)
40
60
80 100
V
OS
OS
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION,
VS = ±15V
FIGURE 4. INPUT OFFSET VOLTAGE DISTRIBUTION,
VS = ±5V
16
16
V
= ±15V
V = ±5V
S
S
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
-0.45
-0.30 -0.15
0
0.15
0.30
0.45
-0.45
-0.30
-0.15
0
0.15
0.30
0.45
TCV (µV/°C)
TCV (µV/°C)
OS
OS
FIGURE 5. TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±15V
FIGURE 6. TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±5V
FN6631.3
September 9, 2010
10
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
200
100
0
200
100
0
V
= ±15V
V = ± 5V
S
S
-100
-200
-100
-200
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 8. POSITIVE BIAS CURRENT vs
TEMPERATURE, VS = ±5V
FIGURE 7. POSITIVE BIAS CURRENT vs
TEMPERATURE, VS = ±15V
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
= ±5V
V
= ±15V
S
S
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
0.6
1.0
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
0.6
1.0
TC (pA/°C)
TC (pA/°C)
Ib+
Ib+
FIGURE 9. TCIb+ vs NUMBER OF AMPLIFIERS,
VS = ±15V
FIGURE 10. TCIb+ vs NUMBER OF AMPLIFIERS,
VS = ±5V
200
200
V
= ± 15V
Vs = ± 5V
S
100
0
100
0
-100
-200
-100
-200
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. NEGATIVE BIAS CURRENT vs
TEMPERATURE, VS = ±15V
FIGURE 12. NEGATIVE BIAS CURRENT vs
TEMPERATURE, VS = ±5V
FN6631.3
September 9, 2010
11
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= ±15V
V
= ±5V
S
S
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
0.6
1.0
-1.8
-1.4
-1.0
-0.6
-0.2
0.2
0.6
1.0
TC (pA/°C)
TC (pA/°C)
Ib-
Ib-
FIGURE 13. TCIb- vs NUMBER OF AMPLIFIERS,
VS = ±5V
FIGURE 14. TCIb- vs NUMBER OF AMPLIFIERS,
VS = ±15V
200
200
V
= ±15V
V = ±5V
S
S
150
100
50
150
100
50
0
0
-50
-50
-100
-150
-200
-100
-150
-200
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 16. OFFSET CURRENT vs TEMPERATURE,
VS = ±5V
FIGURE 15. OFFSET CURRENT vs TEMPERATURE,
VS = ±15V
50
50
V
= ±5V
S
V
= ±15V
S
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
-0.7 -0.5 -0.3 -0.1
0.1
0.3
0.5
0.7
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
TCI (pA/°C)
TCI (pA/°C)
OS
OS
FIGURE 17. TCIOS- vs NUMBER OF AMPLIFIERS,
VS = ±15V
FIGURE 18. TCIOS- vs NUMBER OF AMPLIFIERS,
VS = ±5V
FN6631.3
September 9, 2010
12
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
180
160
140
120
180
160
140
120
100
V
= ±13V
V = ± 2.25V TO ± 20V
S
cm
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 20. PSRR vs TEMPERATURE
FIGURE 19. CMRR vs TEMPERATURE
63000
53000
43000
33000
23000
13000
3000
14.4
14.2
14.0
13.8
13.6
13.4
13.2
Vs = ±15V
V
= ±13V
O
R
= 10kΩ
L
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. AVOL vs TEMPERATURE
FIGURE 22. VOH vs TEMPERATURE, VS = ±15V,
RL = 10kΩ
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
14.4
V
R
= ±15V
= 10kΩ
V
R
= ±15V
S
S
= 2kΩ
L
L
14.2
14.0
13.8
13.6
13.4
13.2
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. VOL vs TEMPERATURE, VS = ±15V,
FIGURE 24. VOH vs TEMPERATURE, VS = ±15V,
RL = 10kΩ
RL = 2kΩ
FN6631.3
September 9, 2010
13
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
4.4
4.2
4.0
3.8
3.6
3.4
3.2
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
V
R
= ±15V
= 2kΩ
V
R
= ±5V
= 10kΩ
S
S
L
L
-50
0
50
100
150
-50
0
50
100
150
150
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 26. VOH vs TEMPERATURE, VS = ±5V,
FIGURE 25. VOL vs TEMPERATURE, VS = ±15V,
RL = 10kΩ
RL = 2kΩ
-3.2
0.40
V
R
= ±5V
S
= 10kΩ
L
-3.4
-3.6
-3.8
-4.0
-4.2
-4.4
0.35
±15V
0.30
±2.25V
0.25
0.20
0.15
0.10
-50
0
50
100
150
-50
0
50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. VOL vs TEMPERATURE, VS = ±5V,
FIGURE 28. SUPPLY CURRENT vs TEMPERATURE
RL = 10kΩ
60
60
I
@ ±15V
I
@ ±15V
SC+
SC-
55
50
45
40
35
30
25
20
55
50
45
40
35
30
25
20
-50
0
50
100
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 29. POSITIVE SHORT CIRCUIT CURRENT vs
TEMPERATURE
FIGURE 30. NEGATIVE SHORT CIRCUIT CURRENT vs
TEMPERATURE
FN6631.3
September 9, 2010
14
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
200
150
100
50
1000
100
10
V
= ±19V
= 1
+
A
V
0
-50
-100
-150
-200
V
R
R
= ±19V
+
L
g
C
= INF,
= 4pF
L
= 10, R = 100k
= 10,000
f
A
V
0
1
2
3
4
5
6
7
8
9
10
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
TIME (s)
FIGURE 31. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
FIGURE 32. INPUT NOISE VOLTAGE SPECTRAL
DENSITY
1
100
80
PSRR- V = ±5V, V = ±15V
S
S
60
40
20
0
0.1
R
C
= INF
= 4pF
= +1
L
L
V
= ±19V
= 1
+
A
V
A
V
V
PSRR+ V = ±5V, V = ±15V
S
S
= 1V
SOURCE
P-P
0.01
0.1
-20
10
1
10
100
1k
10k
100k
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 33. INPUT NOISE CURRENT SPECTRAL
DENSITY
FIGURE 34. PSRR vs FREQUENCY, VS = ±5V, ±15V
160
60
40
R
C
= INF
= 4pF
= +1
L
L
140
120
100
80
A
V
V
+125°C
= 1V
CM
P-P
20
0
+25°C
60
-20
-40°C
40
-40
20
V
= ±2.25V, ±5V, ±15V
S
0
0.1
-60
-15
-10
-5
0
5
10
15
1
10
100
1k
10k 100k 1M 10M 100M
INPUT COMMON MODE VOLTAGE
FREQUENCY (Hz)
FIGURE 35. CMRR vs FREQUENCY, VS = ±2.25, ±5V,
±15V
FIGURE 36. INPUT OFFSET VOLTAGE vs INPUT
COMMON MODE VOLTAGE, VS = ±15V
FN6631.3
September 9, 2010
15
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
200
180
160
140
120
100
80
200
180
160
140
120
100
80
PHASE
PHASE
60
60
40
40
20
0
20
0
GAIN
GAIN
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
R
C
= 10k
R
C
= 10k
L
L
L
L
= 10pF
= 100pF
SIMULATION
SIMULATION
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. OPEN-LOOP GAIN, PHASE vs
FIGURE 38. OPEN-LOOP GAIN, PHASE vs
FREQUENCY, RL = 10kΩ, CL = 10pF
FREQUENCY, RL = 10kΩ, CL = 100pF
8
6
70
R
= 100, R = 100k
f
A
= 1000
= 100
g
V
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
R = R = 10k
4
2
f
g
R = R = 100k
f
g
A
V
= ±20V
= 4pF
= 10k
V
+
L
C
0
R
R = R = 1k
L
f
g
V
= 100mV
OUT
P-P
A
= 10
-2
V
-4
V
R
= ±5V
= 10k
R
= 10k, R = 100k
f
R = R = 100
+
g
f
g
L
L
-6
A
= 1
V
C
= 4pF
= +2
-8
A
V
R
= OPEN, R = 0
g f
-10
-20
-10
V
= 10mV
P-P
OUT
-12
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 40. FREQUENCY RESPONSE vs FEEDBACK
RESISTANCE Rf/Rg
FIGURE 39. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
1
0
1
0
-1
-1
R
= 100k
L
-2
-3
-4
-5
-6
-7
-8
-9
-2
-3
-4
-5
-6
-7
-8
-9
R = 100k
L
R
= 10k
= 1k
L
L
R
= 10k
L
R
R
= 1k
L
R
= 499
L
R
= 499
L
V
= ±5V
= 4pF
= +1
V
= ±20V
= 4pF
= +1
+
+
C
C
L
L
A
A
V
V
V
= 10mV
V
= 100mV
OUT P-P
OUT
P-P
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 41. GAIN vs FREQUENCY vs RL
FIGURE 42. GAIN vs FREQUENCY vs RL
FN6631.3
September 9, 2010
16
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
8
6
1
0
C
C
= 334pF
= 224pF
L
-1
-2
-3
-4
-5
-6
-7
-8
4
L
C
= 104pF
L
2
0
V
V
= 10mV
= 50mV
OUT
P-P
OUT
OUT
P-P
-2
-4
-6
-8
C
= 51pF
V
= ±5V
= 4pF
= +1
L
S
V
= 100mV
= 200mV
P-P
V
R
= ±15V
= 10k
= +1
S
C
L
V
V
L
OUT
OUT
P-P
C
= 4pF
L
A
V
A
V
= 500mV
P-P
R
= INF
V
= 100mV
P-P
L
OUT
V
= 1V
P-P
OUT
-9
-
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 44. GAIN vs FREQUENCY vs OUTPUT
VOLTAGE
FIGURE 43. GAIN vs FREQUENCY vs CL
2
0
140
120
100
80
-2
-4
-6
V
= ±20V
= ±5V
-8
S
60
V
R
C
A
= 10k
= 4pF
= +1
-10
-12
-14
-16
S
L
C
R
A
= 4pF
= 10k
= +1
L
L
40
20
0
V
= ±5V
S
L
V
= ±15V
= ±2.25V
S
V
V
V
= ±15V
S
V
V
= 100mV
S
V
= 1V
P-P
OUT
P-P
OUT
10
100
1k
10k
100k
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
FIGURE 45. GAIN vs FREQUENCY vs SUPPLY
VOLTAGE
FIGURE 46. CROSSTALK vs FREQUENCY, VS = ±5V,
±15V
2.5
2.0
1.5
6
4
V
C
A
= ±15V
= 4pF
= 11
+
L
VS = ±5V, ±15V, RL = 10k
1.0
V
2
0
R = 10k, R = 1k
V
f
g
0.5
= 10V
OUT
P-P
VS = ±5V, ±15V, RL = 2k
0
-0.5
-1.0
RL = 10k
RL = 2k
-2
-4
-6
C
A
= 4pF
= 1
= 4V
L
-1.5
-2.0
-2.5
V
V
OUT
P-P
0
50
100
150
200
TIME (µs)
250
300
350
400
0
5
10
15
20
25
30
35
TIME (µs)
FIGURE 47. LARGE SIGNAL 10V STEP RESPONSE,
VS = ±15V
FIGURE 48. LARGE SIGNAL TRANSIENT RESPONSE vs
RL VS = ±5V, ±15V
FN6631.3
September 9, 2010
17
ISL28107, ISL28207, ISL28407
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, TA = +25°C unless otherwise
specified. (Continued)
0.26
0.22
0.18
0.14
0.10
0.06
0.02
-0.02
-0.06
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
15
13
11
9
V
R
C
= ±15V
= 10k
= 4pF
= 100
S
L
L
A
V
VS = ±5V, ±15V, ±20V
R = 10k, R = 100
f
g
V
= 200mV
IN
P-P
7
5
R
C
A
= 2k, 10k
= 4pF
= 1
3
L
L
INPUT
1
V
OUTPUT
V
= 100mV
OUT
P-P
-1
0
5
10
15
20
25
30
35
40
0
20 40 60 80 100 120 140 160 180 200
TIME (µs)
TIME (µs)
FIGURE 49. SMALL SIGNAL TRANSIENT RESPONSE
VS = ±5V, ±15V, ±20V
FIGURE 50. POSITIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±15V
0.06
0.02
1
50
OUTPUT
V
= ±15V
= 10k
= 1
S
45
40
35
30
25
20
15
10
5
-1
R
A
L
V
INPUT
-0.02
-0.06
-0.10
-0.14
-0.18
-0.22
-0.26
-3
V
= 100mV
OUT
P-P
-5
-7
V
= ±15V
= 10k
= 4pF
= 100
S
L
-9
R
C
L
-11
-13
-15
A
V
R = 10k, R = 100
f
g
V
= 200mV
IN
P-P
0
0
20 40 60 80 100 120 140 160 180 200
TIME (µs)
1
10
100
1,000
10,000
CAPACITANCE (pF)
FIGURE 51. NEGATIVE OUTPUT OVERLOAD
RESPONSE TIME, VS = ±15V
FIGURE 52. % OVERSHOOT vs LOAD CAPACITANCE,
VS = ±15V
FN6631.3
September 9, 2010
18
ISL28107, ISL28207, ISL28407
Output Current Limiting
Applications Information
The output current is internally limited to approximately
±40mA at +25°C and can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op-amp. Continuous operation under these
conditions may degrade long term reliability.
Functional Description
The ISL28107, ISL28207 and ISL28407 are single, dual
and quad, very low 1/f noise (14nV/√Hz @ 10Hz)
precision op-amps. These amplifiers feature very high
open loop gain (50kV/mV) for excellent CMRR (145dB),
and gain accuracy. Both devices are fabricated in a new
precision 40V complementary bipolar DI process.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28107, ISL28207
and ISL28407 are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
The super-beta NPN input stage with bias current
cancellation provides bipolar-like levels of AC
performance with the low input bias currents
approaching JFET levels. The temperature stabilization
provided by bias current cancellation removes the high
input bias current temperature coefficient commonly
found in JFET amplifiers. Figures 7 and 8 show the input
bias current variation over temperature.
Using Only One Channel
The ISL28207 is a dual op-amp. If the application only
requires one channel, the user must configure the
unused channel to prevent it from oscillating. The unused
channel will oscillate if the input and output pins are
floating. This will result in higher than expected supply
currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is
to short the output to the inverting input and ground the
positive input (as shown in Figure 53).
The input offset voltage (VOS) has an very low, worst
case value of 75µV max at +25°C and a maximum TC of
0.65µV/°C. Figure 36 shows VOS as a function of supply
voltage and temperature with the common mode voltage
at 0V for split supply operation.
The complimentary bipolar output stage maintains
stability driving large capacitive loads (to 10nF) without
external compensation. The small signal overshoot vs.
load capacitance is shown in Figure 52.
-
+
Operating Voltage Range
The devices are designed to operate over the 4.5V
(±2.25V) to 40V (±20V) range and are fully
FIGURE 53. PREVENTING OSCILLATIONS IN
UNUSED CHANNELS
characterized at 10V (±5V) and 30V (±15V). Both DC
and AC performance remain virtually unchanged over the
complete 4.5V to 40V operating voltage range.
Parameter variation with operating voltage is shown in
the “Typical Performance Curves” beginning on page 10.
The input common mode voltage range sensitivity to
temperature is shown in Figure 36 (±15V).
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
Input ESD Diode Protection
The input terminals (IN+ and IN-) each have internal
ESD protection diodes to the positive and negative
supply rails, a series connected 500Ω current limiting
resistor followed by an anti-parallel diode pair across
the input NPN transistors (Circuit 1 in “Pin Descriptions”
on page 4).
(EQ. 1)
T
= T
+ θ xPD
JMAX
MAX JA MAXTOTAL
where:
• PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX
)
The resistor-ESD diode configuration enables a wide
differential input voltage range equal to the lesser of the
Maximum Supply Voltage in the “Absolute Maximum
Ratings” on page 6 (42V) or, a maximum of 0.5V beyond
the V+ and V- supply voltage. The internal protection
resistors eliminate the need for external input current
limiting resistors in unity gain connections and other
circuit applications where large voltages or high slew
rate signals are present. Although the amplifier is fully
protected, high input slew rates that exceed the amplifier
slew rate (±0.32V/µs) may cause output distortion.
• PDMAX for each amplifier can be calculated using
Equation 2:
V
OUTMAX
R
L
----------------------------
PD
= V × I
+ (V - V ) ×
OUTMAX
(EQ. 2)
MAX
S
qMAX
S
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
FN6631.3
September 9, 2010
19
ISL28107, ISL28207, ISL28407
• IqMAX = Maximum quiescent supply current of 1
amplifier
License Statement
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
ISL28107, ISL28207, ISL28407 SPICE
Model
Figure 54 shows the SPICE model schematic and
Figure 55 shows the net list for the ISL28107, ISL28207
and ISL28407 SPICE model. The model is a simplified
version of the actual device and simulates important AC
and DC parameters. AC parameters incorporated into
the model are: 1/f and flatband noise, Slew Rate,
CMRR, Gain and Phase. The DC parameters are VOS,
IOS, total supply current and output voltage swing. The
model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 6. The AVOL is
adjusted for 155dB with the dominate pole at 0.01Hz.
The CMRR is set (145dB, fcm = 100Hz). The input stage
models the actual device to present an accurate AC
representation. The model is configured for ambient
temperature of +25°C.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
Figures 56 through 66 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Closed Loop Gain vs RL, Large Signal
Step Response, Open Loop Gain Phase and Simulated
CMRR vs Frequency.
FN6631.3
September 9, 2010
20
ISL28107, ISL28207, ISL28407
V++
V++
R3
R4
IEE1
4
5
96E-6
4.45k
4.45k
4
5
CASCODE
CASCODE
Q4
6
7
Q5
3
D1
DX
C4
2
2pF
SUPERB
SUPERB
Vin-
V5
V
-
Q1 Q2
IN
C5
2pF
R1
8
5E11
24
25
EOS
C6
1.2pF
1
IOS
Mirror
Vc
D12
DN
0.1V
R17
VCM
+
-
+
-
Vmid
Q3
15pA
9
+
-
IEE
R2
200E-6
600
In+
VOS
5E11
En
5E-6
V
+
IN
V--
VCM
Voltage Noise
Input Stage
V++
V++
D2
DX
D4
DX
G1
G3
G5
L1
13
10
4
1.59E-3
+
+
+
-
+
-
+
-
R5
1
R7
C2
R9
1
V1
V3
17
6.25pF
R11
1
1.86V
1.86V
2.55E10
-
-
5
11
Vc
Vg
Vmid
Vg
Vc
R12
1
R6
1
R8
R10
1
C3
Vmid
G4
G6
G2
2.55E10
6.25pF
18
+
-
+
-
-
+
-
+
-
+
V4
V2
L2
1.86V
1.86V
12
14
VCM
1.59E-3
D5
DX
D3
DX
V--
V--
VCM
ST Gain Stage
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
1
V++
D8
DX
D9
DX
G7
V+
V+
+
-
+
E2
R15
90
-
-
+
22
23
V5
DX
DX
D6
D7
20
21
ISY
V
OUT
VOUT
1.12V
0.21mA
Vg
V6
1.12V
R16
90
V-
G8
-
+
+
-
+
-
-
+
D10
DY
D11
DY
-
E3
V-
+
V--
G9
G10
Supply Isolation Stage
Output Stage
FIGURE 54. SPICE SCHEMATIC
FN6631.3
September 9, 2010
21
ISL28107, ISL28207, ISL28407
* source ISL28107_SPICEmodel
R_R7
R_R8
C_C2
C_C3
D_D4
D_D5
V_V3
V_V4
*
VG V++ 2.55e10
* Revision A, October 28th 2009 LaFontaine
* Model for Noise, supply currents, 145dB f=100Hz
CMRR, *155dB f=0.01Hz AOL
V-- VG 2.55e10
VG V++ 6.25e-10
V-- VG 6.25e-10
13 V++ DX
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
V-- 14 DX
13 VG 1.86
VG 14 1.86
*
*
*
*
*
|
|
|
|
|
-input
*Mid supply Ref
|
|
|
|
+Vsupply
R_R9
R_R10
I_ISY
E_E2
E_E3
*
VMID V++ 1
V-- VMID
|
|
|
-Vsupply
1
|
|
output
|
V+ V- DC 0.21E-3
V++ 0 V+ 0 1
.subckt ISL28107subckt Vin+ Vin-V+ V- VOUT
V-- 0 V- 0 1
* source ISL28127_SPICEMODEL_0_0
*
*Common Mode Gain Stage with Zero
*Voltage Noise
G_G5
G_G6
R_R11
R_R12
L_L1
L_L2
*
V++ VC VCM VMID 5.62e-8
V-- VC VCM VMID 5.62e-8
E_En
IN+ VIN+ 25 0 1
25 0 600
R_R17
D_D12
V_V7
VC 17
18 VC
1
1
24 25 DN
24 0 0.1
17 V++ 1.59e-3
18 V-- 1.59e-3
*
*Input Stage
I_IOS
C_C6
IN+ VIN- DC 15e-12
IN+ VIN- 1.2E-12
VCM VIN- 5e11
IN+ VCM 5e11
2 VIN- 1 SuperB
3 8 1 SuperB
*Output Stage with Correction Current Sources
G_G7
G_G8
G_G9
G_G10
D_D6
D_D7
D_D8
D_D9
D_D10
D_D11
V_V5
V_V6
R_R15
R_R16
*
VOUT V++ V++ VG 1.11e-2
V-- VOUT VG V-- 1.11e-2
22 V-- VOUT VG 1.11e-2
23 V-- VG VOUT 1.11e-2
VG 20 DX
R_R1
R_R2
Q_Q1
Q_Q2
Q_Q3
V-- 1 7 Mirror
4 6 2 Cascode
5 6 3 Cascode
4 V++ 4.45e3
21 VG DX
Q_Q4
V++ 22 DX
Q_Q5
V++ 23 DX
R_R3
V-- 22 DY
R_R4
5 V++ 4.45e3
V-- 23 DY
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
20 VOUT 1.12
VOUT 21 1.12
D_D1
I_IEE
I_IEE1
V_VOS
E_EOS
*
6 7 DX
VOUT V++ 9E1
1 V-- DC 200e-6
V++ 6 DC 96e-6
9 IN+ 5e-6
V-- VOUT 9E1
.model SuperB npn
8 9 VC VMID 1
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
*1st Gain Stage
G_G1
G_G2
R_R5
R_R6
D_D2
D_D3
V_V1
V_V2
*
V++ 11 4 5 101.6828e-3
.model Cascode npn
V-- 11 4 5 101.6828e-3
11 V++ 1
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
V-- 11
1
10 V++ DX
V-- 12 DX
10 11 1.86
11 12 1.86
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
*2nd Gain Stage
G_G3
G_G4
V++ VG 11 VMID 2.21e-3
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28107subckt
V-- VG 11 VMID 2.21e-3
FIGURE 55. SPICE NET LIST
FN6631.3
September 9, 2010
22
ISL28107, ISL28207, ISL28407
Characterization vs Simulation Results
1000
100
10
1000
V
= ±19V
= 1
+
A
V
100
10
100m
0.1
1
10
100
1k
10k
100k
1.0
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 57. SIMULATED INPUT NOISE VOLTAGE
FIGURE 56. CHARACTERIZED INPUT NOISE VOLTAGE
70
70
R
= 100, R = 100k
f
A
= 1000
= 100
= 10
A
= 1000
= 100
R
= 100, R = 100k
f
g
V
V
g
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
R
= 1k, R = 100k
f
g
60
40
20
0
A
A
V
V
= ±20V
= 4pF
= 10k
V
+
L
C
R
L
V
= 100mV
OUT
P-P
A
A
= 10
V
V
R
= 10k, R = 100k
g
f
R
= 10k, R = 100k
g
f
A
= 1
V
A
= 1
V
R
= OPEN, R = 0
f
R
= OPEN, R = 0
g f
g
-10
-20
-20
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 58. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
FIGURE 59. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
1
0
1
0
R
= 100k
L
-1
R
= 1k
L
-2
-4
-6
-2
-3
-4
-5
-6
-7
-8
-9
R = 100k
L
R
= 10k
L
R
= 10k
L
R
= 1k
L
R
= 499
V
= ±15V
= 4pF
= +1
L
R
= 499
+
L
V
= ±20V
= 4pF
= +1
+
C
L
C
L
A
V
A
V
V
= 100mV
OUT
P-P
-8
-9
V
= 100mV
P-P
OUT
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 60. CHARACTERIZED CLOSED LOOP GAIN vs
RL
FIGURE 61. SIMULATED CLOSED LOOP GAIN vs RL
FN6631.3
September 9, 2010
23
ISL28107, ISL28207, ISL28407
Characterization vs Simulation Results(Continued)
20
6
V
C
= ±15V
= 4pF
= 11
4
2
+
10
0
L
A
V
R = 10k, R = 1k
f
g
OUTPUT
V
= 10V
P-P
OUT
0
INPUT
R
= 10k
= 2k
L
-2
-4
-6
-10
-20
R
L
0
50
100
150
TIME (µs)
200
250
300
0
50
100
150
200
TIME (µs)
250
300
350
400
FIGURE 63. SIMULATED LARGE SIGNAL 10V STEP
RESPONSE
FIGURE 62. CHARACTERIZED LARGE SIGNAL 10V
STEP RESPONSE
200
200
180
160
140
150
PHASE
120
PHASE
100
80
60
40
20
0
-20
-40
-60
-80
100
50
GAIN
R
C
= 10k
L
L
R
C
= 10k
L
L
0
GAIN
= 10pF
= 10pF
SIMULATION
SIMULATION
-50
1m 10m
-100
1
100
10K
1M
100M
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 65. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 64. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
150
100
50
SIMULATION
0
1m
100m
10
1k
100k
10M
100M
FREQUENCY (Hz)
FIGURE 66. SIMULATED CMRR vs FREQUENCY
FN6631.3
September 9, 2010
24
ISL28107, ISL28207, ISL28407
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
Web to make sure you have the latest Rev.
DATE REVISION
CHANGE
9/7/10
FN6631.3 1. General changes:
a. Added in ISL28407 Quad devices for SOIC, TSSOP and QFN packages.
b. Added in TDFN packages for single ISL28107 and dual ISL28207 devices.
c. Added in new VOS and TCVOS limits for TDFN packages
2. Specific changes:
a. On page 1 – Added in ISL28407 to title and front page info. Corrected Input Bias Current in Features
from 60pA to 15pA (in order to match Spec Table)
b. On page 2 - Added in ISL28107FRTZ, ISL28207FRTZ, ISL28407FBZ, ISL28407FVZ, and ISL28407FRZ
packages to Ordering information. Added in –T7, T-13 & -T7A tape and reel extensions where applicable.
c. On page 2 -Corrected part marking for ISL28207FRTZ parts from 207Z to 8207
d. On page 3 – Added in TDFN, 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN to pin configurations.
e. On page 4 – Updated “Pin Descriptions” with newly added packages.
f. On page 6 – in “Thermal Information”, added in thermal packaging info & applicable notes for TDFN
packages.
g. On page 6 and page 8 Electrical Specifications Tables – Added two new line items for VOS spec. TDFN
package ISL28107 limits ±100uV 25C and ±190uV full temp. TDFN package ISL28207 limits ±100uV 25C
and ±175uV full temp.
h. On page 6 and page 8 Electrical Specifications Table – Added two new line items for TCVOS spec. TDFN
package ISL28107 limits ±0.9uV/C full temp. TDFN package ISL28207 limits ±0.75uV/C.
i. On page 28 to page 32 - Added in POD for L8.3x3A, M14.15, M14.173, and L16.4x4
3/9/10
FN6631.2 1. Added MSOP package to the ordering information and added applicable POD M8.118 to end of datasheet
2. Separated each part number with it's own specific -T7 and -T13 suffix. Removed “Add
“-T7” or “-T13” suffix for Tape and Reel.” from Note 1.
3. Added MSOP to the Pin Configuration and Pin Descriptions
4. Updated ±15 and ±5V Electrical Specification table with the following edits:
A) Separated VOS specs for SOIC and MSOP packages. Added new VOS specs for MSOP Grade
package.
B) Separated TCVOS specs for SOIC and MSOP packages. Added new TCVOS specs for MSOP
package.
5. Added Theta JA and JC for the 8 Ld MSOP package. Added Theta JC values for both SOIC package
options. Changed Theta JA for 8 Ld SOIC (ISL28207) from 115 to 105.
2/22/10
1. Added “Related Literature*(see page 26)” on page 1.
2. Added Evaluation Boards to “Ordering Information” on page 2.
3. “Electrical Specifications” Tables, page 6 to page 9. Unbolded MIN/MAX specs with “TA = -40°C to
+85°C” conditions (since only MIN/MAX specs with “TA = -40°C to +125°C” conditions should be bolded,
per note in common conditions)
4. Corrected Note reference in ISC parameter on page 7 and page 9 from Note 3 to Note 9.
11/10/09 FN6631.1 1. Updated VOS, IB, and IOS electrical specifications.
2. Added Typical performance curves, Figures 1 through 30.
3. Output Short Circuit Current test condition has been clarified with Note 9.
4. Updated POD.
5. Added Spice Model, associated text and Figures 56 through 66.
6. Deleted old Figures 6, 7, 8, 10, 11 and 12.
7. Added Licence Statement on page 16 and referenced in spice model.
6/5/09
FN6631.0 Initial Release.
FN6631.3
September 9, 2010
25
ISL28107, ISL28207, ISL28407
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28107, ISL28207 and ISL28407.
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6631.3
September 9, 2010
26
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6631.3
September 9, 2010
27
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.036
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN6631.3
September 9, 2010
28
ISL28107, ISL28207, ISL28407
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN6631.3
September 9, 2010
29
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
0.10 C A-B 2X
8.65
A
3
6
DETAIL"A"
0.22±0.03
D
14
8
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
(0.35) x 45°
4° ± 4°
5
0.31-0.51
0.25M C A-B D
B
3
6
TOP VIEW
0.10 C
H
1.75 MAX
1.25 MIN
0.25
GAUGE PLANE
SEATING PLANE
C
0.10-0.25
1.27
0.10 C
SIDE VIEW
DETAIL "A"
(1.27)
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
(1.50)
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
FN6631.3
September 9, 2010
30
ISL28107, ISL28207, ISL28407
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN6631.3
September 9, 2010
31
ISL28107, ISL28207, ISL28407
Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4X 1.95
0.65
12X
4.00
A
6
B
13
16
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
12
2 . 10 ± 0 . 15
9
4
0.15
(4X)
5
8
0.10 M C A B
TOP VIEW
+0.15
-0.10
16X 0 . 60
4
0.28 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
1.00 MAX
BASE PLANE
( 3 . 6 TYP )
SEATING PLANE
0.08
C
SIDE VIEW
(
2 . 10 )
( 12X 0 . 65 )
5
( 16X 0 . 28 )
( 16 X 0 . 8 )
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6631.3
September 9, 2010
32
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