ISL6721AAVZ-T_技术文档

DATASHEET

ISL6721A

FN6797

Rev.1.00

Jul 24, 2018

Flexible Single-Ended Current Mode PWM Controller

The ISL6721A is a low power, single-ended Pulse-Width

Modulating (PWM) current mode controller designed for

a wide range of DC/DC conversion applications

including Boost, Flyback, and isolated output

configurations. Peak current mode control effectively

handles power transients and provides inherent

overcurrent protection. Other features include a low

power mode in which the supply current drops to less

than 200µA during overvoltage and overcurrent

shutdown faults. The ISL6721A differs from the

ISL6721 in that the UVLO and UV thresholds have been

modified.

Features

• 1A MOSFET gate driver

• 100µA startup current

• Fast transient response with Peak Current Mode

control

• Adjustable switching frequency up to 1MHz

• Bidirectional synchronization

• Low Power Disable mode

• Delayed restart from OV and OC shutdown faults

• Adjustable slope compensation

• Adjustable soft-start

This advanced BiCMOS design features low operating

current, adjustable operating frequency up to 1MHz,

adjustable soft-start, and a bidirectional SYNC signal

that allows the oscillator to be locked to an external clock

for noise sensitive applications.

• Adjustable overcurrent shutdown threshold

• Adjustable UV and OV monitors

• Leading edge blanking

Related Literature

For a full list of related documents, visit our website

• Integrated thermal shutdown

• ISL6721A product page

• 1% tolerance voltage reference

• Pb-Free (RoHS compliant)

Applications

• Telecom and datacom power

• Wireless base station power

• File server power

• Industrial power systems

• Isolated buck and flyback regulators

• Boost regulators

FN6797 Rev.1.00

Jul 24, 2018

Page 1 of 36

ISL6721A

Contents

1.

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1

1.2

1.3

1.4

1.5

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

2.3

2.4

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.

4.

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Implementing Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Soft-Start Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Overvoltage and Undervoltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Overcurrent Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Fault Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Ground Plane Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.

Reference Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

Circuit Element Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Design Criteria. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Selecting Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Output Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Control Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Regulation Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Component List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FN6797 Rev.1.00

Jul 24, 2018

Page 2 of 36

ISL6721A

6.

7.

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FN6797 Rev.1.00

Jul 24, 2018

Page 3 of 36

ISL6721A

1. Overview

1.1

Typical Applications

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FN6797 Rev.1.00

Jul 24, 2018

Page 4 of 36

ISL6721A

1. Overview

CR1

R12

L1

+VOUT

VIN+

+

C2

C3

C12

RETURN

Q1

R8

R1

R2

R3

R4

C11

C1

VIN+

R10

C4

U1

C10

GATE

VC

PGND

VCC

ISENSE

SYNC

SLOPE VREF

UV

OV

LGND

SS

RTCT COMP

R9

ISET

VFB

R5

R11

C8

C5

C6

C7

R6

C9

R7

VIN-

Figure 2. Typical Boost Converter Application Schematic

FN6797 Rev.1.00

Jul 24, 2018

Page 5 of 36

ISL6721A

1. Overview

1.2

Block Diagram

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FN6797 Rev.1.00

Jul 24, 2018

Page 6 of 36

ISL6721A

1. Overview

1.3

Ordering Information

Part Number

(Notes 2, 3)

Tape and Reel

(Units) (Note 1)

Package

(RoHS Compliant)

Part Marking

21AZ

Temp Range (°C)

-40 to +105

Pkg. Dwg. #

L16.3x3B

ISL6721AARZ

ISL6721AARZ-T

ISL6721AAVZ

ISL6721AAVZ-T

Notes:

-

6k

-

16 Ld QFN

21AZ

-40 to +105

16 Ld QFN

L16.3x3B

M16.173

6721A AVZ

-40 to +105

16 Ld TSSOP

-40 to +105

2.5k

1. Refer to TB347 for details about reel specifications.

2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), refer to the ISL6721A device information page. For more information about MSL, refer to

TB363.

Table 1. Key Differences Between Family of Parts

Part Number

UVLO thresholds (start/stop) (V)

UV threshold (V)

ISL6721A

6.80/6.20

1.93

ISL6721

8.25/7.7

1.45

1.4

Pin Configurations

16 Ld TSSOP

Top View

16 Ld QFN

Top View

GATE

ISENSE

SYNC

SLOPE

UV

1

2

3

4

5

6

7

8

16 VC

15 PGND

14 VCC

13 VREF

12 LGND

11 SS

16

15

14

13

SYNC

SLOPE

UV

1

2

3

4

12 VCC

11 VREF

10 LGND

OV

10 COMP

9 FB

RTCT

ISET

OV

9

SS

5

6

7

8

FN6797 Rev.1.00

Jul 24, 2018

Page 7 of 36

ISL6721A

1. Overview

1.5

Pin Descriptions

Pin Number

(16 Ld TSSOP) (16 Ld QFN)

Pin Name

Description

1

2

15

GATE

Device output. This high current power driver is capable of driving the gate of a power

MOSFET with peak currents of 1.0A. This GATE output is actively held low when V_CC

is below the UVLO threshold.

The output high voltage is held to ~13.5V. Do not apply voltages exceeding this clamp

value to the GATE pin. The output stage provides very low impedance to overshoot

and undershoot.

16

ISENSE

Input to the current sense comparators. The IC has two current sensing comparators:

a PWM comparator for peak current mode control and an overcurrent protection

comparator. The overcurrent comparator threshold is adjustable through the ISET pin.

Exceeding the overcurrent threshold starts a delayed shutdown sequence. When an

overcurrent condition is detected, the soft-start charge current source is disabled and a

discharge current source is enabled. The soft-start capacitor begins discharging, and if

it discharges to less than 4.375V (sustained overcurrent threshold), a shutdown

condition occurs and the GATE output is forced low. Refer to “Overcurrent Operation”

on page 17 for more details. The GATE output remains low until the reset threshold is

attained. At this point, a soft-start cycle begins.

If the overcurrent condition ceases and an additional 50µs period elapses before the

shutdown threshold is reached, no shutdown occurs and the soft-start voltage is

allowed to recharge.

3

4

1

2

SYNC

This bidirectional synchronization signal coordinates the switching frequency of

multiple units. Units can be synchronized by connecting the SYNC signal of each unit

together or by using an external master clock signal. The oscillator timing capacitor,

C_T, is still required even if an external clock is used. The first unit to assert this signal

assumes control. The SYNC frequency can be either higher or lower than the free

running oscillator frequency.

SLOPE

Method by which the ISENSE ramp slope can be increased for improved noise

immunity or improved control loop stability for duty cycles greater than 50%. An

internal current source charges an external capacitor to GND during each switching

cycle. The resulting ramp is scaled and added to the ISENSE signal.

5

6

7

3

4

5

UV

OV

Undervoltage monitor input pin. This signal is compared to an internal 1.93V

reference to detect an undervoltage condition.

Overvoltage monitor input pin. This signal is compared to an internal 2.5V reference

to detect an overvoltage condition.

RTCT

Oscillator timing control pin. The operational frequency and maximum duty cycle are

set by connecting a resistor, R_T, between V_REFand this pin and a timing capacitor, C_T,

from this pin to LGND. The oscillator produces a sawtooth waveform with a

programmable frequency range of 100kHz to 1.0MHz. The charge time, t_C; the

discharge time, t_D; the switching frequency, f ; and the maximum duty cycle, Dmax,

sw

can be calculated from Equations 1, 2, 3, and 4:

(EQ. 1)

(EQ. 2)

(EQ. 3)

(EQ. 4)

t

 0.655  R  C

s

C

T

0.001  R – 3.6









T

-------------------------------------------

t

f

 –R  C  LN

s

D

T

0.001  R – 1.9

1

+ t

C

-----------------

D

=

Hz

sw

t

Dmax = t  f

C

SW

Use Figure 4 on page 14 as a guideline for selecting the capacitor and resistor values

required for a given frequency.

FN6797 Rev.1.00

Jul 24, 2018

Page 8 of 36

ISL6721A

1. Overview

Pin Number

(16 Ld TSSOP) (16 Ld QFN)

Pin Name

Description

8

9

6

7

8

ISET

Sets the pulse-by-pulse overcurrent threshold by applying a DC voltage between

0.35V and 1.2V to this input. When overcurrent inception occurs, the SS capacitor

begins to discharge and starts the overcurrent delayed shutdown cycle.

FB

Feedback voltage input connected to the inverting input of the error amplifier. The

non-inverting input of the error amplifier is internally tied to a reference voltage.

Current sense leading edge blanking is disabled when the FB input is less than 2.0V.

10

COMP

Error amplifier output and the PWM comparator input. The control loop frequency

compensation network is connected between the COMP and FB pins.

The ISL6721A features a built-in full cycle soft-start. Soft-start is implemented as a

clamp on the maximum COMP voltage.

11

9

SS

Connect the soft-start capacitor between this pin and LGND to control the duration of

soft-start. The value of the capacitor determines both the rate of increase of the duty

cycle during start-up and controls the overcurrent shutdown delay.

12

13

10

11

LGND

VREF

A small signal reference ground for all analog functions on this device.

The 5V reference voltage output. Bypass to LGND with a 0.01µF or larger capacitor to

filter this output as needed. Using capacitance less than this value may cause

unstable operation.

14

12

VCC

Power connection for the device. Although quiescent current, I_CC, is low, it is

dependent on the frequency of operation. To optimize noise immunity, bypass VCC to

LGND with a ceramic capacitor as close to the VCC and LGND pins as possible.

The total supply current (I_Cplus I_CC) will be higher, depending on the load applied to

GATE. Total current is the sum of the quiescent current and the average gate current.

Knowing the operating frequency, f_sw, and the MOSFET gate charge, Qg, the average

GATE output current can be calculated in Equation 5:

Igate = Qg  f

A

(EQ. 5)

SW

15

13

14

PGND

VC

Provides a dedicated ground for the output gate driver. Connect the LGND and PGND

pins externally using a short printed circuit board trace close to the IC. This is

imperative to prevent large, high frequency switching currents flowing through the

ground metallization inside the IC (decouple V_Cto PGND with a low ESR 0.1µF or

larger capacitor).

16

A separate collector supply to the output gate drive. Separating VC and PGND helps

decouple the IC’s analog circuitry from the high power gate drive noise (decouple VC

to PGND with a low ESR 0.1µF or larger capacitor).

N/A

Thermal Pad Thermal Pad The thermal pad located on the bottom of the QFN package is electrically isolated.

Renesas recommends connecting it to signal ground.

FN6797 Rev.1.00

Jul 24, 2018

Page 9 of 36

ISL6721A

2. Specifications

2.1

Absolute Maximum Ratings

Parameter

Minimum

GND - 0.3

Maximum

Unit

V

Supply Voltage, V_CC, V_C

GATE

+20.0

Gate Output Limit

Voltage

V

PGND to LGND

VREF

-0.3

+0.3

5.3V

VREF

1

V

A

GND - 0.3

Signal Pins

Peak GATE Current

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may

adversely impact product reliability and result in failures not covered by warranty.

2.2

Thermal Information

Thermal Resistance (Typical)



_JA(°C/W)

44



_JC(°C/W)

16 Ld QFN (Notes 4, 5)

16 Ld TSSOP (Notes 6, 7)

Notes:

4

105

33

4. _JAis measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”

features. See TB379.

5. For _JC, the “case temp” location is the center of the exposed metal pad on the package underside.

6. _JAis measured with the component mounted on a high-effective thermal conductivity test board in free air. Refer to TB379.

7. For _JC, the “case temp” location is taken at the package top center.

Parameter

Maximum Junction Temperature

Maximum Storage Temperature Range

Pb-Free Reflow Profile

Minimum

-55

Maximum

+150

Unit

°C

-65

+150

°C

Refer to TB493

2.3

Recommended Operating Conditions

Parameter

Minimum

Maximum

+105

Unit

°C

Temperature Range

-40

9

Supply Voltage Range (Typical, Note 8)

18

VDC

Note:

8. All voltages are measured with respect to GND.

FN6797 Rev.1.00

Jul 24, 2018

Page 10 of 36

ISL6721A

2. Specifications

2.4

Electrical Specifications

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and the Typical Application schematics

on page 4 and page 5. 9V < V_CC= V_C< 20V, RT = 11kΩ, CT = 330 pF. Typical values are at T_A= +25°C. Boldface limits apply over the

operating temperature range, -40°C to +105°C.

Min

Max

Parameter

Undervoltage Lockout

Test Conditions

(Note 9)

Typ

(Note 9)

Units

START Threshold

6.40

6.80

6.20

0.60

100

200

4.5

6.90

6.30

1.00

175

V

STOP Threshold

5.85

Hysteresis

0.50

V

Start-Up Current, I_CC

OC/OV Fault Operating Current, I_CC

Operating Current, I_CC

Operating Supply Current, I_C

Reference Voltage

Overall Accuracy

V_CC< START Threshold

-

µA

mA

300

(Note 11)

10.0

12.0

Includes 1nF GATE loading

8.0

Line, load, 0°C to +105°C

Line, load, -40°C to +105°C

4.95

4.90

-

5.00

5

5.05

-

V

Long Term Stability

T_A= +125°C, 1000 hours

(Note 10)

mV

Fault Voltage

4.50

4.65

75

4.65

4.80

165

-

4.75

4.95

250

-

V

VREF Good Voltage

Hysteresis

V

mV

mA

Operational Current

Current Limit

-10

-20

-

Current Sense

Input Impedance

Offset Voltage

Input Voltage Range

Blanking Time

Gain, A_CS

-

5

0.10

-

kΩ

V

0.08

0

0.11

1.5

V

(Note 10)

30

60

100

0.81

ns

V/V

V_SLOPE= 0V, V_FB= 2.3V,

0.77

0.79

V

A

_ISET= 0.35V, 1.5V

_CS= ISET/ISENSE

Error Amplifier

Open Loop Voltage Gain

Gain-Bandwidth Product

Reference Voltage Initial Accuracy

(Note 10)

60

-

90

15

-

dB

MHz

V

V_FB= COMP, T_A= +25°C

(Note 10)

2.465

2.515

2.565

Reference Voltage

COMP to PWM Gain, A_COMP

COMP to PWM Offset

FB Input Bias Current

COMP Sink Current

COMP Source Current

COMP VOH

V_FB= COMP

2.44

0.31

0.51

-2

2.515

0.33

0.75

0.1

2.590

0.35

0.88

2

V

V/V

V

COMP = 4V, T_A= +25°C

COMP = 4V (Note 10)

V_FB= 0V

µA

mA

V

COMP = 1.5V, V_FB= 2.7V

COMP = 1.5V, V_FB= 2.3V

V_FB= 2.3V

2

6

-

-0.25

4.25

0.4

-0.5

4.4

-

5.0

1.2

COMP VOL

V_FB= 2.7V

0.8

V

FN6797 Rev.1.00

Jul 24, 2018

Page 11 of 36

ISL6721A

2. Specifications

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and the Typical Application schematics

on page 4 and page 5. 9V < V_CC= V_C< 20V, RT = 11kΩ, CT = 330 pF. Typical values are at T_A= +25°C. Boldface limits apply over the

operating temperature range, -40°C to +105°C. (Continued)

Min

Max

Parameter

Test Conditions

(Note 9)

Typ

80

(Note 9)

Units

dB

PSRR

Frequency = 120Hz (Note 10)

SS = 2.5V, V_FB= 0V, ISET = 2V

60

-

SS Clamp, V_COMP

Oscillator

2.4

2.5

2.6

V

Frequency Accuracy

289

318

2

347

3

kHz

%

Frequency Variation with V_CC

T = +105°C (f_20V- f_9V)/f_9V

T = -40°C (f_20V-f_9V)/f_9V

(Note 10)

-

2

3

%

Temperature Stability

-

8

-

%

Maximum Duty Cycle

(Note 12)

68

75

81

-

%

Comparator High Threshold - Free Running

-

3.00

4.00

1.50

1.0

V

Comparator High Threshold - with External SYNC (Note 10)

Comparator Low Threshold

-

V

-

V

Discharge Current

0°C to +105°C

-40°C to +105°C

0.75

0.70

1.2

mA

Synchronization

Input High Threshold

Input Pulse Width

-

2.5

-

V

ns

25

Input Frequency Range

(Note 10)

0.65 x

Free

1.0

MHz

Running

Input Impedance

VOH

-

2.5

-

4.5

-

kΩ

V

R

_LOAD= 4.5k

VOL

R_LOAD= open

-

0.1

55

V

SYNC Advance

SYNC rising edge to GATE

falling edge,

-

25

ns

C_GATE= C_SYNC= 100pF

Output Pulse Width

C_SYNC= 100pF

50

-

ns

Soft-Start

Charging Current

SS = 2V

-40

4.26

30

-55

4.50

40

-70

4.74

55

µA

V

Charged Threshold Voltage

Initial Overcurrent Discharge Current

Sustained OC Threshold < SS

< Charged Threshold

µA

Overcurrent Shutdown Threshold Voltage

Charged Threshold minus,

T_A= +25°C

0.095

0.125

0.155

V

Fault Discharge Current

Reset Threshold Voltage

Slope Compensation

Charge Current

SS = 2V

0.25

1.0

-

mA

V

T_A= +25°C

0.22

0.27

0.31

SLOPE = 2V, 0°C to +105°C

-40°C to +105°C

-45

-41

-53

-

-65

µA

Slope Compensation Gain

Fraction of slope voltage added

to I_SENSE, T_A= +25°C

0.097

0.103

V/V

Fraction of slope voltage added

to I_SENSE

0.082

-

0.118

V/V

FN6797 Rev.1.00

Jul 24, 2018

Page 12 of 36

ISL6721A

2. Specifications

Recommended operating conditions unless otherwise noted. Refer to “Block Diagram” on page 6 and the Typical Application schematics

on page 4 and page 5. 9V < V_CC= V_C< 20V, RT = 11kΩ, CT = 330 pF. Typical values are at T_A= +25°C. Boldface limits apply over the

operating temperature range, -40°C to +105°C. (Continued)

Min

Max

Parameter

Test Conditions

V_RTCT= 4.5V

(Note 9)

Typ

(Note 9)

Units

Discharge Voltage

-

0.1

0.2

V

Gate Output

Gate Output Limit Voltage

V_C= 20V, C_GATE= 1nF,

_OUT= 0mA

11.0

13.5

1.5

16.0

2.2

V

I

Gate VOH

V_C- GATE, V_C= 10V,

_OUT= 150mA

-

I

Gate VOL

GATE - PGND, IOUT = 150mA

IOUT = 10mA

-

1.2

0.6

1.0

1.5

0.8

-

V

A

Peak Output Current

V_C= 20V, C_GATE= 1nF

(Note 10)

Output “Faulted” Leakage

Rise Time

V

_C= 20V, UV = 0V, GATE = 2V

1.2

2.6

60

-

mA

ns

V_C= 20V, C_GATE= 1nF

1V < GATE < 9V

-

100

Fall Time

V

_C= 20V, C_GATE= 1nF

-

15

-

40

ns

1V < GATE < 9V

Minimum ON time

ISET = 0.5V; V_FB= 0V;

VC = 11V ISENSE to GATE

w/10:1 Divider RTCT = 4.75V

through 1kΩ

110

(Note 10)

Overcurrent Protection

Minimum ISET Voltage

Maximum ISET Voltage

ISET Bias Current

-

0.35

-

V

1.2

-1.0

150

-

V_ISET= 1.00V

T_A= +25°C

1.0

445

µA

ms

Restart Delay

295

OV and UV Voltage Monitor

Overvoltage Threshold

Undervoltage Fault Threshold

Undervoltage Clear Threshold

Undervoltage Hysteresis Voltage

UV Bias Current

2.4

1.89

1.96

20

2.5

1.93

2.01

50

-

2.6

2.00

2.10

100

1.0

V

mV

µA

V_UV= 2.10 V

V_OV= 2.00 V

-1.0

OV Bias Current

-

1.0

Thermal Protection

Thermal Shutdown

(Note 10)

120

105

-

130

120

10

140

135

-

°C

Thermal Shutdown Clear

Hysteresis

Notes:

9. Parameters with MIN and/or MAX limits are 100% tested at 25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

10. This parameter, although guaranteed by characterization or correlation testing, is not 100% tested in production.

11. This is the V_CCcurrent consumed when the device is active but not switching. Does not include gate drive current.

12. This is the maximum duty cycle achievable using the specified values of RT and CT. Larger or smaller maximum duty cycles

may be obtained using other values for RT and CT. See Equations 1, 2, 3, and 4.

FN6797 Rev.1.00

Jul 24, 2018

Page 13 of 36

ISL6721A

3. Typical Performance Curves

1.002

1.000

1

1.000

1

0.998

0.995

0.993

0.991

-40

-10

20

50

80

110

-40

-10

20

50

80

110

Temperature (°C)

Figure 3. EA Reference Voltage vs Temperature

Figure 4. VREF Reference Voltage vs Temperature

3

1.002

0.996

0.989

0.983

0.976

0.970

10

100pF

100

220pF

330pF

470pF

680pF

1000pF

10

10 20 30 40 50 60 70 80 90 100

2000pF

-40

-10

20

50

80

110

RT (kΩ)

Temperature (°C)

Figure 5. Oscillator Frequency vs Temperature

Figure 6. Resistance for CT Capacitor Values Given

FN6797 Rev.1.00

Jul 24, 2018

Page 14 of 36

ISL6721A

4. Functional Description

4.1

Features

The ISL6721A current mode PWM is an ideal choice for low-cost Flyback and Forward topology applications

requiring enhanced control and supervisory capability. With adjustable overvoltage and undervoltage thresholds,

overcurrent threshold, and hiccup delay, a highly flexible design with minimal external components is possible.

Other features include peak current mode control, adjustable soft-start, slope compensation, adjustable oscillator

frequency, and a bidirectional synchronization clock input.

4.2

Oscillator

The ISL6721A has a sawtooth oscillator with a programmable frequency range to 1MHz, which can be

programmed with a resistor and capacitor on the RTCT pin. Refer to Figure 6 for the resistance and capacitance

required for a given frequency.

4.3

Implementing Synchronization

Synchronize the oscillator to an external clock applied at the SYNC pin or by connecting the SYNC pins of

multiple ICs together. If using an external master clock signal, it must be at least 65% of the free-running frequency

of the oscillator for proper synchronization. The external master clock signal should have a pulse width greater than

20ns. If no master clock is used, the first device to assert SYNC assumes control of the SYNC signal. An external

SYNC pulse is ignored if it occurs during the first 1/3 of the switching cycle.

During normal operation, the RTCT voltage charges from 1.5V to 3.0V and back during each cycle. Clock and

SYNC signals are generated when the 3.0V threshold is reached. If an external clock signal is detected during the

latter 2/3 of the charging cycle, the oscillator switches to external synchronization mode and relies on the external

SYNC signal to terminate the oscillator cycle. The generation of a SYNC signal is inhibited in this mode. If the

RTCT voltage exceeds 4.0V (no external SYNC signal terminates the cycle), the oscillator reverts to the internal

clock mode and a SYNC signal is generated.

4.4

Soft-Start Operation

The ISL6721A features soft-start using an external capacitor in conjunction with an internal current source.

Soft-start reduces voltage stresses and surge currents during start-up.

At start-up, the soft-start circuitry clamps the error amplifier output (COMP pin) to a value proportional to the

soft-start voltage. The error amplifier output rises as the soft-start capacitor voltage rises. This increases the output

pulse width from zero to the steady state operating duty cycle during the soft-start period. When the soft-start voltage

exceeds the error amplifier voltage, soft-start is complete. Soft-start forces a controlled output voltage rise. Soft-start

occurs during start-up and after recovery from a fault condition or overcurrent shutdown. The soft-start voltage is

clamped to 4.5V.

4.5

Gate Drive

The ISL6721A can source and sink 1A peak current. Separate collector supply (V ) and power ground (PGnd) pins

C

help isolate the IC’s analog circuitry from the high power gate drive noise. To limit the peak current through the IC,

place an external resistor between the IC totem-pole output (GATE pin) and the MOSFET gate. This small series

resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the

board and the FET’s input capacitance.

4.6

Slope Compensation

Use slope compensation to improve noise immunity in applications in which the maximum duty cycle is less than

50%, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined

empirically, but is generally about 10% of the full scale current feedback signal. Slope compensation is required to

prevent instability in applications in which the duty cycle is greater than 50%. Slope compensation is a technique in

FN6797 Rev.1.00

Jul 24, 2018

Page 15 of 36

ISL6721A

4. Functional Description

which the current feedback signal is modified by adding additional slope to it. The minimum amount of slope

compensation required corresponds to 1/2 the inductor downslope. However, adding excessive slope compensation

results in a control loop that behaves more as a voltage mode controller than as current mode controller (Figure 7).

Downslope

Current Sense Signal

Time

Figure 7. Slope Compensation

The minimum amount of capacitance to place at the SLOPE pin is calculated in Equation 6:

t

–6

ON

(EQ. 6)

----------------------

C

= 4.2410



F

SLOPE

V

SLOPE

where t is the On time and V

is the amount of voltage to be added as slope compensation to the current

ON

SLOPE

feedback signal. In general, the amount of slope compensation added is two to three times the minimum required.

Example:

Assume the inductor current signal presented at the ISENSE pin decreases 125mV during the Off period, and:

Switching Frequency, f = 250kHz

SW

Duty Cycle, D = 60%

t

= D/f = 0.6/250E3 = 2.4µs

SW

ON

= (1 - D)/f = 1.6µs

OFF

SW

Determine the downslope:

Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the amount of voltage that must be added to the current

sense signal by the end of the On time (Equation 7).

1

2

--

(EQ. 7)

V

=

 0.078  2.4 = 94mV

SLOPE

Therefore (Equation 8),

–6

2.410

-----------------------

 110pF

(EQ. 8)

C

= 4.2410



SLOPEMIN

0.094

An appropriate slope compensation capacitance for this example would be 1/2 to 1/3 the calculated value, or

between 68pF and 33pF.

4.7

Overvoltage and Undervoltage Monitor

The OV and UV signals are inputs to a window comparator that monitors the input voltage level to the converter. If

the voltage falls outside of the user designated operating range, a shutdown fault occurs. For OV faults, the supply

current, I , is reduced to 200µA for ~295ms, at which time recovery is attempted. If the fault is cleared, a

CC

soft-start cycle begins. If the fault is not cleared, another shutdown cycle occurs. A UV condition also results in a

shutdown fault, but the device does not enter Low Power mode and no restart delay occurs when the fault clears.

A resistor divider between V and LGND to each input determines the operational thresholds. The UV threshold

IN

has a fixed hysteresis of 75mV nominal.

FN6797 Rev.1.00

Jul 24, 2018

Page 16 of 36

ISL6721A

4. Functional Description

4.8

Overcurrent Operation

The overcurrent threshold level is set by the voltage applied at the ISET pin. Set the overcurrent level by using a

resistor divider network from VREF to LGND. Set the ISET threshold at a level that corresponds to the desired

peak output inductor current plus the additive effects of slope compensation.

Overcurrent delayed shutdown is enabled when the soft-start cycle is complete. If an overcurrent condition is

detected, the soft-start charging current source is disabled and the discharging current source is enabled. The

soft-start capacitor is discharged at a rate of 40µA. At the same time, a 50µs retriggerable one-shot timer is

activated and remains active for 50µs after the overcurrent condition stops. The soft-start discharge cycle cannot be

reset until the one-shot timer becomes inactive. If the soft-start capacitor discharges by more than 0.125V to

4.375V, the output is disabled and the soft-start capacitor is discharged. The output remains disabled and I drops

CC

to 200µA for approximately 295ms. A new soft-start cycle is then initiated. The OC protection shutdown and

restart behavior is often referred to as hiccup operation due to its repetitive start-up and shutdown characteristics.

If the overcurrent condition stops at least 50µs before the soft-start voltage reaches 4.375V, the soft-start charging

and discharging currents revert to normal operation and the soft-start voltage is allowed to recover.

Hiccup OC protection may be defeated by setting ISET to a voltage that exceeds the Error Amplifier current

control voltage, or about 1.5V.

4.9

Leading Edge Blanking

The leading edge blanking circuitry removes the initial 100ns of the current feedback signal input at ISENSE. The

blanking period begins when the GATE output leading edge exceeds 3.0V. Leading edge blanking prevents current

spikes from parasitic elements in the power supply from causing false trips of the PWM comparator and the

overcurrent comparator.

4.10 Fault Conditions

A fault condition occurs if VREF falls below 4.65V, the OV input exceeds 2.50V, the UV input falls below 1.93V,

or the junction temperature of the die exceeds ~+130°C. When a Fault is detected, the GATE output is disabled and

the soft-start capacitor is quickly discharged. A soft-start cycle begins when the Fault condition clears and the

soft-start voltage is below the reset threshold.

4.11 Ground Plane Requirements

Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A

unique section of the ground plane must be designated for high di/dt currents associated with the output stage.

Power ground (PGND) can be separated from the logic ground (LGND) and connected at a single point. Bypass V

C

directly to PGND with good high frequency capacitors. Connect the return connection for input power and the bulk

input capacitor to the PGND ground plane.

FN6797 Rev.1.00

Jul 24, 2018

Page 17 of 36

ISL6721A

5. Reference Design

The typical boost converter application schematic (Figure 2 on page 5) features the ISL6721A in a conventional dual

output 10W discontinuous mode Flyback DC/DC converter. The ISL6721EVAL1Z demonstration board implements

this design and is available for evaluation.

The input voltage range is from 36VDC to 75VDC, and the two outputs are 3.3V at 2.5A and 1.8V at 1.0A. Use the

weighted sum of the two outputs for cross regulation.

5.1

Circuit Element Descriptions

The converter design consists of the following functional blocks:

Input Storage and Filtering Capacitors: C , C , C

1

2

3

Isolation Transformer: T1

Primary voltage Clamp: C , R , C

R6 24 18

Start Bias Regulator: R , R , R , Q , V

R1

1

2

6

3

Operating Bias and Regulator: R , Q , D , C , C , D

2

25

2

1

5

R2

Main MOSFET Power Switch: Q

1

Current Sense Network: R , R , R , C

4

3

23

Feedback Network: R , R , R , R , R , R , R , R , R , C , C , U , U

3

13 15 16 17 18 19 20 26 27 13 14

2

Control Circuit: C , C , C , C , C , C , R , R , R , R , R , R , R , R , R

10 11 12 14 22

7

8

9

10 11 12

5

6

8

9

Output Rectification and Filtering: C , C , C , C , C , C , C , C

R4 R5 15 16 19 20 21 22

Secondary Snubber: R , C

21 17

5.2

Design Criteria

The following design requirements were selected:

Switching frequency, f : 200kHz

SW

V : 36V to 75V

IN

V

: 3.3V at 2.5A

: 1.8V at 1.0A

OUT(1)

OUT(2)

: 12V at 50mA

OUT(BIAS)

P

: 10W

OUT

Efficiency: 70%

Maximum duty cycle, D

: 0.45

MAX

5.3

Transformer Design

Flyback transformer design is an iterative process that requires a great deal of experience to achieve the desired

result. It is a process of many compromises, and even experienced designers will produce different designs when

presented with identical requirements. The iterative design process is not presented here for clarity.

The abbreviated design process is as follows:

• Select a core geometry suitable for the application. Constraints of height, footprint, mounting preference, and

operating environment will affect the choice.

• Select suitable core material(s).

• Select the maximum flux density desired for operation.

FN6797 Rev.1.00

Jul 24, 2018

Page 18 of 36

ISL6721A

5. Reference Design

• Select the core size. Core size is determined by the ability of the core structure to store the required energy, the

number of turns that have to be wound, and the wire gauge needed. Often, the window area (the space used for the

windings) and power loss determine the final core size. Flyback transformers’ ability to store energy is the critical

factor in determining the core size. The cross sectional area of the core and the length of the air gap in the

magnetic path determine the energy storage capability.

• Determine the maximum desired flux density. Depending on the frequency of operation, the core material

selected, and the operating environment, the allowed flux density must be determined. The allowed flux density is

often difficult to determine initially. Usually the highest flux density that produces an acceptable design is used,

but the winding geometry often dictates a larger core than is required based on flux density and energy storage

calculations.

• Determine the number of primary turns.

• Determine the turns ratio.

• Select the wire gauge for each winding.

• Determine winding order and insulation requirements.

• Verify the design.

Input Power:

P

/efficiency = 14.3W (use 15W)

OUT

Max ON time: t

= D

/f = 2.25µs

MAX SW

ON(MAX)

Average input current: I

= P /V

= 0.42A

AVG(IN)

IN IN(MIN)

Peak primary current (Equation 9):

2  I

AVGIN

(EQ. 9)

------------------------------------------

= 1.87

I

=

A

PPK

f

 t

SW ONMAX

Maximum primary inductance (Equation 10):

V

 t

INMIN ONMAX

---------------------------------------------------------

Lpmax =

= 43.3

H

(EQ. 10)

I

PPK

Select 40µH for the primary inductance.

The core structure must be able to deliver a certain amount of energy to the secondary on each switching cycle in

order to maintain the specified output power (Equation 11).

 V

+ Vd

OUT

-----------------------------------

w = P



joules

OUT

(EQ. 11)

f

 V

OUT

SW

where w is the amount of energy required to be transferred each cycle and Vd is the drop across the output

rectifier.

The capacity of a gapped ferrite core structure to store energy is dependent on the volume of the airgap and can be

expressed in Equation 12:

2    w

3

o

(EQ. 12)

-----------------------------

Vg = Aeff  lg =

m

2

B

2

where Aeff is the effective cross sectional area of the core in m , lg is the length of the airgap in meters, µ is the

o

-7

permeability of free space (410 ), and B is the change in flux density in Tesla.

A core structure with less airgap volume than calculated cannot provide the full output power over some portion of its

operating range. Conversely, if the length of the airgap becomes large, magnetic field fringing around the gap occurs.

This increases the airgap volume. Some fringing is usually acceptable, but excessive fringing can cause increased

losses in the windings around the gap, resulting in excessive heating. When a suitable core and gap combination are

found, the iterative design cycle begins. Develop the design and check for ease of assembly and thermal performance.

FN6797 Rev.1.00

Jul 24, 2018

Page 19 of 36

ISL6721A

5. Reference Design

If the core does not allow adequate space for the windings, a core with a larger window area is required. If the

transformer runs hot, it may be necessary to lower the flux density (more primary turns, lower operating frequency),

select a less lossy core material, change the geometry of the windings (winding order), use heavier gauge wire or

multi-filar windings, and/or change the type of wire used (Litz wire, for example).

For simplicity, only the final design is further described.

2

An EPCOS EFD 20/10/7 core using N87 material gapped to an A value of 25nH/N was chosen. It has more than

L

the required air gap volume to store the energy required, but was needed for the window area it provides.

-6

2

Aeff = 31  10

m

-3

lg = 1.56 10

m

The flux density B is only 0.069T or 690 gauss, a relatively low value.

Because Equation 13 shows the number of primary turns, N may be calculated.

p

2

(EQ. 13)



 N  Aeff

o

p

----------------------------------------

L

=

H

p

lg

The result is N = 40 turns. The secondary turns may be calculated as follows (Equation 14):

p

Ig   Vout + Vd  tr

-------------------------------------------------------



(EQ. 14)

N

s

N

 Ippk    Aeff

o

p

where tr is the time required to reset the core. Because discontinuous MMF mode operation is desired, the core

must completely reset during the off time. To maintain Discontinuous mode operation, the maximum time allowed

to reset the core is t - t

where t = 1/f . The minimum time is application dependent and at the

sw ON(MAX)

SW SW

designers discretion, knowing that the secondary winding RMS current and ripple current stress in the output

capacitors increases with decreasing reset time. The calculation for maximum N for the 3.3 V output using

s

t = t - t

= 2.75µs is 5.52 turns.

SW ON (MAX)

The number of secondary turns is also dependent on the number of outputs and the required turns ratios required to

generate them. If Schottky output rectifiers are used and we assume a forward voltage drop of 0.45V, the required

turns ratio for the two output voltages, 3.3V and 1.8V, is 5:3.

With a turns ratio of 5:3 for the secondary windings, we will use N = 5 turns and N = 3 turns. Checking the reset

s1

s2

time using these values for the number of secondary turns yields a duration of Tr = 2.33µs, or about 47% of the

switching period, an acceptable result.

The bias winding turns may be calculated similarly, except a diode forward drop of 0.7V is used. The rounded off

result is 17 turns for a 12V bias.

The next step is to determine the wire gauge. Calculate the RMS current in the primary winding using Equation 15:

t

ONMAX

(EQ. 15)

I

= I



PPK

--------------------------

A

PRMS

3  t

SW

Calculate the peak and RMS current values in the remaining windings using Equations 16 and 17:

2  I

 t

OUT SW

Tr

(EQ. 16)

--------------------------------------

I

=

A

SPK

t

SW

(EQ. 17)

I

= 2  I



OUT

--------------

A

RMS

3  Tr

FN6797 Rev.1.00

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ISL6721A

5. Reference Design

The RMS currents are:

• Primary winding: 0.72A

• 3.3V output: 4.23A

• 1.8V output: 1.69A

• Bias winding: 85mA.

To minimize the transformer leakage inductance, the primary winding is split into two sections connected in

parallel and positioned so that the other windings are sandwiched between them. The output windings are

configured so that the 1.8V winding is a tap off of the 3.3V winding. Tapping the 1.8V output requires that the

shared portion of the secondary conduct the combined current of both outputs. The secondary wire gauge must be

selected accordingly.

The determination of wire current carrying capacity is a compromise between performance, size, and cost. It is

affected by many design constraints such as operating frequency (harmonic content of the waveform) and the

winding proximity/geometry. It generally ranges between 250 and 1000 circular mils per ampere. A circular mil is

defined as the area of a circle 0.001” (1 mil) in diameter. As the frequency of operation increases, the AC resistance

of the wire increases due to skin and proximity effects. Using heavier gauge wire may not alleviate the problem.

Instead multiple strands of wire in parallel must be used. In some cases, Litz wire is required.

The winding configuration selected is:

Primary #1: 40T, 2 #30 bifilar

Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T

Bias: 17T #32

Primary #2: 40T, 2 #30 bifilar

The internal spacing and insulation system is designed for 1500VDC dielectric withstand rating between the

primary and secondary windings.

5.4

Selecting Power MOSFETs

Selecting the main switching MOSFET requires consideration of the voltage and current stresses in the application,

the power dissipated by the device, its size, and its cost.

The converter’s input voltage range is 36VDC to 75VDC. This suggests a MOSFET with a voltage rating of 150V

is required due to the flyback voltage likely to be seen on the primary of the isolation transformer.

The losses associated with MOSFET operation are divided into three categories: conduction, switching, and gate

drive.

The conduction losses are due to the MOSFET’s ON-resistance (Equation 18).

2

(EQ. 18)

Pcond = r

 Iprms

W

DSON

where r

is the ON-resistance of the MOSFET and Iprms is the RMS primary current. Determining the

DS(ON)

conduction losses is complicated by the variation of r

with temperature. As junction temperature increases,

DS(ON)

so does r

, which increases losses and raises the junction temperature more, and so on. It is possible for the

DS(ON)

device to enter a thermal runaway situation without proper heatsinking. Generally, doubling the +25°C r

DS(ON)

specification yields a reasonable value for estimating the conduction losses at +125°C junction temperature.

The switching losses have two components: capacitive switching losses and voltage/current overlap losses. The

capacitive losses occur during device turn-on and can be calculated in Equation 19:

2

1

2

--

Pswcap =  Cfet  Vin  f

(EQ. 19)

W

SW

where Cfet is the equivalent output capacitance of the MOSFET. Device output capacitance is specified on

datasheets as Coss and is non-linear with applied voltage. To find the equivalent discrete capacitance, Cfet, a

FN6797 Rev.1.00

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ISL6721A

5. Reference Design

charge model is used. Using a known current source, the time required to charge the MOSFET drain to the desired

operating voltage is determined and the equivalent capacitance may be calculated in Equation 20:

Ichg  t

(EQ. 20)

-------------------

Cfet =

F

V

The other component of the switching loss is due to the overlap of voltage and current during the switching

transition. A switching transition occurs when the MOSFET is in the process of either turning on or off. Because

the load is inductive, no voltage and current overlap occurs during the turn on transition, so only the turn off

transition is of significance. The power dissipation can be estimated using Equation 21:

1

x

(EQ. 21)

--

P



 I

 V  t  f

IN OL SW

sw

PPK

where t is the duration of the overlap period and x ranges from about 3 through 6 in typical applications and

OL

depends on where the waveforms intersect. This estimate may predict higher dissipation than is realized because a

portion of the turn off drain current is attributable to the charging of the device output capacitance (Coss) and is not

dissipative during this portion of the switching cycle (Figure 8).

Ippk

V_D-S

T ol

Figure 8. Switching Cycle

The final component of MOSFET loss is caused by the charging of the gate capacitance through the device gate

resistance. Depending on the relative value of any external resistance in the gate drive circuit, a portion of this

power will be dissipated externally (Equation 22).

(EQ. 22)

Pgate = Qg  Vg  f

W

SW

When the losses are known, select the device package and design the heatsinking method. Because the design

requires a small surface mount part, an 8 Ld SOIC package was selected. A Fairchild FDS2570 MOSFET was

selected based on these criteria. The overall losses are estimated at 400mW.

5.5

Output Filter Design

In a Flyback design, the primary concern for the design of the output filter is the capacitor ripple current stress and

the ripple and noise specification of the output.

The current flowing in and out of the output capacitors is the difference between the winding current and the output

current. The peak secondary current, I , is 10.73A for the 3.3V output and 4.29A for the 1.8V output. The

SPK

current flowing into the output filter capacitor is the difference between the winding current and the output current.

The 3.3V output’s peak winding current is I

= 10.73A. The capacitor must store this amount minus the output

SPK

current of 2.5A, or 8.23A. The RMS ripple current in the 3.3V output capacitor is about 3.5A

. The RMS ripple

RMS

current in the 1.8V output capacitor is about 1.4A

.

RMS

Voltage deviation on the output during the switching cycle (ripple and noise) is caused by the change in charge of

the output capacitance, the Equivalent Series Resistance (ESR), and Equivalent Series Inductance (ESL). Assign a

portion of the total ripple and noise specification to each of these components. The amount to allow for each

contributor is dependent on the capacitor technology used.

FN6797 Rev.1.00

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ISL6721A

5. Reference Design

For purposes of this discussion, assume the following:

3.3V output: 100mV total output ripple and noise

ESR: 60mV

Capacitor Q: 10mV

ESL: 30mV

1.8V output: 50mV total output ripple and noise

ESR: 30mV

Capacitor Q: 5mV

ESL: 15mV

For the 3.3V output (Equation 23):

V

--------------------------------

0.060

10.73 – 2.5

(EQ. 23)

----------------------------

= 7.3m

ESR 

=

I

– I

SPK

OUT

The change in voltage due to the change in charge of the output capacitor, Q, determines how much capacitance is

required on the output (Equation 24).

–6

I

– I

  tr

OUT

10.73 – 2.5  2.3310

(EQ. 24)

SPK

-----------------------------------------------

------------------------------------------------------------------

= 960F

C 

=

2  V

2  0.010

ESL adds to the ripple and noise voltage in proportion to the rate of change of current into the capacitor

(V = L  di/dt) (Equation 25).

–9

V  dt

0.030  20010

(EQ. 25)

--------------

---------------------------------------------

= 0.56nH

L 

=

di

10.73

High capacitance capacitors usually do not have sufficiently low ESL. High frequency capacitors such as surface

mount ceramic or film are connected in parallel with the high capacitance capacitors to address the effects of ESL.

A combination of high frequency and high ripple capability capacitors is used to achieve the desired overall

performance. The analysis of the 1.8V output is similar to that of the 3.3V output and is omitted for brevity. Two

OSCON 4SEP560M (560µF) electrolytic capacitors and a 22µF X5R ceramic 1210 capacitor were selected for

both the 3.3 and 1.8V outputs. The 4SEP560M electrolytic capacitors are each rated at 4520mA ripple current and

13mΩ of ESR. The ripple current rating of just one of these capacitors is adequate, but two are needed to meet the

minimum ESR and capacitance values.

The bias output is of such low power and current that it places negligible stress on its filter capacitor. A single

0.1µF ceramic capacitor was selected.

5.6

Control Loop Design

The major components of the feedback control loop are a programmable shunt regulator, an opto-coupler, and the

ISL6721A’s inverting amplifier. The opto-coupler transfers the error signal across the isolation barrier. The

opto-coupler is a convenient way to cross the isolation barrier, but it adds complexity to the feedback control loop.

It adds a pole at about 10kHz and a significant amount of gain variation due the Current Transfer Ratio (CTR). The

of the opto-coupler CTR varies with initial tolerance, temperature, forward current, and age.

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ISL6721A

5. Reference Design

Figure 9 shows a block diagram of the feedback control loop.

Primary Side Amplifier

+

-

REF

Power

Stage

V

OUT

PWM

Z

3

Z

4

Error Amplifier

Z

2

Isolation

-

Z

1

REF

+

Figure 9. Feedback Control Loop

The loop compensation is placed around the Error Amplifier (EA) on the secondary side of the converter. The

primary side amplifier located in the control IC is used as a unity gain inverting amplifier and provides no loop

compensation. A Type 2 error amplifier configuration was selected as a precaution if operation in continuous mode

occurs at some operating point (Figure 10).

V

OUT

-

V

ERROR

REF

+

Figure 10. Type 2 Error Amplifier

1

Development of a small signal model for current mode control is rather complex. The reference method was

selected for its ability to accurately predict loop behavior. To further simplify the analysis, the converter will be

modeled as a single output supply with all of the output capacitance reflected to the 3.3V output. When the “single”

output system is compensated, adjustments to the compensation are required based on actual loop measurements.

The first parameter to determine is the peak current feedback loop gain. Because this application is low power, a

resistor in series with the source of the power switching MOSFET is used for the current feedback signal. For

higher power applications, a resistor dissipates too much power and a current transformer would be used instead.

Current loop behavior can be difficult to adjust due to the need to provide overcurrent protection. Current limit and

current loop gain are determined by the current sense resistor and the ISET threshold. ISET was set at 1.0V, near its

maximum, to minimize noise effects. When determining ISET, account for the internal gain and offset of the

ISENSE signal in the control IC. The maximum peak primary current was determined earlier to be 1.87A, so a

choice of 2.25A peak primary current for current limit is reasonable. A current gain, A , of 0.5V/A was selected

EXT

to achieve this (Equation 26).

(EQ. 26)

ISET = 2.25  0.8  0.5 + 0.100 = 1.00

V

Equation 26 represents the control to output transfer function:

s

------

1 +

v



R

 L  f

s SW

2

o

z

o

-----

----------------

= K  ----------------------------------- 

(EQ. 27)

v

c

s

------

1 +



p

FN6797 Rev.1.00

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ISL6721A

5. Reference Design

If we ignore the current feedback sampled-data effects, the value of K can be determined by assuming all of the

output power is delivered by the 3.3V output at the threshold of current limit (Equations 28 through 35):

I

spkmax

(EQ. 28)

-------------------------

K =

V

cmax

R

o

= Load Resistance

(EQ. 29)

(EQ. 30)

(EQ. 31)

(EQ. 32)

(EQ. 33)

(EQ. 34)

(EQ. 35)

L

= Secondary Inductance

s

2

 C

1

--------------------

-----------------------------



C

=

or

f

=

p

z

o

c

R

  R  C

o

1

-------------------

--------------------------------------

=

f

z

R

 C

2    R  C

c

o

c o

= Output Capacitance

R

= Output Capacitor ESR

= Control Voltage Range

V

cmax

The maximum power allowed was determined earlier as 15W, therefore (Equations 36 and 37):

P

OUT

–6

15

3.3

---------------

2 

 t

SW

-------

2 

 510

V

(EQ. 36)

OUT

tr

-----------------------------------------

I

=

= 19.5

A

SPKmax

–6

2.3310

1

--------------------

v

= V

 A

 A 

CS

= 2.93

V

(EQ. 37)

cmax

ISENSE

EXT

A

COMP

where A

is the external gain of the current feedback network, A is the IC internal gain, and A

is the

COMP

EXT

CS

gain between the error amplifier and the PWM comparator.

The Type 2 compensation configuration has two poles and one zero. The first pole is at the origin, and provides the

integration characteristic which results in excellent DC regulation. Referring to the typical boost converter

application schematic (Figure 2 on page 5), the remaining pole and zero for the compensator are located at

(Equations 38 and 39):

C

+ C

14

1

13

------------------------------------------------------------ --------------------------------------------

(EQ. 38)

f

=



pc

2    R  C  C

2    R  C

15 14

15

14

13

1

(EQ. 39)

--------------------------------------------

2    R  C

f

=

zc

15

13

The ratio of R to the parallel combination of R and R determines the mid band gain of the error amplifier

15

17

18

(Equation 40).

R

 R + R



18

15

17

-----------------------------------------------

=

midband

(EQ. 40)

A

R

 R

18

17

Equation 27 shows that the control to output transfer function frequency dependence is a function of the output

load resistance, the value of output capacitance, and the output capacitor ESR. These variations must be considered

when compensating the control loop. The worst case small signal operating point for the converter is at minimum

V , maximum load, maximum C

, and minimum ESR.

IN

OUT

The higher the desired bandwidth of the converter, the more difficult it is to create a solution that is stable over the

entire operating range. A good standard is to limit the bandwidth to about f /4. For this example, the bandwidth will

SW

FN6797 Rev.1.00

Jul 24, 2018

Page 25 of 36

ISL6721A

5. Reference Design

be further limited due to the low GBWP of the LM431-based Error Amplifier (EA) and the opto-coupler. A bandwidth

of approximately 5kHz was selected.

For the EA compensation, the first pole is placed at the origin by default (C is an integrating capacitor). The first

14

zero is placed below the crossover frequency, f , usually around 1/3 f . The second pole is placed at the lower of

co

the ESR zero or at one half of the switching frequency. The midband gain is then adjusted to obtain the desired

crossover frequency. If the phase margin is not adequate, the crossover frequency may have to be reduced.

Using this technique to determine the compensation, the following values for the EA components were selected.

R

C

= R = R = 1kΩ

17

20

13

14

18

15

= open

= 100nF

= 100pF

Figures 11 and 12 show a Bode plot of the system at low line and max load.

50

40

30

20

10

0

200

150

100

50

-10

-20

0

-30

-40

-50

-100

-50

10k

100k

1M

10M

100M

10k

100k

1M

10M

100M

Frequency (Hz)

Figure 12. Phase

Figure 11. Magnitude

5.7

Regulation Performance

Table 2. Output Load Regulation, V_IN= 48V

I_OUT(A), 3.3V

0

I_OUT(A), 1.8V

0.030

0030

0.030

0.52

V_OUT(V), 3.3V

3.351

3.281

3.251

3.223

3.204

3.185

3.168

3.153

3.471

3.283

3.254

3.233

3.218

3.203

3.191

3.619

V_OUT(V), 1.8V

1.825

1.956

1.988

2.014

2.029

2.057

2.084

2.103

1.497

1.800

1.836

1.848

1.855

1.859

1.862

1.347

0.39

0.88

1.38

1.87

2.39

2.89

3.37

0

0.39

0.88

1.38

1.87

2.39

2.89

0

0.52

1.05

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ISL6721A

5. Reference Design

Table 2. Output Load Regulation, V_IN= 48V (Continued)

I

_OUT(A), 3.3V

0.39

0.88

1.38

1.87

2.39

0

I_OUT(A), 1.8V

1.05

V_OUT(V), 3.3V

3.290

3.254

3.235

3.220

3.207

3.699

3.306

3.260

3.239

3.224

3.762

3.329

3.270

3.245

3.819

3.355

3.282

3.869

3.383

V_OUT(V), 1.8V

1.730

1.785

1.805

1.814

1.820

1.265

1.682

1.750

1.776

1.789

1.201

1.645

1.722

1.752

1.142

1.612

1.697

1.091

1.581

1.05

1.55

0.39

0.88

1.38

1.87

0

1.55

2.07

0.39

0.88

1.38

0

2.07

2.62

0.39

0.88

0

2.62

3.14

0.39

3.14

FN6797 Rev.1.00

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ISL6721A

5. Reference Design

5.8

Waveforms

Figures 13 through 15 show typical waveforms. Figure 13 shows the steady state operation of the sawtooth

oscillator waveform at RTCT (Trace 2), the SYNC output pulse (Trace 1), and the GATE output to the converter

FET (Trace 3).

Note:

Trace 1: SYNC Output

Trace 2: RTCT Sawtooth

Trace 3: GATE Output

Figure 13. Typical Waveforms

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ISL6721A

5. Reference Design

Figure 14 shows the converter behavior while operating in an overcurrent fault condition. Trace 1 is the soft-start

voltage, which increases from 0V to 4.5V, at which point the OC fault function is enabled. The OC condition is

detected and the soft-start capacitor is discharged to the 4.375V OC fault threshold at which point the IC enters the

fault shutdown mode. Trace 2 shows the behavior of the timing capacitor voltage during a shutdown fault. Most of

the IC functions, including the oscillator, are de-powered during a fault. During a fault, the IC is turned off until the

restart delay has timed out. After the delay, power is restored and the IC resumes normal operation. Trace 3 is the

GATE output during the soft-start cycle and OC fault.

Note:

Trace 1: SS

Trace 2: RTCT Sawtooth

Trace 3: GATE Output

Figure 14. Soft-Start with Overcurrent Fault

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ISL6721A

5. Reference Design

Figure 15 shows the switching FET waveforms during steady state operation. Trace 1 is drain-source voltage and

Trace 2 is gate-source voltage.

Note:

Trace 1: V_D-S

Trace 3: V_G-S

Figure 15. Gate and Drain-Source Waveforms

5.9

Component List

Reference Designator

Value

1.0µF

0.1µF

560µF

470pF

0.01µF

22µF

Description

Capacitor, 1812, X7R, 100V, 20%

C₁, C₂, C₃

C₅, C₁₃

Capacitor, 0603, X7R, 25V, 10%

Capacitor, Radial, SANYO 4SEP560M

Capacitor, 0603, COG, 50V, 5%

Capacitor, 0805, X7R, 50V, 10%

Capacitor, 1210, X5R, 10V, 20%

Capacitor, 0603, COG, 50V, 5%

Capacitor, Disc, Murata DE1E3KX152MA5BA01

0Ω Jumper, 0603

C₁₅, C₁₆, C₁₉, C₂₀

C₁₇

C₁₈

C₂₁, C₂₂

C₄, C₁₄

100pF

1500pF

C₆

C₇

C₈

330pF

Capacitor, 0603, COG, 50V, 5%

Capacitor, 0603, X7R, 16V, 10%

Diode, Fairchild ES1C

C₉, C₁₀, C₁₁, C₁₂

0.22µF

C_R2, C_R6

C_R4, C_R5

D₁

Diode, IR 12CWQ03FN

Zener, 18V, Zetex BZX84C18

Diode, Schottky, BAT54C

D₂

Q₁

FET, Fairchild FDS2570

Q₂

Transistor, Zetex FMMT491A

Transistor, ON MJD31C

Q₃

R₁, R₂

R₁₀

1.00k

20.0k

Resistor, 1206, 1%

Resistor, 0603, 1%

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ISL6721A

5. Reference Design

Reference Designator

Value

10.0k

38.3k

1.00k

10

Description

R₇, R₉, R₁₁, R₂₆, R₂₇

Resistor, 0603, 1%

Resistor, 1206, 1%

Resistor, 0603, 1%

Resistor, 2512, 1%

Resistor, 0603, 1%

Resistor, 2512, 1%

Resistor, 0603, 1%

OMIT

R₁₂

R₁₃, R₁₅, R₁₇, R₁₈, R₁₉, R₂₅

R₁₄

R₁₆

R₂₁

R₂₂

R₂₄

R₃, R₂₃

R₄

165

10.0

5.11

3.92k

100

1.00

221k

75.0k

R₅

R₆

R₈, R₂₀

T₁

Transformer, MIDCOM 31555

Opto-coupler, NEC PS2801-1

U₂

U₃

Shunt Reference, National LM431BIM3

PWM, Renesas ISL6721A

U₄

V_R1

Zener, 15V, Zetex BZX84C15

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ISL6721A

5. Reference Design

5.10 References

(1) Ridley, R., “A New Continuous-Time Model for Current Mode Control”, IEEE Transactions on Power

Electronics, Vol. 6, No. 2, April 1991.

(2) Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode Power Supply Design Seminar, SEM-700, 1990.

FN6797 Rev.1.00

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ISL6721A

6. Revision History

Rev.

Date

Description

1.00 Jul 24, 2018 Applied new formatting and layout.

Changed Feature bullet from “Adjustable overcurrent shutdown delay” to “Adjustable overcurrent shutdown

threshold” on page 1.

Added tape and reel column and updated Note 1 in Ordering Information table on page 7.

Added Table 1 (Key Differences Between Family of Parts) on page 7.

Updated the SYNC, UV, and ISENSE pin descriptions and moved to page 8.

Removed the word “period” from the Input Frequency Range Max value on page 12.

Changed the titles and y axis labels of Figures 11 and 12 from GAIN and PHASE MARGIN to Magnitude and

Phase, respectively, on page 26.

Added Revision History.

FN6797 Rev.1.00

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Page 33 of 36

ISL6721A

7. Package Outline Drawings

For the most recent package outline drawing, see M16.173.

7. Package Outline Drawings

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 2, 5/10

A

1

3

5.00 ±0.10

SEE DETAIL "X"

9

16

6.40

PIN #1

I.D. MARK

4.40 ±0.10

2

3

0.20 C B A

1

8

B

0.09-0.20

0.65

TOP VIEW

END VIEW

1.00 REF

-

0.05

H

C

0.90 +0.15/-0.10

1.20 MAX

SEATING

PLANE

GAUGE

PLANE

0.25 +0.05/-0.06

0.25

5

0.10

C B A

M

0.10 C

0°-8°

0.05 MIN

0.15 MAX

0.60 ±0.15

SIDE VIEW

DETAIL "X"

(1.45)

NOTES:

1. Dimension does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.

2. Dimension does not include interlead flash or protrusion. Interlead

flash or protrusion shall not exceed 0.25 per side.

3. Dimensions are measured at datum plane H.

(5.65)

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Dimension does not include dambar protrusion. Allowable protrusion

shall be 0.08mm total in excess of dimension at maximum material

condition. Minimum space between protrusion and adjacent lead

is 0.07mm.

(0.65 TYP)

(0.35 TYP)

6. Dimension in ( ) are for reference only.

TYPICAL RECOMMENDED LAND PATTERN

7. Conforms to JEDEC MO-153.

FN6797 Rev.1.00

Jul 24, 2018

Page 34 of 36

ISL6721A

7. Package Outline Drawings

L16.3x3B

For the most recent package outline drawing, see L16.3x3B.

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 4/07

4X

1.5

3.00

0.50

12X

A

6

B

PIN #1 INDEX AREA

16

13

6

PIN 1

INDEX AREA

12

1

4

+

0.10

1.70

- 0.15

9

(4X)

0.15

5

8

0.10 M C A B

+ 0.07

4

16X 0.23

TOP VIEW

- 0.05

16X 0.40 ± 0.10

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

C

0 . 90 ± 0.1

BASE PLANE

SEATING PLANE

0.08

( 2. 80 TYP )

(

C

SIDE VIEW

1. 70 )

( 12X 0 . 5 )

( 16X 0 . 23 )

( 16X 0 . 60)

5

C

0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6797 Rev.1.00

Jul 24, 2018

Page 35 of 36

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

equipment; industrial robots; etc.

"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause

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liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	ISL6721AAVZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	Flexible Single-ended Current Mode PWM Controller; QFN16, TSSOP16; Temp Range: -40° to 105°C 信息通信管理开关光电二极管
文件：	总36页 (文件大小：1320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6721AAVZ-T [RENESAS]

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