ISL70005SEHX/SAMPLE [RENESAS]
Switching Regulator/Controller;
| 型号： | ISL70005SEHX/SAMPLE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Switching Regulator/Controller 信息通信管理 开关 |
| 文件： | 总46页 (文件大小：1400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
ISL70005SEH, ISL73005SEH
Radiation Hardened Dual Output Point-of-Load, Integrated Synchronous Buck and Low Dropout
Regulator
The ISL70005SEH and ISL73005SEH are radiation
hardened dual output Point-of-Load (POL) regulators
combining the high efficiency of a synchronous buck
regulator with the low noise of a Low Dropout (LDO)
Features
• Dual output regulator: sync buck and LDO
• Independent EN, SS, and PG indicators
regulator. They are suited for systems with 3.3V or 5V
power buses and can support continuous output load
currents of 3A for the buck regulator and ±1A for the
LDO.
• ±1% reference voltage
• 1A current sourcing/sinking capability on LDO
• External clock synchronization: 100kHz to 1MHz
• Full military temperature range operation
The buck regulator uses a voltage mode control
architecture and switches at a resistor adjustable
frequency of 100kHz to 1MHz. Externally adjustable
loop compensation allows for an optimum balance
between stability and output dynamic performance.
The internal synchronous power switches are
optimized for high efficiency and excellent thermal
performance.
○ T = -55°C to +125°C
A
○ T = -55°C to +150°C
J
• Radiation acceptance testing - ISL70005SEH
○ HDR (50-300rad(Si)/s): 100krad(Si)
○ LDR (0.01rad(Si)/s): 75krad(Si)
• Radiation acceptance testing - ISL73005SEH
○ LDR (0.01rad(Si)/s): 75krad(Si)
The LDO is completely configurable independent of
the switching regulator. It uses NMOS pass devices
and separate chip bias voltage (L_VCC) to drive its
gate, enabling the LDO to operate with a very low
voltage at the L_VIN input. The LDO can sink and
source up to 1A continuously, making it an ideal
choice to power DDR memory.
• SEE hardness (see test report)
2
○ No SEB or SEL at LET 86.4MeV•cm /mg
2
○ SET at LET 86.4MeV•cm /mg <±3% ΔV
OUT
2
○ No SEFI at LET 43MeV•cm /mg
The ISL70005SEH and ISL73005SEH are available
in a space saving 28 Ld ceramic dual flat-pack
package or in die form. They are specified to operate
• Electrically screened to DLA SMD 5962-19209
Applications
across a temperature range of T = -55°C to +125°C.
A
• Point-of-load for low power FPGA core, auxiliary
and I/O supply voltages
Related Literature
• DDR memory power for VDDQ and VTT rails
• Distributed power system of satellite payloads
For a full list of related documents visit our website:
• ISL70005SEH, ISL73005SEH device pages
ISL70005SEH, ISL73005SEH
Buck Regulator
0.915
0.910
0.905
0.900
3.3V or 5V
VDDQ = 1.8V
B_PVINx B_LXx
VDDQ
VTT = 0.9V
L_VIN
L_OUT
LDO Regulator
DDR Memory
Controller
R
T
DDR
Memory
L_VCC = B_VCC = 5V
L_VIN = 1.8V
0.895
R
S
L_EA+ = 0.9V
0.890
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
LDO Current (A)
Figure 2. LDO Load Regulation; DDR2 Configuration
Figure 1. Power Solution for DDR2 Memory
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 1 of 46
ISL70005SEH, ISL73005SEH
Contents
1.
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
1.3
1.4
1.5
Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.
4.
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1
4.2
4.3
4.4
Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low Dropout Regulator (LDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Internal Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Over-Temperature Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Power Supply Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Switching Frequency Selection and External Sync for Buck Regulator. . . . . . . . . . . . . . . . . . . . . . . . 31
B_EN and L_EN Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Soft-Start Capacitor for Buck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Soft-Start Capacitor for LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power-Good Indicator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Independent Output Point-of-Load Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LDO Tracking Buck for DDR Memory Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.
Synchronous Buck Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1
6.2
6.3
6.4
6.5
Buck Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Buck Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Buck Output Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Buck Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Buck Feedback Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.
8.
LDO Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
LDO Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LDO Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1
8.2
8.3
Buck Regulator PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LDO Regulator PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Example PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 2 of 46
ISL70005SEH, ISL73005SEH
9. Die and Assembly Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10. Metalization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 3 of 46
ISL70005SEH, ISL73005SEH
1. Overview
1. Overview
1.1
Typical Application Schematics
VIN = 3.3V
ISL70005SEH
to FPGA
to FPGA
1
2
3
4
5
6
7
8
9
B_SS
L_PG 28
B_PG 27
B_FB
B_COMP
B_RT
B_VIN2 26
B_LX2 25
VIN = 3.3V
VCORE = 1.8V
+
VIN = 3.3V
From FPGA
B_VCC B_PGND2 24
B_SYNC B_PGND1 23
B_LX1 22
B_VIN1 21
TEST 20
B_GND1
B_GND2
VREF
R4
VIN = 3.3V
R1
From I/O Port
From I/O Port
10 B_EN
11 L_EN
12 L_VCC
13 L_SS
14 L_EA+
L_VIN 19
L_OUT 18
L_PGND 17
L_GND 16
L_EA- 15
VIN = 3.3V
VI/O = 1.5V
VIN = 3.3V
RF
RG
Figure 3. ISL70005SEH Application for Low Power FPGA Core and I/O Supply
VIN = 3.3V
ISL70005SEH
to I/O Port
1
2
3
4
5
6
7
8
9
B_SS
L_PG 28
B_PG 27
to I/O Port
B_FB
B_COMP
B_RT
B_VIN2 26
B_LX2 25
VIN = 3.3V
VDDQ = 1.8V
+
VIN = 3.3V
From FPGA
B_VCC
B_PGND2 24
B_SYNC B_PGND1 23
B_LX1 22
B_VIN1 21
TEST 20
B_GND1
B_GND2
VREF
R4
VIN = 3.3V
R1
From I/O Port
From I/O Port
VDDQ = 1.8V
VTT = 0.9V (Tracks VDDQ)
10 B_EN
11 L_EN
12 L_VCC
13 L_SS
14 L_EA+
L_VIN 19
L_OUT 18
L_PGND 17
L_GND 16
L_EA- 15
VIN = 3.3V
RF
RG
VDDQ/2
Figure 4. ISL70005SEH Application for DDR Memory Power Solution
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 4 of 46
ISL70005SEH, ISL73005SEH
1. Overview
1.2
Functional Block Diagram
B_GND1,
B_GND2
B_VIN1,
B_VIN2
B_PG
B_RT
B_SYNC
B_VCC
B_VCC
B_VCC
B_GND
B_VCC
SHDNB
PGOOD
Logic
Oscillator and Clock
Generator
+ Current
Sense
SHDN
B
B_VCC
B_COMP
B_VCC
B_FB
VREF
PWM Control Logic,
Gate Drive and
Overcurrent Limit
B_LX1,
B_LX2
L_VCC
B_VCC
VREF
600mV
B_PGND1,
B_PGND2
B_VCC
L_VCC
I
SS
L_VCC
SHDNB
B_SS
THERMAL
SENSE
UVLO and Shutdown
Logic
B_EN
L_EN
L_VCC
L_VIN
Source
SHDNL
L_PG
I_SENSE
L_VCC
L_VCC
SHDNL
PGOOD
Logic
L_OUT
L_VCC
Sink
I_SENSE
B_GND
Overcurrent
Limit
L_PGND
L_GND
L_VCC
L_PGND
I
SS
L_VCC
L_VCC
L_GND
L_GND
B_PGND
L_EA- L_EA+
L_SS
Figure 5. Block Diagram
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 5 of 46
ISL70005SEH, ISL73005SEH
1. Overview
1.3
Ordering Information
Package
(RoHS
Compliant)
Ordering SMD
Part Number
(Note 2)
Radiation Hardness
(Total Ionizing Dose)
Temperature
Range (°C)
Package
Drawing
Number (Note 1)
5962R1920901VXC
5962R1920901V9A
5962L1920902VXC
5962L1920902V9A
N/A
ISL70005SEHVF
HDR to 100krad(Si)
LDR to 75krad(Si)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
28 Ld CDFP
Die
K28.A
ISL70005SEHVX (Note 5)
-
ISL73005SEHVF
LDR to 75krad(Si)
28 Ld CDFP
Die
K28.A
ISL73005SEHVX (Note 5)
-
K28.A
-
ISL70005SEHF/PROTO (Note 3)
ISL70005SEHX/SAMPLE (Notes 3, 5)
ISL70005SEHDEMO1Z (Note 4)
ISL70005SEHEV2Z (Note 4)
N/A
28 Ld CDFP
Die
N/A
N/A
N/A
Evaluation Board
Evaluation Board
N/A
Notes:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers
listed must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100%Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are
intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature
specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the
electrical limits and conditions specified in the DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the
DLA SMD electrical limits. These part types do not come with a Certificate of Conformance because they are not DLA qualified devices.
4. Evaluation boards use the /PROTO parts and /PROTO parts are not rated or certified for total ionizing dose (TID) or Single Event Effect
(SEE) immunity.
5. Die product tested at TA = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of
meeting the electrical performance outlined in “Electrical Specifications” on page 10.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 6 of 46
ISL70005SEH, ISL73005SEH
1. Overview
1.4
Pin Configuration
28 Ld CDFP
Top View
B_SS
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
L_PG
B_PG
B_FB
B_COMP
B_RT
B_VIN2
B_LX2
B_PGND2
B_PGND1
B_LX1
B_VCC
B_SYNC
B_GND1
B_GND2
VREF
B_VIN1
9
20
19
TEST
10
L_VIN
B_EN
11
12
13
14
18
17
16
15
L_OUT
L_PGND
L_GND
L_EA-
L_EN
L_VCC
L_SS
L_EA+
Note: The ESD triangular mark is indicative of Pin #1. It is a part of the device
marking and is placed on the lid in the quadrant where Pin #1 is located.
1.5
Pin Descriptions
Pin
Number Pin Name ESD Circuit
Description
1
2
3
4
5
B_SS
2
2
2
2
5
Soft-start input to the buck regulator. When B_EN is driven above 2V, a 24µA pull-up current charges
a ceramic capacitor connected from B_SS to B_GNDx to set the soft-start ramp time.
B_FB
Inverting input to the buck error amplifier. Connect a type III compensation network between this pin
and the B_COMP pin.
B_COMP
B_RT
Output for the error amplifier of the buck regulator. Connect an external compensation network
between this pin and the B_FB pin.
Oscillator frequency select input. Connect a resistor from this pin to B_GNDx to program the
switching frequency from 100kHz to 1MHz.
B_VCC
Supply input to the internal buck control circuitry. Bypass B_VCC to B_GNDx using a ceramic
capacitor as close as possible to the IC.
Note: B_VCC must be connected to the same DC voltage as B_VINx and L_VCC.
6
B_SYNC
2
Clock frequency synchronization input to the buck regulator. During soft-start, the ISL7x005SEH
uses its internal oscillator until B_SS >600mV, and then synchronizes to B_SYNC if a clock is
present. The rising edge of B_SYNC starts a new PWM cycle (begins minimum off-time). Connect to
GND if synchronization is not used.
7
8
9
B_GND1
B_GND2
VREF
N/A
N/A
1
Buck analog ground pin and package lid connection.
Output of the 600mV reference voltage. Bypass this pin to L_GND with a minimum 100nF ceramic
capacitor located as close as possible to the IC. This pin may be used as the LDO reference voltage
by connecting VREF to L_EA+. Additional loading is not recommended.
10
11
12
B_EN
L_EN
6
6
4
Enable input to the buck regulator. Driving this pin above 2V enables the buck.
Enable input to the LDO. Driving this pin above 2V enables the LDO.
L_VCC
Bias supply pin to the LDO analog circuitry and common functions circuitry. Bypass L_VCC to
L_GND using a ceramic capacitor as close as possible to the IC.
Note: L_VCC must be connected to the same DC voltage as B_VCC and B_VINx.
13
14
L_SS
1
1
Soft-start input to the LDO. When L_EN is driven above 2V, a 24µA pull-up current charges the
ceramic capacitor connected from L_SS to L_GND to set the soft-start output ramp time.
L_EA+
Non-inverting input to the LDO error amplifier. Connect this pin to the VREF pin for independent LDO
application or a resistor divider from the buck output for tracking DDR memory power applications.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 7 of 46
ISL70005SEH, ISL73005SEH
1. Overview
Pin
Number Pin Name ESD Circuit
Description
15
L_EA-
1
Inverting input to the LDO error amplifier. Connect a resistor divider network from L_OUT to this pin
to set the output voltage. Connect L_EA- to L_OUT for setting L_OUT equal to L_EA+.
16
17
18
19
20
21
L_GND
L_PGND
L_OUT
L_VIN
NA
NA
1
LDO analog ground pin.
LDO power-stage ground pin.
LDO output pin.
4
Input supply for the LDO power-stage MOSFET. L_VIN voltage must not exceed L_VCC.
Factory use only. Must be connected to L_GND in application.
TEST
6
B_VIN1
3
Input supply for the buck power-stage MOSFETs. Bypass B_VINx pins directly to B_PGNDx with
ceramic capacitors located as close as possible to the IC.
Note: B_VIN1 must be connected to the same DC voltage as B_VCC and L_VCC.
22
B_LX1
NA
Buck regulator switch node connection. Output of the internal buck power MOSFETs. Connect to the
power inductor.
23
24
25
B_PGND1
B_PGND2
B_LX2
NA
NA
NA
Buck power-stage ground pin.
Buck regulator switch node connection. Output of the internal buck power MOSFETs. Connect to the
power inductor.
26
27
B_VIN2
B_PG
L_PG
N/A
3
2
Input supply for the buck power-stage MOSFETs. Bypass B_VINx pins directly to B_PGNDx with
ceramic capacitors located as close as possible to the IC.
Note: B_VIN2 must be connected to the same DC voltage as B_VCC and L_VCC.
Power-good output for the buck regulator. This output is open-drain logic. Connect a 10kΩ to 100kΩ
pull-up resistor to B_VCC. Can be wired-OR with L_PG to have a single power-good signal. Bypass
B_PG to B_GND with a 1nF ceramic capacitor to mitigate SEE.
28
2
Power-good output for the LDO. This output is open-drain logic, connect a 10kΩ to 100kΩ pull-up
resistor to L_VCC. Can be wired-OR with B_PG to have a single power-good signal. Bypass L_PG to
L_GND with a 1nF ceramic capacitor to mitigate SEE.
LID
N/A
The top lid of the package is electrically connected to pins 7 (B_GND1) and 8 (B_GND2).
L_VCC
PIN #
B_VCC
PIN #
B_VINx
7V
Clamp
Circuit 1
Circuit 2
Circuit 3
B_PGND
L_GND
B_GND
L_VCC
PIN #
B_VCC
7V
Clamp
7V
Clamp
Circuit 4
Circuit 5
Circuit 6
PIN #
L_GND
B_GND
L_GND
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 8 of 46
ISL70005SEH, ISL73005SEH
2. Specifications
2. Specifications
2.1
Absolute Maximum Ratings
Parameter
Minimum
B_GND - 0.3
B_GND - 0.3
B_PGND - 0.3
B_PGND - 0.3
L_GND - 0.3
L_GND - 0.3
L_GND - 0.3
L_GND - 0.3
Maximum
Unit
V
B_VCC
B_GND + 6.5
B_GND + 6.0
B_PGND + 6.5
B_PGND + 6.0
L_GND + 6.5
L_GND + 6.0
L_GND + 6.5
L_GND + 6.0
B_VCC (Notes 6, 7)
B_VINx
V
V
B_VINx (Notes 6, 7)
L_VCC
V
V
L_VCC (Notes 6, 7)
L_VIN
V
V
L_VIN (Notes 6, 7)
B_LXx
V
B_PGND - 0.3; limit 6.5 from
B_VIN
B_VINx + 0.3; limit 6.5 to
B_PGND
V
B_LXx (Notes 6, 7)
B_PGND - 0.3; limit 6.0 from
B_VIN
B_VINx + 0.3; limit 6.0 to
B_PGND
V
V
B_LXx (<50ns pulse width up to 1MHz switching frequency)
B_PGND - 2.0; limit 6.5 from
B_VIN
B_VINx + 1.5; limit 6.5 to
B_PGND
L_OUT
L_PGND - 0.3
L_PGND - 0.3
B_GND - 0.3
L_GND - 0.3
B_GND - 0.3
L_VIN + 0.3; limit 6.5
L_VIN + 0.3; limit 6.0
B_VCC + 0.3
V
V
V
V
V
L_OUT (Notes 6, 7)
L_PG, B_PG, B_RT, B_SYNC, B_COMP, B_FB
B_EN, L_EN, L_EA-, L_EA+, VREF, TEST
B_SS
L_VCC + 0.3
B_VCC + 0.3, limit B_GND +
3.5
L_SS
L_GND - 0.3
L_VCC + 0.3, limit L_GND +
3.5
V
B_GND to L_PGND, B_GND to L_GND, L_GND to L_PGND
B_GND to B_PGND, L_GND to B_PGND, L_PGND to B_PGND
ESD Rating
-0.3
-0.6
0.3
0.6
V
V
Value
Unit
kV
V
Human Body Model (Tested per MIL-STD-883 TM3015.7)
Charged Device Model (Tested per JS-002-2014)
2
750
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
Notes:
6. For operation in a heavy ion environment at LET = 86.4MeV•cm2/mg at 125°C (TC) and with buck converter sourcing 0A and 3.5A load
current.
7. For operation in a heavy ion environment at LET = 86.4MeV•cm2/mg at 125°C (TC) with LDO sourcing and sinking 1.2A load current.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 9 of 46
ISL70005SEH, ISL73005SEH
2. Specifications
2.2
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
1.2
CDFP Package K28.A (Notes 8, 9)
19.5
Notes:
8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See
TB379.
9. For θJC, the case temperature location is the center of the package underside.
Parameter
Maximum Junction Temperature
Storage Temperature Range
Minimum
Maximum
+150
Unit
°C
-65
+150
°C
2.3
Recommended Operating Conditions
Parameter
Minimum
-55
Maximum
+125
Unit
°C
Ambient Temperature
B_VIN1, B_VIN2, B_VCC, L_VCC
3.3 ±10%
5.0 ±10%
V
(These four pins must be at the same DC voltage)
L_VIN
1.0
0.6
L_VCC
1.27
V
V
L_EA+, L_EA-
2.4
Electrical Specifications
Buck Regulator Electrical Specifications
2.4.1
Unless otherwise noted, B_VINx = B_VCC = 3V to 5.5V; B_GND = B_PGNDx = 0V; B_EN = 2.0V; B_SYNC = B_LXx = Open Circuit; B_PG is
pulled up to B_VCC with a 3kΩ resistor; VREF is bypassed to L_GND with a 22nF capacitor; B_SS is bypassed to B_GNDx with a 220nF
capacitor; IOUT = 0A; TA = TJ = +25°C. Boldface limits apply across the operating temperature range, -55°C to +125°C, without
irradiation. They also apply at +25°C after total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s
(ISL70005SEH only) or after total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
Parameter
Test Conditions
Min
Typ
Max
Unit
Power Supply
Operating Supply Current - Switching
Shutdown Supply Current - Idle
Enable Pin Characteristics
B_EN Rising Threshold
B_EN = 2V, 100kHz switching, B_LXx floating
B_EN = GND
10
15
mA
mA
0.6
3.0
1.6
1.4
100
80
2.0
1.9
V
V
B_EN Falling Threshold
B_EN Input Hysteresis
200
100
mV
kΩ
kΩ
B_EN Pull-Down Resistance
B_EN Pull-Down Resistance
PWM Control Logic
B_EN = 5.5V
B_EN = 1.4V
160
130
60
Switching Frequency
B_RT resistor = 544kΩ
B_RT resistor = 44kΩ
85
115
kHz
kHz
ns
875
100
1000 1175
B_LXx Minimum On-Time
B_LXx Minimum On-Time
B_LXx Minimum Off-Time
B_VIN = B_VCC = 5.5V, B_COMP = 180mV,
1kΩ from B_LXx to 2.75V
175
215
105
240
325
165
B_VIN = B_VCC = 3V, B_COMP = 180mV,
1kΩ from B_LXx to 1.5V
115
50
ns
ns
B_COMP = 180mV,
1kΩ from B_LXx to [B_VIN / 2]
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 10 of 46
ISL70005SEH, ISL73005SEH
2. Specifications
Unless otherwise noted, B_VINx = B_VCC = 3V to 5.5V; B_GND = B_PGNDx = 0V; B_EN = 2.0V; B_SYNC = B_LXx = Open Circuit; B_PG is
pulled up to B_VCC with a 3kΩ resistor; VREF is bypassed to L_GND with a 22nF capacitor; B_SS is bypassed to B_GNDx with a 220nF
capacitor; IOUT = 0A; TA = TJ = +25°C. Boldface limits apply across the operating temperature range, -55°C to +125°C, without
irradiation. They also apply at +25°C after total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s
(ISL70005SEH only) or after total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
Parameter
Modulator Gain (Note 10)
Test Conditions
Min
Typ
Max
Unit
V/V
kHz
2.35
External Synchronization Range
B_RT clock set to 90% of B_SYNC clock, 50% duty cycle
clock input
100
2
1000
B_SYNC Input Voltage
B_SYNC VIH voltage
B_SYNC VIL voltage
V
V
0.8
1
B_SYNC Input Leakage Current
Soft-Start
-1
µA
Soft-Start Source Current
Soft-Start Discharge ON-Resistance
Soft-Start Discharge Time
SS = GND
17
23
3.0
256
30
µA
6.0
Ω
Clock
Cycles
Reference Voltage
Reference Voltage Tolerance
Error Amplifier
VREF + error amplifier VIO
0.594
0.6
0.606
V
DC Gain (Note 10)
80
7
dB
MHz
V
Gain-Bandwidth Product (Note 10)
Maximum Output Voltage
Slew Rate (Note 10)
B_VCC = 5.5V
3.5
4.2
8.5
V/µs
nA
B_FB Input Leakage Current
Power MOSFET
B_FB = 0.6V, B_VINx = 5.5V
250
Packaged Upper Device rDS(ON)
B_VINx = B_VCC = 3.0V; single B_LXx output
B_VINx = B_VCC = 5.5V; single B_LXx output
B_VINx = B_VCC = 3.0V; single B_LXx output
B_VINx = B_VCC = 5.5V; single B_LXx output
80
65
40
35
160
130
90
245
210
160
150
15
mΩ
mΩ
mΩ
mΩ
%
Packaged Lower Device rDS(ON)
85
Packaged ON Resistance Matching,
B_LX1 rDS(ON)_1 to B_LX2 rDS(ON)_2,
Upper and Lower Device
TA = +125°C
Match = | rDS(ON)_1 - rDS(ON)_2 | / AVG
where AVG = (rDS(ON)_1 + rDS(ON)_2) / 2
5
Die Upper Device rDS(ON)
B_VINx = B_VCC = 3.0V; TA = 25°C single B_LXx output
B_VINx = B_VCC = 5.5V; TA = 25°C single B_LXx output
B_VINx = B_VCC = 3.0V; TA = 25°C Single B_LXx output
B_VINx = B_VCC = 5.5V; TA = 25°C single B_LXx Output
40
20
15
10
75
50
35
30
5
110
85
60
65
15
mΩ
mΩ
mΩ
mΩ
%
Die Lower Device
rDS(ON)
Die ON Resistance Matching,
B_LX1 rDS(ON)_1 to B_LX2 rDS(ON)_2
Upper and Lower Device
B_VINx = 3.0V; TA = +25°C
Match = | rDS(ON)_1 - rDS(ON)_2 | / AVG
where AVG = (rDS(ON)_1 + rDS(ON)_2) / 2
B_LXx Output Leakage
B_EN = B_LXx = xGND, single B_LXx output
3
µA
µA
ns
B_EN = GND, B_LXx = 5.5V, single B_LXx output
15
50
Dead Time (Note 10)
0
30
Power-Good Signal
B_PG Overvoltage Error Threshold
B_PG Overvoltage Error Hysteresis
B_PG Undervoltage Error Threshold
B_FB as a % of VREF
B_FB as a % of VREF
B_FB as a % of VREF
107
1.5
85
111
3.5
89
115
5
%
%
%
93
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 11 of 46
ISL70005SEH, ISL73005SEH
2. Specifications
Unless otherwise noted, B_VINx = B_VCC = 3V to 5.5V; B_GND = B_PGNDx = 0V; B_EN = 2.0V; B_SYNC = B_LXx = Open Circuit; B_PG is
pulled up to B_VCC with a 3kΩ resistor; VREF is bypassed to L_GND with a 22nF capacitor; B_SS is bypassed to B_GNDx with a 220nF
capacitor; IOUT = 0A; TA = TJ = +25°C. Boldface limits apply across the operating temperature range, -55°C to +125°C, without
irradiation. They also apply at +25°C after total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s
(ISL70005SEH only) or after total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
Parameter
B_PG Undervoltage Error Hysteresis
B_PG Drive
Test Conditions
B_FB as a % of VREF
Min
1.5
7.2
Typ
Max
5
Unit
%
3.5
B_VIN = 3V, B_PG = 0.4V, B_EN = GND
B_VINx = B_PG = 5.5V
mA
µA
B_PG Leakage
1
Protection Features
Undervoltage Protection
Undervoltage Trip Threshold
Undervoltage Recovery Threshold
Overcurrent Protection
Overcurrent Limit
B_FB as a % of VREF; in test mode
B_FB as a % of VREF, in test mode
71
86
75
90
79
94
%
%
4.0
6.4
A
Note:
10. Specifications established by characterization or analysis and are not production tested.
2.4.2
LDO Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the following specified conditions: COUT = 150µF tantalum, TA = TJ = +25°C,
IL = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. See “Applications
Information” on page 31 and TB379. Boldface limits apply across the operating temperature range, -55°C to +125°C without irradiation.
They also apply at +25°C after total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70005SEH
only) or after total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. Pulse load techniques used by ATE to
ensure TJ = TA.
Parameter
DC Characteristics
Test Conditions
Min
Typ
Max
Unit
L_VIN Voltage Range
L_OUT Voltage Range
MIN ensured by L_VIN dropout testing
0.775
0.6
L_VCC
V
V
MIN ensured by L_VIN dropout testing;
MAX ensured by L_VCC dropout testing;
L_EA+ = 0.600V
L_VCC - 1.5
VREF Voltage
0.591
0.609
V
Power-On Reset
L_VCC Internal UVLO Rising Threshold
L_VCC Internal UVLO Falling Threshold
L_VCC Internal UVLO Hysteresis
2.6
2.45
75
2.8
2.95
2.80
420
V
V
175
mV
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 12 of 46
ISL70005SEH, ISL73005SEH
2. Specifications
Unless otherwise noted, all parameters are guaranteed over the following specified conditions: COUT = 150µF tantalum, TA = TJ = +25°C,
IL = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. See “Applications
Information” on page 31 and TB379. Boldface limits apply across the operating temperature range, -55°C to +125°C without irradiation.
They also apply at +25°C after total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70005SEH
only) or after total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. Pulse load techniques used by ATE to
ensure TJ = TA. (Continued)
Parameter
Test Conditions
Min
Typ
Max
Unit
DC Output Voltage Accuracy, L_OUTx
L_VIN = [4.15V, 5.5V], L_VCC = 5.5V, R1/R2 = 4.5,
R1: L_OUT to L_EA-; R2: L_EA- to L_GND
L_EA+ = 0.600V, ILOAD = [10mA, 1A]
L_OUTx where x = [1, 3, 5, 7]
3.225 3.272
3.285 3.327
1.463 1.487
3.336
V
L_VIN = [4.15V, 5.5V], L_VCC = 5.5V, R1/R2 = 4.5,
R1: L_OUT to L_EA-; R2: L_EA- to L_GND
L_EA+ = 0.600V, ILOAD = [-10mA, -1A]
L_OUTx where x = [2, 4, 6, 8]
3.397
1.519
V
V
L_VIN = [2V, 3V, 5.5V], L_VCC = [3.35V, 5.5V],
R1/R2 = 1.5,
R1: L_OUT to L_EA-; R2: L_EA- to L_GND
L_EA+ = 0.600V, ILOAD = [10mA, 1A]
L_OUTx where x = [9, 11, 13, 15, 17, 19, 21, 23]
L_VIN = [2V, 3V, 5.5V], L_VCC = [3.35V, 5.5V],
R1/R2 = 1.5,
1.490 1.512
1.546
V
R1: L_OUT to L_EA-; R2: L_EA- to L_GND
L_EA+ = 0.600V, ILOAD = [-10mA, -1A]
L_OUTx where x = [10, 12, 14, 16, 18, 20, 22, 24]
L_VIN = [1.75V, 3V, 5.5V],
1.235 1.245
1.246 1.255
0.585 0.595
0.596 0.605
1.258
1.269
0.608
0.619
15
V
V
L_VCC = [3.1V, 5.5V], L_EA- = L_OUT,
L_EA+ = 1.250V, ILOAD = [10mA, 1A]
L_OUTx where x = [25, 27, 29, 31, 33, 35, 37, 39]
L_VIN = [1.75V, 3V, 5.5V]
L_VCC = [3.1V, 5.5V], L_EA- = L_OUT,
L_EA+ = 1.250V, ILOAD = [-10mA, -1A]
L_OUTx where x = [26, 28, 30, 32, 34, 36, 38, 40]
L_VIN = [1.1V, 3V, 5.5V], L_VCC = [3V, 5.5V],
L_EA- = L_OUT,
L_EA+ = 0.600V, ILOAD = [10mA, 1A]
L_OUTx where x = [41, 43, 45, 47, 49, 51, 53, 55]
V
L_VIN = [1.1V, 3V, 5.5V], L_VCC = [3V, 5.5V],
L_EA- = L_OUT,
L_EA+ = 0.600V, ILOAD = [-10mA, -1A]
L_OUTx where x = [42, 44, 46, 48, 50, 52, 54, 56]
V
Regulation Dead-Band
L_VOUT difference between the two current cases:
5
10
mV
I
OUT = [sourcing 10mA, sinking 10mA]
for L_VCC = 5.5V, L_VIN = 5.5V,
L_EA+ = 0.600V, L_OUT = L_EA-
L_EA+, L_EA- Input Bias Current
L_VCC Pin Current
L_EA+ = L_EA- = 0.6V, L_VIN = 5.5V
1
µA
L_OUT = 1.5V; ILOAD = 1A; L_VIN = 1.65V;
3.0V < L_VCC < 5.5V
7.2
10
mA
L_VCC Pin Current in Shutdown
L_EN = B_EN = 0V, L_VCC = 5.5V
450
1000
1.5
µA
V
L_VCC Dropout Voltage L_VCCDO
(Note 13)
IOUT = 1A, L_OUT = 3.3V; L_VIN = 3.8V
L_VCC = L_OUT + L_VCCDO
;
L_VIN Dropout Voltage, L_VINDO (Note 12) IOUT = 1A, L_OUT = 0.6V; L_VIN = L_OUT +
L_VINDO; 3.0V < L_VCC < 5.5V; TA = -55°C
75
115
145
175
mV
mV
mV
I
OUT = 1A, L_OUT = 0.6V; L_VIN = L_OUT +
100
135
L_VINDO; 3.0V < L_VCC < 5.5V; TA = 25°C
IOUT = 1A, L_OUT = 0.6V; L_VIN = L_OUT +
L_VINDO; 3.0V < L_VCC < 5.5V; TA = 125°C
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 13 of 46
ISL70005SEH, ISL73005SEH
2. Specifications
Unless otherwise noted, all parameters are guaranteed over the following specified conditions: COUT = 150µF tantalum, TA = TJ = +25°C,
IL = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. See “Applications
Information” on page 31 and TB379. Boldface limits apply across the operating temperature range, -55°C to +125°C without irradiation.
They also apply at +25°C after total ionizing dose of 100krad(Si) with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70005SEH
only) or after total ionizing dose of 75krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. Pulse load techniques used by ATE to
ensure TJ = TA. (Continued)
Parameter
Protection Features
Test Conditions
Min
Typ
Max
Unit
Positive Overcurrent Limit
Negative Overcurrent Limit
1.25
-2
2
A
A
-1.25
195
Thermal Shutdown Temperature (Note 11) Junction temperature
153
175
8
°C
°C
Thermal Shutdown Hysteresis (Rising
Threshold) (Note 11)
Junction temperature
AC Ripple Rejection and Noise Characteristics
1kHz VIN Supply Ripple Rejection
V
P-P = 300mV; f = 1kHz; ILOAD = 1A;
60
50
80
50
70
36
11
dB
dB
L_VCC = 5V; L_VIN = 3.15V; L_OUT = 1.5V
100kHz VIN Supply Ripple Rejection
(Note 11)
VP-P = 300mV; f = 100kHz; ILOAD = 1A;
L_VCC = 5V; L_VIN = 3.15V; L_OUT = 1.5V
1kHz L_VCC Supply Ripple Rejection
V
P-P = 300mV; f = 1kHz; ILOAD = 1A;
dB
L_VCC = 5V; L_VIN = 3V; L_OUT = 1.5V
100kHz L_VCC Supply Ripple Rejection
(Note 11)
VP-P = 300mV; f = 100kHz; ILOAD = 1A;
L_VCC = 5V; L_VIN = 3V; L_OUT = 1.5V
dB
Output Noise Voltage (Note 11)
L_VCC = 5V; L_VIN = 1.4V;
µVRMS
L_OUT = 1.25V; ILOAD = 100mA;
BW = 10Hz < f < 100kHz; L_EA- = L_OUT
Enable Pin Characteristics
L_EN Rising Threshold
1.6
1.4
100
80
2.0
1.9
V
V
L_EN Falling Threshold
L_EN Input Hysteresis
200
mV
kΩ
kΩ
L_EN Pull-Down Resistance
L_EN Pull-Down Resistance
PGOOD Characteristics
L_PG Overvoltage Error Threshold
L_PG Overvoltage Error Hysteresis
L_PG Undervoltage Error Threshold
L_PG Undervoltage Error Hysteresis
L_PG Output Low Drive
L_EN = 5.5V
L_EN = 1.4V
160
130
60
L_EA- as a % of L_EA+; L_EA+ = 0.6V
L_EA- as a % of L_EA+; L_EA+ = 0.6V
L_EA- as a % of L_EA+; L_EA+ = 0.6V
L_EA- as a % of L_EA+; L_EA+ = 0.6V
L_VCC = 3V; L_PG = 0.4V; L_EN = L_GND
L_VIN = L_PG = 5.5V
107
1.5
85
111
3.5
89
115
5
%
%
93
5
%
1.5
7.2
3.5
%
mA
µA
L_PG Leakage Current
1
Notes:
11. Specifications established by characterization or design and are not production tested.
12. L_VIN dropout is defined by the difference in L_VIN and L_OUT when the regulator produces a 2% drop in L_OUT from its nominal value.
13. L_VCC dropout is defined by the difference in L_VCC and L_OUT when the regulator produces a 2% drop in L_OUT from its nominal
value.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 14 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C.
f
100
90
80
70
60
50
40
100
90
80
70
60
50
40
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
Vout = 1.5V
Vout = 2.5V
Vout = 1.8V
Vout = 1.5V
0.0
0.5
1.0
1.5
Load Current (A)
2.0
2.5
3.0
3.0
3.0
0.0
0.5
1.0
1.5
Load Current (A)
2.0
2.5
3.0
Figure 6. Efficiency vs IOUT; B_VIN = 3V; 100kHz
Figure 7. Efficiency vs IOUT; B_VIN = 5V; 100kHz
95
95
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
Vout = 1.5V
Vout = 1.8V
Vout = 1.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
Load Current (A)
Load Current (A)
Figure 8. Efficiency vs IOUT; B_VIN = 3V; 500kHz
Figure 9. Efficiency vs IOUT; B_VIN = 5V; 500kHz
95
95
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
Vout = 1.5V
Vout = 1.8V
Vout = 1.5V
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Figure 10. Efficiency vs IOUT; B_VIN = 3V; 1MHz
Figure 11. Efficiency vs IOUT; B_VIN = 5V; 1MHz
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 15 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
from 1.5V to 3.3V
V
from 1.5V to 1.8V
OUT
OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Figure 12. Power Loss vs IOUT; B_VIN = 3V; 100kHz
Figure 13. Power Loss vs IOUT; B_VIN = 5V; 100kHz
1.4
1.4
1.2
V
from 1.5V to 1.8V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
OUT
V
from 1.5V to 3.3V
OUT
1.0
0.8
0.6
0.4
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Figure 14. Power Loss vs IOUT; B_VIN = 3V; 500kHz
Figure 15. Power Loss vs IOUT; B_VIN = 5V; 500kHz
1.4
1.4
V
from 1.5V to 3.3V
V
from 1.5V to 1.8V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
OUT
OUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Figure 16. Power Loss vs IOUT; B_VIN = 3V; 1MHz
Figure 17. Power Loss vs IOUT; B_VIN = 5V; 1MHz
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 16 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
1.804
1.803
1.802
1.801
1.800
1.799
1.798
1.804
1.803
1.802
1.801
1.800
1.799
1.798
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Figure 18. Buck Load Regulation; B_VIN = 3V
Figure 19. Buck Load Regulation; B_VIN = 5V
1.8025
3.2785
3.2780
3.2775
3.2770
3.2765
3.2760
3.2755
3.2750
3.2745
1.8020
1.8015
1.8010
1.8005
1.8000
1.7995
Load = 0.5A
Load = 2.5A
Load = 0.5A
Load = 2.5A
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
B_VCC = B_VIN (V)
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
B_VCC = B_VIN (V)
Figure 20. Buck Line Regulation; VOUT = 1.8V
Figure 21. Buck Line Regulation; VOUT = 3.3V
SS 500mV/Div
SS 500mV/Div
PG 2V/Div
PG 2V/Div
VOUT 1V/Div
EN 5V/Div
VOUT 1V/Div
EN 5V/Div
500µs/DIV
200µs/DIV
Figure 22. Buck Soft-Start; Load = 0.68Ω; LDO Disabled
Figure 23. Buck Soft-Start; Load = 0.68Ω; LDO Enabled
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 17 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
SS 1V/Div
SS 1V/Div
PG 2V/Div
PG 2V/Div
VOUT 1V/Div
VOUT 1V/Div
EN 5V/Div
EN 5V/Div
500µs/DIV
500µs/DIV
Figure 25. LDO Soft-Start; Load = 1.5Ω to GND; Buck
Figure 24. LDO Soft-Start; Load = 1.5Ω to GND; Buck
Enabled
Disabled
B_PG 2V/Div
B_PG 2V/Div
B_VOUT 1V/Div
B_VOUT 1V/Div
B_SS 1V/Div
EN 5V/Div
B_SS 1V/Div
EN 5V/Div
L_SS 1V/Div
L_PG 2V/Div
L_SS 1V/Div
L_PG 2V/Div
L_VOUT 1V/Div
L_VOUT 1V/Div
500µs/Div
500µs/Div
Figure 26. Buck and LDO Soft-Start; B_EN = L_EN; 0.68Ω
Load on Buck; 1.5Ω Load on LDO; FPGA Configuration
Figure 27. Buck and LDO Soft-Start; B_EN = L_EN;
Load = 0A on Buck and LDO; DDR Configuration
LX 5V/Div
Inductor Current 500mA/Div
VOUT 50mV/Div
VOUT 50mV/Div
LX 5V/Div
Inductor Current 500mA/Div
1µs/Div
1µs/Div
Figure 28. Buck Steady State Operation; Load = 0A
Figure 29. Buck Steady State Operation; Load = 3A
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 18 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
f
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
VOUT 50mV/Div
VOUT 50mV/Div
Inductor Current 1.5A/Div
Inductor Current 1.5A/Div
Load Step Current 1.5A/Div
Load Step Current 1.5A/Div
10µs/Div
10µs/Div
Figure 30. Buck Load Step ON Transient Response;
Figure 31. Buck Load Step OFF Transient Response;
VOUT = 1.8V
VOUT = 1.8V
VOUT 50mV/Div
VOUT 50mV/Div
Inductor Current 1.36A/Div
Load Step Current 1.36A/Div
Inductor Current 1.36A/Div
Load Step Current 1.36A/Div
10µs/Div
10µs/Div
Figure 32. Buck Load Step ON Transient Response;
Figure 33. Buck Load Step OFF Transient Response;
VOUT = 3.3V
VOUT = 3.3V
Inductor Current 2A/Div
Inductor Current 2A/Div
B_VOUT 1V/Div
B_PG 5V/Div
B_PG 5V/Div
B_VOUT 1V/Div
B_SS 500mV/Div
B_LX 2V/Div
B_LX 2V/Div
B_SS 500mV/Div
2µs/Div
500µs/Div
Figure 34. Buck Overcurrent Detection and Fault
Response
Figure 35. Buck Overcurrent Hiccup Operation
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 19 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
f
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
Inductor Current 2A/Div
1000
800
700
B_VOUT 1V/Div
600
500
400
B_PG 5V/Div
300
200
100
B_LX 2V/Div
B_SS 500mV/Div
500µs/Div
RT Resistor (kΩ)
Figure 37. Buck Internal Oscillator RT vs fSW
Figure 36. Buck Overcurrent Fault Recovery Response
60
40
100
80
60
40
20
60
100
80
60
40
40
20
20
20
0
0
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
-20
-40
-60
-20
-40
-60
Gain
Gain
Phase
Phase
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Frequency (Hz)
Frequency (Hz)
Figure 38. Buck Bode Plot; Load = 0A
Figure 39. Buck Bode Plot; Load = 3A
1.195
1.194
1.193
1.192
1.191
1.190
1.191
1.190
1.189
1.188
1.187
1.186
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
L_VIN Voltage (V)
L_VIN Voltage (V)
Figure 40. LDO Line Regulation; Load = 0A
Figure 41. LDO Line Regulation; Load = 1A Sourcing
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 20 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.765
0.760
0.755
0.750
0.745
0.740
L_VCC = B_VCC = 5V
L_VIN = 1.5V
L_EA+ = 0.75V
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
LDO Current (A)
LDO Current (A)
Figure 42. LDO Constant Current Limit Threshold
Figure 43. LDO Load Regulation DDR3 Configuration
0.915
0.910
0.905
0.900
1.265
1.260
1.255
1.250
L_VCC = B_VCC = 5V
L_VCC = B_VCC = 5V
L_VIN = 1.8V
0.895
L_VIN = 2.5V
1.245
L_EA+ = 1.25V
L_EA+ = 0.9V
0.890
1.240
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
LDO Current (A)
LDO Current (A)
Figure 44. LDO Load Regulation DDR2 Configuration
Figure 45. LDO Load Regulation DDR Configuration
1.84
1.83
1.82
1.23
1.22
1.21
1.20
1.81
L_VIN = 3V
1.80
L_VCC = B_VCC = 5V
L_VIN = 3V
L_EA+ = VREF
L_VCC = B_VCC = 5V
1.19
1% Resistor Divider
1.79
L_EA+ = VREF
1% Resistor Divider
1.18
1.78
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Load Current (A)
Load Current (A)
Figure 46. LDO Load Regulation Av = 2
Figure 47. LDO Load Regulation Av = 3
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 21 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
L_VOUT 50mV/Div
L_VOUT 50mV/Div
1A Sourcing
1A Sourcing
Load Current 500mA/Div
Load Current 500mA/Div
1A Sinking
1A Sinking
2µs/Div
2µs/Div
Figure 48. LDO Source-to-Sink Transient Response;
L_OUT = L_EA- = L_EA+ = 0.6V
Figure 49. LDO Source-to-Sink Transient Response;
L_OUT = L_EA- = L_EA+ = 0.75V
L_VOUT 50mV/Div
L_VOUT 50mV/Div
1A Sourcing
1.1A Sourcing
Load Current 500mA/Div
Load Current 500mA/Div
1A Sinking
1.1A Sinking
2µs/Div
2µs/Div
Figure 50. LDO Source-to-Sink Transient Response;
L_OUT = L_EA- = L_EA+ = 0.9V
Figure 51. LDO Source-to-Sink Transient Response;
L_OUT = L_EA- = L_EA+ = 1.25V
B_EN = L_EN 5V/Div
VREF 200mV/Div
L_VOUT 100mV/Div
Load Current 2A/Div
L_SS 1V/Div
B_SS 1V/Div
LDO Current 2A/Div
20µs/Div
200µs/Div
Figure 52. LDO Constant Current Limit Regulation
Transient Response
Figure 53. VREF Start-Up Timing on B_EN or L_EN Rising
Edge; 100nF capacitor on VREF
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 22 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
L_VIN = 3V
L_VIN = 3V
L_VCC = B_VCC = 5V
L_OUT = 0.9V
300mVpp AC
L_VCC = B_VCC = 5V
L_OUT = 0.9V
300mVpp AC
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Frequency (Hz)
Figure 54. LDO L_VCC PSRR Curve; 1A Source
Figure 55. LDO L_VCC PSRR Curve; 1A Sink
0
0
-10
L_VIN = 3V
L_VIN = 3V;
L_VCC = B_VCC = 5V
L_OUT = 0.9V
-20
-40
L_VCC = B_VCC = 5V
L_OUT = 0.9V
300mVpp AC
-20
-30
-40
-50
-60
-70
-80
-90
-100
300mVpp AC
-60
-80
-100
-120
1.E+01
1.E+02
1.E+03
Frequency (Hz)
1.E+04
1.E+05
1.E+01
1.E+02
1.E+03
Frequency (Hz)
1.E+04
1.E+05
Figure 56. LDO L_VIN PSRR Curve; 1A Source
Figure 57. LDO L_VIN PSRR Curve; 1A Sink
100.00
100.00
L_VIN = 1.4V
L_VIN = 1.4V
L_VCC = B_VCC = 4V
L_OUT = 1.25V
100mA Load
L_VCC = B_VCC = 4V
L_OUT = 1.25V
100mA Load
10.00
1.00
0.10
0.01
10.00
1.00
0.10
0.01
Buck Enabled
Buck Disabled
0.01
0.1
1
10
100
1000
10000 100000
0.01
0.1
1
10
100
1000
10000 100000
Frequency (Hz)
Frequency (Hz)
Figure 58. LDO Noise Spectral Density; Buck Disabled
Figure 59. LDO Noise Spectral Density; Buck Enabled
Dual Output FPGA Configuration
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 23 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
100.00
10.00
1.00
100.00
10.00
1.00
L_VIN = 1.8V
L_VIN = 1.8V
L_VCC = B_VCC = 4V
L_OUT = 0.9V
L_VCC = B_VCC = 4V
L_OUT = 1.2V
100mA Load
100mA Load
DDR Configuration
Buck V
into L_VIN
OUT
0.10
0.10
0.01
0.01
0.01
0.1
1
10
100
1000
10000
100000
0.01
0.1
1
10
100
1000
10000 100000
Frequency (Hz)
Frequency (Hz)
Figure 60. LDO Noise Spectral Density; B_OUT into
L_VIN
Figure 61. LDO Noise Spectral Density; DDR
Configuration
1.190
1.185
1.180
1.175
1.170
1.165
1.200
1.195
1.190
1.185
1.180
1.175
1.170
1.165
1.160
1.155
1.150
L_VCC = B_VCC = 5V
L_OUT = 1.2V;
L_VCC = B_VCC = 5V
L_OUT = 1.2V;
1A Sourcing
1.160
1.155
1.150
Av = 1; L_EA+ = 1.2V
1A Sourcing
Av = 2; L_EA+ = VREF
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.24
1.25
1.26
1.27
1.28
1.29
1.30
L_VIN Voltage (V)
L_VIN Voltage (V)
Figure 62. LDO Dropout Voltage; Av = 2
Figure 63. LDO Dropout Voltage; Av = 1
100
80
60
40
20
0
250
200
150
100
50
100
80
60
40
20
0
250
200
150
100
50
Gain
Phase
0
0
Gain
-20
-40
-50
-20
-40
-50
Phase
-100
1.E+07
-100
1.E+07
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Frequency (Hz)
Figure 65. LDO Bode Plot; Av = 1; Sinking 0.9A;
L_VIN = 3V; L_VOUT = 0.9V
Figure 64. LDO Bode Plot; Av = 1; Sourcing 0.9A;
L_VIN = 3V; L_OUT = 0.9V
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 24 of 46
ISL70005SEH, ISL73005SEH
3. Typical Performance Curves
Unless otherwise noted, the test platform is the ISL70005SEHEV2Z where B_PVIN = B_VCC = L_VCC = 5V; L_VIN = 3V; B_OUT = 1.8V;
SW = 1MHz; Buck CIN = 150µF tantalum + 2x1µF ceramic; Buck COUT = 150µF tantalum + 2x1µF ceramic; LOUT = 2.2µH; LDO CIN = 150µF
tantalum + 11µF ceramic; LDO COUT = 150µF tantalum +12µF ceramic; L_OUT = 1.2V; L_EA+ = VREF = 0.6V; TA = +25°C. (Continued)
f
100
80
60
40
20
0
250
200
150
100
50
100
80
60
40
20
0
250
200
150
100
50
0
0
Gain
Gain
Phase
-20
-40
-50
-100
-20
-40
-50
-100
Phase
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Frequency (Hz)
Figure 66. LDO Bode Plot; Av = 2; Sourcing 1.2A;
L_VIN = 3V; L_OUT = 1.2V
Figure 67. LDO Bode Plot; Av = 2; Sinking 1.2A;
L_VIN = 3V; L_OUT = 1.2V
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 25 of 46
ISL70005SEH, ISL73005SEH
4. Functional Description
4. Functional Description
The ISL70005SEH and ISL73005SEH are radiation hardened dual output Point-of-Load (POL) regulators
combining the high efficiency of a synchronous buck regulator with the low noise of a Low Dropout (LDO)
regulator. This device is suited for systems with 3.3V or 5V power buses and can support continuous output load
currents of 3A for the buck regulator and ±1A for the LDO.
The buck regulator uses a voltage mode control architecture and switches at a resistor adjustable frequency of
100kHz to 1MHz. Externally adjustable loop compensation allows for an optimum balance between stability and
output dynamic performance. The internal synchronous power switches are optimized for high efficiency and
excellent thermal performance.
The LDO is completely configurable independent of the switching regulator. It uses NMOS pass devices and
separate chip bias voltage (L_VCC) to drive its gate, which enables the LDO to function with very low input
voltages at the L_VIN NMOS input. Combined with low dropout performance, the LDO allows regulation with
minimal power dissipation across a wide output voltage. The LDO can sink and source up to 1A continuously
making it an ideal choice to power DDR memory.
The ISL70005SEH and ISL73005SEH offers independently on the Buck and LDO programmable soft-start and
enable functions along with power-good indicators for ease of supply rail sequencing and other housekeeping
requirements. In addition, these devices incorporate fault protection for the regulators. The protection features
include over-temperature, input Undervoltage Lockout (UVLO), output undervoltage detection, output overvoltage
detection and output overcurrent protection.
The ISL70005SEH and ISL73005SEH are available in a space saving 28 Ld ceramic dual flat-pack package or
in die form and are specified to operate across the military temperature range of T = -55°C to +125°C.
A
4.1
Synchronous Buck Converter
Buck Architecture
4.1.1
The synchronous integrated FET buck regulator uses a voltage mode control architecture with external
compensation. It is fabricated on a 0.6µm BiCMOS junction isolated process optimized for power management
applications. With this device and a handful of external components, a complete synchronous buck DC/DC
converter can be readily implemented.
4.1.2
Buck Enable Control
The B_EN pin accepts TTL/CMOS logic input levels. When the voltage on the B_EN pin exceeds its logic rising
threshold, the controller monitors the POR voltage before initiating the soft-start for the PWM regulator. When
B_EN is pulled low, the device enters a low power shutdown mode. The internal synchronous MOSFETs are held
in a high impedance state while in shutdown mode.
4.1.3
Buck Soft-Start
The Buck regulator soft-start is enabled upon rising edge of B_EN. The soft-start function uses an internal current
source and an external capacitor to create a reference ramp during start-up to minimize in-rush current to the
output capacitors. The soft-start circuit clamps the error amplifier reference voltage to the lower of voltage
between the external soft-start capacitor connected to the B_SS pin or the internal reference voltage (0.6V
typical). The soft-start capacitor is charged by an internal current source. As the soft-start capacitor is charged,
the output voltage ramps to the set point determined by the soft-start capacitor voltage and the feedback voltage.
When the voltage on the B_SS pin is equal to the internal reference voltage, the soft-start interval is complete.
When B_SS pin has charged to 1.6V (internally clamped) and with no fault conditions, the buck power-good
B_PG pin goes high impedance. The soft-start capacitor is discharged by a 3.0Ω resistor whenever POR
condition is not met or B_EN is pulled low.
The buck regulator is designed to soft-start into a pre-biased output that is less than its target regulation voltage.
During soft-start there is no switching on the B_LXx pins until the B_SS voltage crosses the B_FB voltage to
prevent discharging a pre-biased output. If the pre-bias output is above its target regulation voltage this is an
overcharged condition for the buck regulator. For a soft-start into an overcharged condition, the buck regulator
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 26 of 46
ISL70005SEH, ISL73005SEH
4. Functional Description
does not complete soft-start. When the B_SS pin voltage reaches 1.6V, the soft-start capacitor is internally
discharged to 0V and begins a new soft-start cycle with no switching on B_LXx. This condition repeats until the
pre-bias output voltage is reduced below the target regulation voltage.
4.1.4
Switching Frequency with B_RT and B_SYNC
The buck regulator PWM switching frequency is set through the internal oscillator with an adjustable range of
100kHz to 1MHz. An external termination resistor, RT, from the B_RT pin to B_GND sets the oscillator frequency.
See “Switching Frequency Selection and External Sync for Buck Regulator” on page 31 for more information on
setting the RT resistor.
The switching frequency can also be synchronized to an external clock through the B_SYNC pin. During soft-start
the clock at B_SYNC is ignored and the PWM controller uses the internal oscillator for switching until the soft-start
voltage is above the internal 600mV reference voltage where it synchronizes to B_SYNC. The synchronization
frequency range is 100kHz to 1MHz. If external synchronization is not used, tie B_SYNC to GND.
4.1.5
Buck Power-Good
The B_PG power-good indicator is an open-drain logic output. On completion of soft-start and without a fault
condition on the buck regulator, the B_PG pin is high impedance. An external pull-up resistor to B_VCC is used
for logic high indicating the buck output is operating in regulation. The recommended range for the pull-up resistor
is 10kΩ to 100kΩ. Before soft-start completes or in a fault condition, the B_PG pin is actively pulled low to indicate
buck output is not operating in regulation. To mitigate SEE, bypass the B_PG pin to B_GND with a 1nF ceramic
capacitor.
4.1.6
Buck Integrated Power MOSFETs
The buck regulator integrates two synchronous operation MOSFETs for the power stage. The high-side MOSFET
is a PMOS and the low-side MOSFET is an NMOS. The MOSFETs are optimized for low r
excellent efficiency over the 3A load current operating range.
to provide
DS(ON)
4.1.7
Buck Error Amplifier Output
The B_COMP pin is the output of the error amplifier. The voltage on B_COMP determines the duty cycle at
B_LXx. For voltage mode control, a Type III compensation network must be connected between B_FB and
B_COMP to stabilize the feedback loop. See “Buck Feedback Compensation Design” on page 36 for the design
of the Type III compensator. The B_COMP pin analog range is from 100mV to 0.4*B_VCC that correlates to the
B_LXx duty cycle from minimum on-time to minimum off-time.
4.1.8
Buck Overcurrent Limiting
The buck regulator integrates cycle-by-cycle output overcurrent limiting. Peak inductor current is sensed on the
integrated high-side PMOS FET. If the high-side switch current exceeds the overcurrent threshold (5.3A typical),
the PMOS turns off and the low-side NMOS FET is turned on for the remainder of the switching cycle. After four
consecutive detections of cycle-by-cycle current limiting, the Buck regulator enters an overcurrent fault protection
mode as described in Buck Fault Protection. The minimum response time from the high-side PMOS turn-on to
overcurrent detection is determined by the B_LX minimum on-time specified in the Electrical Specification table
on page 10. The response time from overcurrent detection to the high-side PMOS turn-off is approximately 60ns.
See Figure 35 and Figure 36.
4.1.9
Buck Fault Protection
The buck regulator integrates output overvoltage detection, output undervoltage protection, overcurrent protection
and over-temperature protection. The fault response for output overvoltage only pulls the B_PG pin low to indicate
an overvoltage condition. After recovery from an overvoltage, the B_PG pin is released. The fault response for an
undervoltage or overcurrent condition pulls the B_PG pin low and starts a hiccup mode, after which a time delay
causes the controller to start a soft-start cycle. The hiccup mode continues indefinitely until the fault condition
recovers. If the soft-start completes with no fault condition, the B_PG pin is released. The fault response for an
over-temperature condition pulls the B_PG and B_SS pins low and disables switching on B_LXx. After recovery
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 27 of 46
ISL70005SEH, ISL73005SEH
4. Functional Description
from over-temperature condition, a soft-start cycle is initiated. After a successful soft-start, the B_PG pin is
released.
The undervoltage and overvoltage fault detection is implemented by sensing the B_FB voltage and comparing it
to internal references for undervoltage and overvoltage thresholds. For the buck regulator, there are two
Undervoltage (UV) thresholds. The first UV threshold (typically 89% of regulation) only flags the B_PG pin to
indicate an undervoltage condition. The second UV threshold (typically 75% of regulation) produces a fault
response on the buck converter where it operates in hiccup mode. See Buck Hiccup Operation for a description of
Hiccup operation.
4.1.10 Buck Hiccup Operation
The buck regulator operates in hiccup mode when an output undervoltage or overcurrent condition occurs. During
these fault conditions, the B_LXx pins are tri-stated and the B_SS pin is internally discharged. The buck regulator
goes through a dummy soft-start cycle where the B_SS capacitor is charged by the internal current source but
there is no switching on B_LXx. When the B_SS capacitor is fully charged (internally clamped to 1.6V), the B_SS
pin is discharged again. The buck regulator then attempts a normal soft-start. This cycle repeats until the fault
condition is removed to allow the buck regulator to go through a successful soft-start where B_PG is released.
4.2
Low Dropout Regulator (LDO)
LDO Architecture
4.2.1
The LDO on the ISL70005SEH and ISL73005SEH is designed with NMOS pull-up and NMOS pull-down FETs
with source and sink capability of up to 1A. Separate gate bias (L_VCC) and pass FET input (L_VIN) pins allow
output voltage regulation up to L_OUT = L_VCC-1.5V and low dropout performance down to L_VIN = 0.775V.
The LDO uses separate feedback loops for voltage regulation when sourcing and sinking current. To prevent
internal shoot-through between the transition of the source and sink regulation loop, a small dead-band voltage
region disables the LDO output at the LDO output current sourcing and sinking transition. During this dead-band
voltage, both the LDO sourcing and sinking NMOS FETs are disabled. Any load current sources from or sinks into
the output capacitor, raising or lowering the output voltage until it is out of the dead-band region where the LDO
resumes voltage regulation. The dead-band voltage is precision trimmed to ±5mV around the target regulation
voltage at unity gain feedback and is amplified by the feedback gain value. For example with L_EA+ = 0.6V and
L_OUT = 1.2V, the dead-band voltage is ±10mV due to the feedback gain of 2. See Equation 1 for calculating the
dead-band voltage above and below the LDO target regulation voltage. For sourcing current, the dead-band
voltage is negative (LDO output is a dead-band voltage below target regulation voltage) and for sinking current,
the dead-band voltage is positive (LDO output is a dead-band voltage above target regulation voltage). During
transient loading conditions from sourcing current to sinking current (or from sinking current to sourcing current),
the delay time for the LDO to resume regulation after sensing it is outside the dead-band region is typically 3µs.
During this delay time, sourcing or sinking load current is provided only by the output capacitor on L_OUT. See
Figure 43 through Figure 52.
L_OUT
L_EA+
------------------
(EQ. 1)
V
= 5mV
DeadBand
4.2.2
LDO Enable Control
The L_EN pin accepts TTL/CMOS logic input levels. When the voltage on the L_EN pin exceeds its logic rising
threshold, the controller monitors the POR voltage before initiating the soft-start for the LDO. When L_EN is pulled
low, the device enters a low power shutdown mode.
4.2.3
LDO Soft-Start
The LDO regulator soft-start is enabled on the rising edge of L_EN. The soft-start circuitry for the LDO is similar to
the soft-start circuit on the buck regulator. The L_SS pin soft-start uses an internal current source and an external
capacitor to create a reference ramp during start-up to minimize in-rush current to the output capacitors. The
soft-start circuit clamps the error amplifier reference voltage to the lower of voltage between the external soft-start
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 28 of 46
ISL70005SEH, ISL73005SEH
4. Functional Description
capacitor connected to L_SS or the reference voltage connected to L_EA+. The soft-start capacitor is charged by
an internal current source. As the soft-start capacitor is charged, the output voltage ramps to the set point
determined by the soft-start capacitor voltage and the feedback voltage. When the voltage on the L_SS pin is
equal to the L_EA+ reference voltage, the soft-start interval is complete. When the L_SS pin has charged to 2.6V
(internally clamped) and with no fault conditions, the LDO power-good L_PG pin is released. The soft-start
capacitor is discharged by a 3.0Ω resistor whenever the Power-On Reset (POR) condition is not met or L_EN is
pulled low.
The LDO sources or sinks up to a limited constant current (1.65A typical) into a pre-biased output during soft-start
to charge or discharge the output capacitor to bring L_OUT to the regulation voltage set by the ramping L_SS
reference.
4.2.4
LDO Error Amplifier Inputs
The LDO has two error amplifier inputs. The L_EA- pin is the inverting feedback pin that sets the output voltage.
The L_EA+ pin is the non-inverting reference pin. The L_EA+ pin must be connected to a voltage such as the
VREF pin (0.6V typical) or to the buck output for tracking applications. The recommended analog voltage range of
L_EA+ is 0.6V to 1.27V.
4.2.5
LDO Output Overcurrent Limiting
The LDO integrates output overcurrent protection by operating in constant current limit when the current reaches
the overcurrent threshold (1.65A for sourcing or sinking, typical). In constant current limit the LDO does not
regulate output voltage. Sourcing or sinking load currents beyond the constant current limit is supported by the
output capacitor, causing the output voltage to rise or fall until the overcurrent condition recovers. There is a 18µs
typical delay time between detecting an overcurrent condition until the constant current limiting is active for both
sourcing and sinking. See Figure 42 and Figure 52.
4.2.6
LDO Power-Good
The L_PG power-good indicator is an open-drain logic output. After completion of soft-start and without a fault
condition on the LDO, the L_PG pin is high impedance. An external pull-up resistor to L_VCC is used for logic
high indicating the LDO output is operating in regulation. The recommended range for the pull-up resistor is 10kΩ
to 100kΩ. Before soft-start completes or in a fault condition, the L_PG pin is actively pulled low to indicate LDO
output is not operating in regulation. To mitigate SEE, bypass the L_PG pin to L_GND with a 1nF ceramic
capacitor.
4.2.7
LDO Fault Protection
The LDO integrates output undervoltage detection, output overvoltage detection, output overcurrent protection,
and over-temperature protection. When the LDO output current reaches the source or sink overcurrent threshold,
it operates in constant current limit with no regulation on LDO output voltage. While the LDO operates in constant
current limit but does not cross the undervoltage or overvoltage thresholds, there is no fault response on the
L_PG pin. The undervoltage and overvoltage fault detection is implemented by sensing the L_EA- voltage and
comparing it to internal references for the undervoltage and overvoltage thresholds. The fault response for an
output undervoltage or overvoltage only pulls the L_PG pin low to indicate a fault condition. After recovery from an
output undervoltage or overvoltage condition, the L_PG pin is released. The LDO integrates over-temperature
thermal shutdown. The fault response to an over-temperature condition is similar to the buck regulator. The L_SS
pin is discharged and the L_PG pin is pulled low while the L_OUT pin is high impedance. After recovery from an
over-temperature condition, a soft-start cycle is initiated. After a successful soft-start, the L_PG pin is released.
4.3
Internal Reference Voltage
The ISL70005SEH and ISL73005SEH integrate a 0.6V reference with ±1% tolerance over line, temperature, and
radiation that is precision trimmed for the buck regulator. This reference voltage is trimmed with the input offset of
buck error amplifier compensated. The reference voltage coming out to the VREF pin is prior to the buck regulator
error amplifier. Therefore, VREF includes the input offset voltage of the error amplifier that reduces the accuracy
of VREF pin to ±1.5% tolerance.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 29 of 46
ISL70005SEH, ISL73005SEH
4. Functional Description
During the first rising edge of B_EN (Buck enable) or L_EN (LDO enable), the internal reference voltage is also
enabled. When the VREF pin voltage reaches 0.564V (94% of 0.6V), soft-start begins on either the B_SS (Buck
soft-start) or L_SS (LDO soft-start) pin. Renesas recommends decoupling the VREF pin to L_GND for SEE
mitigation. The minimum recommended value is 100nF. VREF has a typical source impedance of 1.7kΩ.
Therefore, the delay from a rising edge of enable to the beginning of soft-start is determined by the RC time
constant to reach 94% of 0.6V. For a 100nF capacitor on VREF, the typical delay time is approximately 500µs.
See Figure 53 for an example of the VREF start-up time to the beginning of the soft-start delay.
4.4
Over-Temperature Detection
The over-temperature detection circuit on the ISL70005SEH and ISL73005SEH is located near the LDO output as
this is where most of the power dissipation occurs in the circuit. When an over-temperature condition is detected,
the fault response is as described in “Buck Fault Protection” on page 27 for the buck regulator and “LDO Fault
Protection” on page 29 for the LDO. The over-temperature rising threshold is typically T = 175°C with a recovery
J
hysteresis of 8°C. Power dissipation from the Buck or LDO causes a differential temperature from junction that
triggers an over-temperature condition at a lower ambient temperature.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 30 of 46
ISL70005SEH, ISL73005SEH
5. Applications Information
5. Applications Information
5.1
Power Supply Biasing
It is necessary in application to have B_VCC, L_VCC, and B_VIN biased to the same RMS DC voltage. A low
pass filter can be placed on B_VIN to B_VCC and L_VCC to provide noise filtering on the analog supplies. A 1Ω
resistor and 0.1µF capacitor on B_VCC = L_VCC to B_GND = L_GND is recommended. The L_VCC input UVLO
threshold is specified in the electrical specification table with a typical rising threshold of 2.8V. Below UVLO both
the B_LXx and L_OUT output is high impedance. B_VIN is the input to the buck synchronous power MOSFETs
and L_VIN is the input to the LDO upper NMOS FET. The recommended input voltage range of B_VCC, L_VCC,
and B_VIN is 3V to 5.5V. The recommended input voltage range of L_VIN is from 1.0V to L_VCC. There are no
power sequencing requirements for the B_VCC = L_VCC = B_VIN and L_VIN power supplies.
5.2
Switching Frequency Selection and External Sync for Buck Regulator
The internal oscillator frequency for the synchronous buck regulator is programmable by an external resistor on
the B_RT pin. Select the RT resistor based on Figure 37 and Equation 2. For external synchronization
applications using the B_SYNC pin, the recommendation is for the external synchronization frequency to be as
near as possible to the internal oscillator frequency set by RT resistor to minimize voltage transients at the buck
output during the internal to external synchronization.
54348
(EQ. 2)
--------------------------
RTk =
– 8.9
f
kHz
SW
During soft-start, the PWM controller uses its internal oscillator frequency set by the B_RT resistor value. When
B_SS voltage > 600mV the PWM controller synchronizes to the external clock on B_SYNC.
In application, the internal oscillator to external clock synchronization occurs after eight clock cycles on B_SYNC.
5.3
B_EN and L_EN Pins
The ISL70005SEH and ISL73005SEH internal band-gap is enabled by the logic high of B_EN or L_EN. After the
band-gap is enabled, soft-start begins when VREF pin is typically 94% of the nominal 600mV. The delay time for
VREF rising is typically 500µs with a 100nF capacitor on VREF. The 100nF capacitor is for SEE mitigation.
In application, the first rising edge of B_EN or L_EN includes the VREF delay time before soft-start initiates and
impacts the start-up timing between B_EN or L_EN first rising to B_PG or L_PG rising. If the band-gap is already
enabled, during the rising edge of B_EN or L_EN there is approximately 50µs delay before soft-start begins. For
buck always on applications, tie B_EN to B_VCC = L_VCC. For LDO always on applications, tie L_EN to
B_VCC = L_VCC.
See Figure 22 to Figure 27 for soft-start timing from enable to power-good indication.
5.4
Soft-Start Capacitor for Buck
Place a soft-start capacitor on B_SS pin to B_GND. A 23µA typical current source on B_SS charges the soft-start
capacitor to set the voltage ramp to the error amplifier during soft-start. The value of the soft-start capacitor
determines the time to ramp the buck output voltage into regulation (B_SS reaches 0.6V). B_SS is internally
clamped to 1.5V. When B_SS reaches the internally clamped 1.5V and with no other fault condition, the B_PG pin
is released. Use Equation 3 to determine the capacitor needed for the soft-start time to ramp the buck output
voltage into regulation. Use Equation 4 to determine the time for B_PG to go high after enabling the buck.
I
A
SS
(EQ. 3)
(EQ. 4)
---------------------
C
nF =
t ms
SS
SS
0.6V
1.5V
A
---------------------
t
ms =
C nF
PG
SS
I
SS
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 31 of 46
ISL70005SEH, ISL73005SEH
5. Applications Information
5.5
Soft-Start Capacitor for LDO
Place a soft-start capacitor on L_SS pin to L_GND. A 23µA typical current source on L_SS charges the soft-start
capacitor to set the voltage ramp to the error amplifier during soft-start. The value of the soft-start capacitor
determines the time to bring the LDO output voltage into regulation (L_SS reaches L_EA+). L_SS is internally
clamped to 2.6V. When L_SS reaches the internally clamped 2.6V and with no other fault condition, the L_PG pin
is released. Choose a soft-start capacitor based on the soft-start time using Equation 5 below. To avoid reaching
the LDO constant current limit during soft-start to charge the LDO output capacitor, choose a soft-start capacitor
using Equation 6 below. The constant current limit is 1.65A typical, 1.2A minimum. Use Equation 7 to determine
the time for L_PG to go high after enabling the LDO.
I
A
SS
---------------------
(EQ. 5)
(EQ. 6)
C
C
t
nF =
nF
t ms
SS
SS
SS
L_EA+
I
A
SS
--------------------------------------------------
C
uF
OUT
1000 I
A
CCLimit
2.6V
A
(EQ. 7)
---------------------
ms =
C nF
SS
PG
I
SS
5.6
Power-Good Indicator Pins
Use a 10kΩ or larger pull-up resistor on the B_PG and L_PG pins to B_VCC = L_VCC for power-good indication.
A 1nF capacitor on the B_PG and L_PG pin to B_GND and L_GND is recommended for SEE mitigation. B_PG
and L_PG can be connected together for a wired-OR single power-good indicator.
5.7
Independent Output Point-of-Load Application
The ISL70005SEH and ISL73005SEH can be used in a dual output Buck and LDO regulator for use in
applications such as the FPGA core and I/O supply rail. Independent enable control, soft-start, and power-good
indicator are available for the Buck and LDO (see Figure 3 on page 4).
5.8
LDO Tracking Buck for DDR Memory Application
The ISL70005SEH and ISL73005SEH can be configured for LDO tracking Buck application (see Figure 4 on
page 4).
Specifically for DDR memory applications, the 1A source and sink LDO is configured as the VTT rail regulator.
The buck configured as the VDDQ regulator can be used to bias the LDO L_VIN input to minimize power
dissipation in the LDO. The VDDQ output is divided by half with a resistor divider to set the reference voltage on
the LDO L_EA+ pin. Connect L_OUT to L_EA- for unity gain to set L_OUT = L_EA+ = VDDQ/2. For accurate
tracking, do not place any capacitance on the L_EA+ pin to L_GND. Otherwise transient voltages on the buck
regulator output are not properly tracked by the LDO output due to the RC delay formed by the resistor divider and
capacitor into the L_EA+ reference input. Use proper PCB layout to minimize noise into L_EA+ pin.
For accurate tracking during soft-start, the recommendation is to use a smaller soft-start capacitor on L_SS
compared to B_SS. This ensures that the lowest reference voltage to the error amplifier on the LDO is only set by
L_EA+, which is controlled by the ramping voltage on B_SS pin.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 32 of 46
ISL70005SEH, ISL73005SEH
6. Synchronous Buck Design Guide
6. Synchronous Buck Design Guide
6.1
Buck Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot and undershoot across the internal
MOSFETs of the synchronous buck regulator. Use small low ESR ceramic capacitors for high-frequency
decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turns on. Place the
small ceramic capacitors physically close to the MOSFETs between the drain of the upper MOSFET (B_VINx
pins) and the source of the lower MOSFET (B_PGNDx pins).
The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For
reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and
largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the
maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS
current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors may be closely approximated using Equation 8.
2
VOUT
-------------
VIN
VOUT
VIN
2
VIN – VOUT VOUT
1
(EQ. 8)
I
=
------------- x I
x 1 –
+ -------- x ------------------------------- x-------------
OUT
CINrms
MAX
12 Lxf
VIN
OSC
The recommended bulk input capacitor is a 150µF low ESR tantalum capacitor. The capacitor used for the
ISL70005SEHEV2Z evaluation platform is an AVX TPM series 16V tantalum with 30mΩ ESR. Place a 0.1µF and
10nF high frequency low ESR ceramic capacitor close to the B_VINx and B_PGNDx pins. These capacitors
provide the instantaneous current into the buck regulator during the high frequency switching transitions.
6.2
Buck Output Capacitor Selection
An output capacitor is required to filter the inductor ripple current and supply the load transient current. The
filtering requirements are a function of the switching frequency and the ripple current. The load transient
requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These
requirements are generally achieved with a combination of bulk and decoupling capacitors with careful layout.
High-frequency low ESR ceramic capacitors initially supply the transient load current and reduce the current load
slew rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the Effective
Series Resistance (ESR) and voltage rating requirements rather than actual capacitance requirements. Place
high-frequency decoupling capacitors as close to the power pins of the load as physically possible. Be careful not
to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance
components.
The shape of the output voltage waveform during a load transient that represents the worst case loading
conditions ultimately determines the number of output capacitors and their type. When this load transient is
applied to the regulator, most of the current required by the load is initially contributed by the output capacitors.
This is due to the finite amount of time required for the inductor current to slew up or down to the level of the
output current required by the load. This results in a momentary undershoot or overshoot in the output voltage. At
the initial edge of the transient undershoot or overshoot, the Equivalent Series Inductance (ESL) of each capacitor
induces a spike that adds on top of the voltage drop due to the ESR. After the initial spike, the output voltage dips
down (load step on) or peaks up (load step off) as the output capacitor sources or sinks the transient load current
until the output inductor current reaches the load current. Figure 68 on page 34 shows a typical response of the
output voltage to a transient load current.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 33 of 46
ISL70005SEH, ISL73005SEH
6. Synchronous Buck Design Guide
ΔV
PEAK
V
OUT
ΔV
ESR
ΔV
ΔV
DIP
ESL
I
OUT
I
TRAN
Figure 68. Typical Transient Response
The amplitudes of the voltage spikes caused by capacitor ESR and ESL is approximated by Equation 9:
V
V
= ESR I
(EQ. 9)
ESR
TRAN
TRAN
dI
----------------------------
= ESL
ESL
dt
where I
= Output load current transient.
TRAN
In a typical converter design, the ESR of the output capacitor bank impacts the transient response. The ESR and
the ESL determine the number output capacitors required to minimize the initial voltage spike at the output
transient response. It may be necessary to place multiple output capacitors in parallel to reduce the parasitic ESR
and ESL to achieve minimize the magnitude of the output voltage spike during a load transient response.
The ESL of the capacitor, which is an important parameter, is not usually listed in datasheets. Practically it can be
approximated using Equation 10 if an Impedance vs Frequency curve is given, where f is the frequency where
res
the lowest impedance is achieved (resonant frequency). The ESL of the capacitor becomes a concern when
designing circuits that supply power to loads with high rates of change in the current.
1
ESL = ------------------------------------------------------
(EQ. 10)
2
C2 f
res
If ΔV
and/or ΔV
PEAK
is too large for the output voltage limits, the amount of capacitance may need to be
DIP
increased. In this situation, a trade-off between output inductance and output capacitance may be necessary.
The recommended bulk output capacitor is a 150µF low ESR tantalum capacitor. The capacitor used for the
ISL70005SEHEV2Z evaluation platform is an AVX TPM series 16V tantalum with 30mΩ ESR. In addition, place
the high frequency ceramic decoupling closed to the load for optimal performance during transient loads.
6.3
Buck Output Inductor Selection
The output inductor is selected to minimize the response time of the regulator to a load transient and meet
steady-state output voltage ripple requirements. A smaller inductance value improves transient response but
increases output voltage ripple. The inductor value determines the inductor ripple current with the output voltage
ripple being a function of the ripple current. The inductor ripple current and output voltage ripple are approximated
using Equation 11 and Equation 12:
V – V
IN
------------------------------------ ---------------
V
OUT
L
OUT
(EQ. 11)
I
=
RIPPLE
f
V
SW
IN
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 34 of 46
ISL70005SEH, ISL73005SEH
(EQ. 12)
6. Synchronous Buck Design Guide
V
= I
ESR
RIPPLE
OUT_RIPPLE
where ESR is the output capacitor equivalent series resistance.
Increasing inductance reduces the ripple current and output voltage ripple; however, the regulator response time
to transient load is increased.
One of the parameters limiting the response of the regulator to a load transient is the time required to change the
inductor current. The response time is the time required to slew the inductor current from its initial level to the
transient level. During this interval the difference between the inductor current and the transient load current is
sourced from or sunk into the output capacitor. Minimizing the response time reduces the amount of transient
voltage overshoot and undershoot on the output capacitor.
The response time to a transient is different for the transient load on and off. Equation 13 gives the approximate
response time to a load step.
L I
L I
TRAN
Load On:
TRAN
Load Off:
(EQ. 13)
-------------------------------
-------------------------
t
=
t
=
RISE
FALL
V
– V
V
IN
OUT
OUT
• I
• t
• t
is the transient load current step
TRAN
RISE
FALL
is the inductor response time to a turn on load step
is the response time to a turn off load step
The worst case response time can be during either the load step on or off. Check for transient load response for
both turn-on and turn-off at minimum and maximum load current.
The recommended inductor is 2.2µH for 1MHz applications. The inductor used for the ISL70005SEHEV2Z
evaluation platform is a Coilcraft XFL4020 series 2.2µH with 21mΩ DCR.
The inductor saturation current rating is recommended to be above the peak overcurrent threshold of the
ISL70005SEH (typical 5.35A, maximum 6.0A) to ensure that inductor does not saturate operating near the
overcurrent condition. Inductor saturation along with standard tolerance over temperature and life can decrease
the inductance and increase ripple current.
6.4
Buck Output Voltage Setting
The Buck regulator output voltage is set by two feedback resistors connected from the V
B_GND. See Equation 14 for setting the buck output voltage.
to B_FB and B_FB to
OUT
R
1
(EQ. 14)
------
Buck V
= 0.6V
+ 1
OUT
R
4
where R is from Buck V
to B_FB and R is from B_FB to B_GND.
1
OUT
4
The resistor R is recommended to be in the range of 10kΩ to 30kΩ. The value of R controls the design of the
1
1
Type III Compensation network to stabilize the feedback loop (see “Buck Feedback Compensation Design” on
page 36). For Buck V = 0.6V, connect V directly to B_FB.
OUT
OUT
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 35 of 46
ISL70005SEH, ISL73005SEH
6. Synchronous Buck Design Guide
Due to the minimum Ton (325ns, maximum) and Toff times (165ns, maximum) of the ISL70005SEH and
ISL73005SEH Buck B_LXx pins and the selected switching frequency f , the buck regulator is restricted by a
SW
duty cycle limitation that bounds the upper and lower output voltage achievable. The equations for minimum and
maximum buck output voltage is calculated below on Equations 15 and 16.
V
= Min ON-Time (max) + Dead Time (max) f
(EQ. 15)
OUT_MIN
V
SW(max)
r
– I
r
– r
– I
+ R
IN_(MAX) OUT_MIN
DSON(high)
DSON(low)
OUT_MIN
DSON(low)
DCR
DCR
(EQ. 16)
V
= 1 – Min OFF-Time (max) + Dead Time (max) f
OUT_MAX
V – I
SW(max)
r
– r
– I
r
+ R
IN_(MIN) OUT_MAX
DSON(high)
DSON(low)
OUT_MAX
DSON(low)
6.5
Buck Feedback Compensation Design
The ISL70005SEH and ISL73005SEH buck regulators use voltage mode control for output voltage regulation.
Due to the double pole roll off in gain at the LC output filter resonant frequency, in voltage mode control a Type III
compensator is required to stabilize the feedback loop. The goal of the compensation network is to provide a
closed loop transfer function with the highest 0dB crossing frequency with adequate Gain and Phase margin. See
Figure 69 for the schematic of a Type III compensator. This feedback network is connected between the B_FB
and B_COMP pin. The loop compensation used on the ISL70005SEHEV2Z evaluation board is based upon the
K-Factor design to determine the pole-zero placement of the Type III compensation. The K-Factor design places
the two zeros at a square-root of K below the crossover frequency and the two poles at a square-root of K above
the crossover frequency, where the value K is determined by how much phase boost is needed.
C1
C3
C2
R3
R2
VOUT
R1
B_COMP
VREF
Figure 69. Type III Compensator
The steps to design the Type III Compensator based on K-Factor:
1. Plot the Gain-Phase Response of the Plant (Modulator and LC output filter).
2. Pick the Phase Margin desired, denoted as M. Typical phase margin range is 45° to 75°. As a good compromise
of fast transient response and good stability margin, 50°-70° degrees is a good recommended range.
3. Choose the Unity Gain Frequency (UGF) of the Type III Compensator. To ensure there is enough attenuation
of gain at the switching frequency f
the UGF should be no greater than one decade below f
.
SW
SW
4. Find the Open Loop Phase of the Plant at UGF, denoted as P.
5. Calculated the amount of Phase Boost, denoted as B, required. B = M - P - 90.
2
6. Calculate the K factor based upon the amount of Phase Boost B. K = { Tan [ (B/4) + 45° ] } .
7. Find the Open Loop Gain of the Plant at UGF. Take the reciprocal of this gain, denoted as G.
8. Use Equation 17 through Equation 21 to find the R and C values of the Type III Compensator.
R = Set by the feedback resistor for Buck output voltage regulation. R should be in the 10kΩ to 30kΩ range.
1
1
1
(EQ. 17)
-------------------------------------------------
C
=
1
2 UGF G R
1
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 36 of 46
ISL70005SEH, ISL73005SEH
(EQ. 18)
6. Synchronous Buck Design Guide
C
= C K – 1
2
1
K
(EQ. 19)
--------------------------------------
R
=
2
2 UGF C
2
R
1
K – 1
(EQ. 20)
(EQ. 21)
-----------------
R
C
=
=
3
3
1
---------------------------------------------------------
2 UGF K R
3
Type III Compensator Design Example for the ISL70005SEHEV2Z Platform:
1. The ISL70005SEHEV2Z buck regulator is set to operate at f = 1MHz with a 45.3kΩ resistor on the B_RT pin.
SW
The output inductor Lo = 2.2µH used is a Coilcraft XFL4020 with DCR = 21mΩ. The output capacitor
Co = 150µF used is an AVX TPM Series 16V tantalum with ESR = 30mΩ. The ceramic capacitors with much
lower ESR used are only a small fraction of the bulk capacitance and can be ignored. The modulator gain of
the ISL70005SEH is B_VIN / 2.315V. Plot the Open Loop Plant Gain-Phase using either a spreadsheet tool or
MathCad. This is needed for determining the gain and phase of the Plant at UGF.
2. Phase margin desired: M = 50°.
3. Compensator unity gain frequency: UGF = 30kHz.
4. For B_VIN = 5V, the open-loop plant phase at UGF is P = -125.7°.
5. Phase boost B = M - P - 90° = 50° + 125.7° - 90° = 85.7°.
2
6. K-Factor calculated as K = {Tan [(85.7°/4) + 45°]} = 5.25.
7. The open-loop gain of the plant at UGF is 0.378. The value G = 1/0.378 = 2.647.
8. Calculate the R and C values of the Type III Compensator.
a. R = 24.9kΩ
1
1
1
------------------------------------------------------
------------------------------------------------------------------------------------------
C
C
R
=
=
= 80.5pF
b.
c.
d.
; Use 82pF standard value
1
2
2
2 UGF G R
2 3.14 30000 2.647 24900
1
= C K – 1 = 80.5pF 5.25 – 1 = 342pF
; Use 330pF standard value
1
K
5.25
-----------------------------------------------------------------------
; Use 36.5kΩ standard value
= 35.5k
-------------------------------------------
=
=
2 UGF C
2 3.14 30000 342pF
2
R
24900
5.25 – 1
1
-----------------
-------------------------
; Use 5.9kΩ standard value
= 5.86k
e.
f.
R
C
=
=
=
3
K – 1
1
1
---------------------------------------------------------
2 UGF K R
----------------------------------------------------------------------------------------
=
= 395pF
; Use 390pF standard value
3
2 3.14 30000 5.25 5860
3
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 37 of 46
ISL70005SEH, ISL73005SEH
6. Synchronous Buck Design Guide
20
0
0
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
Gain (dB)
Phase (Degrees)
-160
1.E+07
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Figure 70. Calculated Open-Loop Gain-Phase
100
80
60
40
20
0
Gain (dB)
Phase (Degrees)
60
40
20
-20
-40
-60
-80
0
-20
-40
-60
-100
1.E+07
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Figure 71. Calculated K-Factor Type III Compensator
80
60
0
Gain - Measured
Gain - Calculated
Phase - Measured
Phase - Calculated
-50
40
-100
-150
-200
-250
-300
20
0
-20
-40
-60
-80
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Figure 72. Calculated vs Measured Buck Closed Loop Bode Response
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 38 of 46
ISL70005SEH, ISL73005SEH
7. LDO Design Guide
7. LDO Design Guide
7.1
LDO Input and Output Capacitor Selection
The recommended bulk output capacitor is a 150µF low ESR tantalum capacitor. The capacitor used for the
ISL70005SEHEV2Z evaluation platform is an AVX TPM series 150µF 16V tantalum with 30mΩ ESR. A low ESR
high frequency 10µF ceramic capacitor must be placed close to the L_OUT and L_PGND pins for LDO stability.
See “Example PCB Layout” on page 40 for recommended placement of the 10µF capacitor. There is no minimal
requirement for input capacitance; however, it must be sized appropriately to avoid reaching dropout voltage and
meet transient requirements during load step. For example, the ISL70005SEHEV2Z uses the same tantalum
capacitor for bulk input and output capacitance.
7.2
LDO Output Voltage Setting
The LDO output voltage is set by two feedback resistors connected from the L_OUT to L_EA- and L_EA- to
L_GND. See Equation 22 for setting the LDO output voltage.
R
F
(EQ. 22)
--------
L_OUT = L_EA+
+ 1
R
G
R is from L_VOUT to L_EA- and R is from L_EA- to L_GND. L_EA+ is the non-inverting input reference
F
G
voltage. The VREF pin can be connected to L_EA+ for a 600mV 1.5% accurate reference voltage. For unity gain
applications, connect L_OUT directly to L_EA- to set L_OUT = L_EA+.
When the LDO is used for sourcing current only applications, careful consideration must be taken in setting the
L_OUT voltage. The dead-band voltage discussed in “LDO Architecture” on page 28 introduces an offset to
Equation 22 that must be nulled out. For example, if L_EA+ = VREF = 0.6V and L_OUT is targeted for 1.2V, the
dead-band voltage is -10mV, which means when sourcing current, the LDO output voltage is 10mV below the
target regulation voltage. Set L_OUT = 1.2V + 10mV = 1.21V for Equation 22 to achieve the targeted
L_OUT = 1.2V.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 39 of 46
ISL70005SEH, ISL73005SEH
8. PCB Layout Guidelines
8. PCB Layout Guidelines
8.1
Buck Regulator PCB Layout
PCB design is critical to high frequency switching regulator performance. Careful component placement and trace
routing are necessary to reduce switching voltage spikes and minimize undesirable voltage drops. Optimize
regulator performance by reducing noise from the power ground into the analog ground by avoiding high-current
ground returns near sensitive analog ground. Bypass or ground pins accordingly to their respective IC ground pin.
See the “Pin Descriptions” on page 7 and Figure 5 on page 5 as guidance.
Place critical components as close as possible to the IC to minimize stray inductance and resistance. Place the
high-frequency ceramic decoupling capacitors for the Buck input near the B_VIN1/B_VIN2 and
B_PGND1/B_PGND2 pins as they provide the instantaneous switching input currents to the Buck Regulator.
Keep the connection between the B_LX1 and B_LX2 pins to the output inductor short and direct to avoid creating
a large switching plane on the PCB. Void the copper on adjacent layers where the switching node is formed, to
eliminate parasitic capacitance on the switching node, which impacts efficiency and causes switching spikes. To
minimize output ripple voltage, place the ceramic and tantalum output capacitors near the output inductor to form
a minimal ground loop return back to the B_PGND1/B_PGND2 pins. Place the output voltage feedback resistor
divider as close as possible to the B_FB pin of the IC. Connect the top leg of the divider to the Buck output voltage
with a Kelvin trace near the point of load to optimize load regulation performance. Connect the bottom leg of the
divider directly to the B_GND1 and B_GND2 pins. Place the Type III compensation network close to the B_COMP
and B_FB pins. Place the soft-start capacitor on the B_SS pin and the oscillator setting resistor on the B_RT pin
close to the Buck regulator. Terminate the soft-start capacitor and timing resistor near the B_GND1 and B_GND2
pins.
For applications where the switching node voltage spikes overshoot B_VINx or undershoot B_PGNDx near the
absolute maximum rating, a Schottky clamp diode across the B_LXx to B_PGNDx pins and across the B_VINx to
B_LXx pins may be needed to help suppress the switching transient to protect the power MOSFETs of the Buck
regulator.
8.2
LDO Regulator PCB Layout
Place the LDO input and output capacitors close to the L_VIN, L_OUT, and L_PGND connections. For the LDO
output capacitors, Renesas recommends placing the 10µF ceramic capacitor closest to the L_OUT and P_GND
pins to maintain LDO stability. Similar to the Buck regulator, place the LDO feedback voltage resistor dividers near
the L_EA- and L_GND pins. Connect the L_OUT connection to the feedback divider with a Kelvin trace near the
point of load for optimum load regulation performance. Place the LDO soft-start capacitor near the L_SS and
L_GND pins.
8.3
Example PCB Layout
B_SS
B_RT
Inductor
B_VIN
B_LX1
B_LX2
C
caps on
bottom layer
Buck C
OUT
IN
B_VIN
L_VIN
LDO C
IN
L_OUT
LDO C
OUT
L_SS
L_EA+
SS Cap
Figure 73. Top Layer PCB
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 40 of 46
ISL70005SEH, ISL73005SEH
9. Die and Assembly Characteristics
9. Die and Assembly Characteristics
Table 1. Die and Assembly Related Information
Die Information
Dimensions
6,504µm x 8,436µm (256 mils x 332 mils)
Thickness: 304.8µm ± 25µm (12 mils ± 1 mil)
Interface Materials
Glassivation
Type: Silicon Dioxide and silicon nitride
Thickness: 0.3µm ± 0.03µm and 1.2µm ± 0.12µm
Top Metallization
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ± 0.4µm
Backside Finish
Silicon
Process
0.6µm BiCMOS, junction isolated
Assembly Information
Substrate and Package Lid Potential
Additional Information
Worst Case Current Density
Transistor Count
Internal connection to B_GND1 and B_GND2
<2 x 105 A/cm2
7,317
Weight of Packaged Device
Lid Characteristics
2.15 grams (typical) - K28.A package
Finish: Gold
Lid Potential: Internal connection to B_GND1 and B_GND2
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 41 of 46
ISL70005SEH, ISL73005SEH
10. Metalization Mask Layout
10. Metalization Mask Layout
B_VIN2
B_LX2
B_RT
B_VCC
B_PGND
B_SYNC
B_LX1
B_VIN1
TEST
B_GND1
B_GND2
VREF
L_VIN
L_VIN
B_EN
L_EN
L_OUT
L_OUT
Origin of Coordinate Table
Table 2. Layout X-Y Coordinates (Centroid of bond pad)
X Coordinate
Y Coordinate Pad X Dimension Pad Y Dimension
Bond Wire Diameter
(0.001”)
Pad Name
L_EN
Pad Number
(µm)
(µm)
(µm)
125
125
125
125
125
125
125
(µm)
125
125
125
320
320
125
320
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
B_EN
776
VREF
1,628
2,528
3,530
4,621
5,364
B_GND2
B_GND1
B_SYNC
B_VCC
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 42 of 46
ISL70005SEH, ISL73005SEH
10. Metalization Mask Layout
Table 2. Layout X-Y Coordinates (Centroid of bond pad) (Continued)
X Coordinate
(µm)
Y Coordinate Pad X Dimension Pad Y Dimension
(µm)
Bond Wire Diameter
Pad Name
B_RT
Pad Number
(µm)
6,268
6,956
6,956
6,956
6,956
6,956
6,935
6,016
4,831
3,646
2,727
1,862
957
(µm)
125
125
125
125
125
125
508
508
254
508
508
125
260
260
254
254
125
125
125
125
125
125
125
125
125
320
125
(0.001”)
1.5
1.5
1.5
1.5
1.5
1.5
3
8
0
125
125
125
125
125
125
254
254
894
254
254
125
254
254
254
254
125
125
125
125
125
125
125
125
125
125
125
B_COMP
B_FB
9
425
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1,106
1,931
2,644
3,183
5,057
5,238
5,242
5,238
5,238
5,744
5,254
4,001
5,257
4,024
4,820
5,040
5,260
2,986
3,334
3,685
2,417
1,838
1,249
519
B_SS
L_PG
B_PG
B_VIN2
B_LX2
B_PGND
B_LX1
B_VIN1
TEST
3
3
3
3
1.5
3
L_VIN
L_VIN
593
3
L_OUT
L_OUT
L_PGND
L_PGND
L_PGND
L_GND
L_GND
L_GND
L_EA-
81
3
-283
-720
-720
-720
-720
-720
-720
-720
-720
-720
-720
-720
3
3
3
3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
L_EA+
L_SS
L_VCC
L_VCC
921
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 43 of 46
ISL70005SEH, ISL73005SEH
11. Revision History
11. Revision History
Rev.
Date
Description
1.01
Jan.8.20
Fixed UVLO pin association from B_VCC to L_VCC in electrical spec table. Moved to appropriate section.
Updated Power Supply Biasing section on page 31.
Updated the B_COMP output voltage range in the Buck Error Amplifier Output section on page 27.
1.00
Dec.11.19
initial release
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 44 of 46
ISL70005SEH, ISL73005SEH
12. Package Outline Drawing
For the most recent package outline drawing, see K28.A.
12. Package Outline Drawing
K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
28 lead ceramic metal seal flatpack package
A
A
e
INCHES
MIN
MILLIMETERS
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.740
0.520
0.550
-
MIN
1.14
MAX
2.92
0.56
0.48
0.23
0.15
18.80
13.21
13.97
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-A-
-B-
0.38
0.38
0.10
0.10
-
-
b1
c
-
S1
-
b
c1
D
-
E1
3
0.004
Q
H
A - B
D
S
0.036
M
H
A - B
S
C
D
S
M
S
E
0.460
-
11.68
-
-
E
E1
E2
E3
e
3
-D-
A
0.180
0.030
4.57
0.76
-
-H-
-C-
-
-
7
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
-
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.250
0.026
0.00
-
0.015
0.370
0.045
-
0.20
6.35
0.66
0.00
-
0.38
9.40
1.14
-
2
L
-
BASE
METAL
Q
S1
M
N
8
(c)
6
b1
0.0015
0.04
-
M
M
(b)
28
28
-
SECTION A-A
Rev. 0 5/18/94
Notes:
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark. Alternately, a tab
(dimension k) may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the
limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum
limits of lead dimensions b and c or M shall be measured at the
centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric
materials shall be molded to the bottom of the package to cover
the leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when
solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
R34DS0008EU0101 Rev.1.01
Jan.8.20
Page 45 of 46
1RWLFH
ꢃꢅ 'HVFULSWLRQVꢀRIꢀFLUFXLWVꢆꢀVRIWZDUHꢀDQGꢀRWKHUꢀUHODWHGꢀLQIRUPDWLRQꢀLQꢀWKLVꢀGRFXPHQWꢀDUHꢀSURYLGHGꢀRQO\ꢀWRꢀLOOXVWUDWHꢀWKHꢀRSHUDWLRQꢀRIꢀVHPLFRQGXFWRUꢀSURGXFWVꢀ
DQGꢀDSSOLFDWLRQꢀH[DPSOHVꢅꢀ<RXꢀDUHꢀIXOO\ꢀUHVSRQVLEOHꢀIRUꢀWKHꢀLQFRUSRUDWLRQꢀRUꢀDQ\ꢀRWKHUꢀXVHꢀRIꢀWKHꢀFLUFXLWVꢆꢀVRIWZDUHꢆꢀDQGꢀLQIRUPDWLRQꢀLQꢀWKHꢀGHVLJQꢀRIꢀ\RXUꢀ
SURGXFWꢀRUꢀV\VWHPꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀDQGꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ
WKHVHꢀFLUFXLWVꢆꢀVRIWZDUHꢆꢀRUꢀLQIRUPDWLRQꢅ
ꢁꢅ 5HQHVDVꢀ(OHFWURQLFVꢀKHUHE\ꢀH[SUHVVO\ꢀGLVFODLPVꢀDQ\ꢀZDUUDQWLHVꢀDJDLQVWꢀDQGꢀOLDELOLW\ꢀIRUꢀLQIULQJHPHQWꢀRUꢀDQ\ꢀRWKHUꢀFODLPVꢀLQYROYLQJꢀSDWHQWVꢆꢀFRS\ULJKWVꢆꢀRUꢀ
RWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀWKLUGꢀSDUWLHVꢆꢀE\ꢀRUꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRUꢀWHFKQLFDOꢀLQIRUPDWLRQꢀGHVFULEHGꢀLQꢀWKLVꢀ
GRFXPHQWꢆꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢆꢀWKHꢀSURGXFWꢀGDWDꢆꢀGUDZLQJVꢆꢀFKDUWVꢆꢀSURJUDPVꢆꢀDOJRULWKPVꢆꢀDQGꢀDSSOLFDWLRQꢀH[DPSOHVꢅꢀ
ꢇꢅ 1RꢀOLFHQVHꢆꢀH[SUHVVꢆꢀLPSOLHGꢀRUꢀRWKHUZLVHꢆꢀLVꢀJUDQWHGꢀKHUHE\ꢀXQGHUꢀDQ\ꢀSDWHQWVꢆꢀFRS\ULJKWVꢀRUꢀRWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀRUꢀ
RWKHUVꢅ
ꢈꢅ <RXꢀVKDOOꢀQRWꢀDOWHUꢆꢀPRGLI\ꢆꢀFRS\ꢆꢀRUꢀUHYHUVHꢀHQJLQHHUꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢆꢀZKHWKHUꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀ
DQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀRUꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀVXFKꢀDOWHUDWLRQꢆꢀPRGLILFDWLRQꢆꢀFRS\LQJꢀRUꢀUHYHUVHꢀHQJLQHHULQJꢅ
ꢉꢅ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀFODVVLILHGꢀDFFRUGLQJꢀWRꢀWKHꢀIROORZLQJꢀWZRꢀTXDOLW\ꢀJUDGHVꢊꢀꢋ6WDQGDUGꢋꢀDQGꢀꢋ+LJKꢀ4XDOLW\ꢋꢅꢀ7KHꢀLQWHQGHGꢀDSSOLFDWLRQVꢀIRUꢀ
HDFKꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀGHSHQGVꢀRQꢀWKHꢀSURGXFWꢌVꢀTXDOLW\ꢀJUDGHꢆꢀDVꢀLQGLFDWHGꢀEHORZꢅ
ꢋ6WDQGDUGꢋꢊ
&RPSXWHUVꢍꢀRIILFHꢀHTXLSPHQWꢍꢀFRPPXQLFDWLRQVꢀHTXLSPHQWꢍꢀWHVWꢀDQGꢀPHDVXUHPHQWꢀHTXLSPHQWꢍꢀDXGLRꢀDQGꢀYLVXDOꢀHTXLSPHQWꢍꢀKRPHꢀ
HOHFWURQLFꢀDSSOLDQFHVꢍꢀPDFKLQHꢀWRROVꢍꢀSHUVRQDOꢀHOHFWURQLFꢀHTXLSPHQWꢍꢀLQGXVWULDOꢀURERWVꢍꢀHWFꢅ
ꢋ+LJKꢀ4XDOLW\ꢋꢊ 7UDQVSRUWDWLRQꢀHTXLSPHQWꢀꢎDXWRPRELOHVꢆꢀWUDLQVꢆꢀVKLSVꢆꢀHWFꢅꢏꢍꢀWUDIILFꢀFRQWUROꢀꢎWUDIILFꢀOLJKWVꢏꢍꢀODUJHꢐVFDOHꢀFRPPXQLFDWLRQꢀHTXLSPHQWꢍꢀNH\ꢀ
ILQDQFLDOꢀWHUPLQDOꢀV\VWHPVꢍꢀVDIHW\ꢀFRQWUROꢀHTXLSPHQWꢍꢀHWFꢅ
8QOHVVꢀH[SUHVVO\ꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀSURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGRFXPHQWꢆꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀQRWꢀLQWHQGHGꢀRUꢀDXWKRUL]HGꢀIRUꢀXVHꢀLQꢀSURGXFWVꢀRUꢀV\VWHPVꢀWKDWꢀPD\ꢀSRVHꢀDꢀGLUHFWꢀWKUHDWꢀWRꢀ
KXPDQꢀOLIHꢀRUꢀERGLO\ꢀLQMXU\ꢀꢎDUWLILFLDOꢀOLIHꢀVXSSRUWꢀGHYLFHVꢀRUꢀV\VWHPVꢍꢀVXUJLFDOꢀLPSODQWDWLRQVꢍꢀHWFꢅꢏꢆꢀRUꢀPD\ꢀFDXVHꢀVHULRXVꢀSURSHUW\ꢀGDPDJHꢀꢎVSDFHꢀV\VWHPꢍꢀ
XQGHUVHDꢀUHSHDWHUVꢍꢀQXFOHDUꢀSRZHUꢀFRQWUROꢀV\VWHPVꢍꢀDLUFUDIWꢀFRQWUROꢀV\VWHPVꢍꢀNH\ꢀSODQWꢀV\VWHPVꢍꢀPLOLWDU\ꢀHTXLSPHQWꢍꢀHWFꢅꢏꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀ
DQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀGDPDJHVꢀRUꢀORVVHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀDQ\ꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀWKDWꢀLVꢀ
LQFRQVLVWHQWꢀZLWKꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢆꢀXVHUꢌVꢀPDQXDOꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢅ
ꢑꢅ :KHQꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀUHIHUꢀWRꢀWKHꢀODWHVWꢀSURGXFWꢀLQIRUPDWLRQꢀꢎGDWDꢀVKHHWVꢆꢀXVHUꢌVꢀPDQXDOVꢆꢀDSSOLFDWLRQꢀQRWHVꢆꢀꢋ*HQHUDOꢀ1RWHVꢀIRUꢀ
+DQGOLQJꢀDQGꢀ8VLQJꢀ6HPLFRQGXFWRUꢀ'HYLFHVꢋꢀLQꢀWKHꢀUHOLDELOLW\ꢀKDQGERRNꢆꢀHWFꢅꢏꢆꢀDQGꢀHQVXUHꢀWKDWꢀXVDJHꢀFRQGLWLRQVꢀDUHꢀZLWKLQꢀWKHꢀUDQJHVꢀVSHFLILHGꢀE\ꢀ
5HQHVDVꢀ(OHFWURQLFVꢀZLWKꢀUHVSHFWꢀWRꢀPD[LPXPꢀUDWLQJVꢆꢀRSHUDWLQJꢀSRZHUꢀVXSSO\ꢀYROWDJHꢀUDQJHꢆꢀKHDWꢀGLVVLSDWLRQꢀFKDUDFWHULVWLFVꢆꢀLQVWDOODWLRQꢆꢀHWFꢅꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀPDOIXQFWLRQVꢆꢀIDLOXUHꢀRUꢀDFFLGHQWꢀDULVLQJꢀRXWꢀRIꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRXWVLGHꢀRIꢀVXFKꢀ
VSHFLILHGꢀUDQJHVꢅ
ꢒꢅ $OWKRXJKꢀ5HQHVDVꢀ(OHFWURQLFVꢀHQGHDYRUVꢀWRꢀLPSURYHꢀWKHꢀTXDOLW\ꢀDQGꢀUHOLDELOLW\ꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀVHPLFRQGXFWRUꢀSURGXFWVꢀKDYHꢀVSHFLILFꢀ
FKDUDFWHULVWLFVꢆꢀVXFKꢀDVꢀWKHꢀRFFXUUHQFHꢀRIꢀIDLOXUHꢀDWꢀDꢀFHUWDLQꢀUDWHꢀDQGꢀPDOIXQFWLRQVꢀXQGHUꢀFHUWDLQꢀXVHꢀFRQGLWLRQVꢅꢀ8QOHVVꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀ
SURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢆꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀ
DUHꢀQRWꢀVXEMHFWꢀWRꢀUDGLDWLRQꢀUHVLVWDQFHꢀGHVLJQꢅꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀLPSOHPHQWLQJꢀVDIHW\ꢀPHDVXUHVꢀWRꢀJXDUGꢀDJDLQVWꢀWKHꢀSRVVLELOLW\ꢀRIꢀERGLO\ꢀLQMXU\ꢆꢀ
LQMXU\ꢀRUꢀGDPDJHꢀFDXVHGꢀE\ꢀILUHꢆꢀDQGꢓRUꢀGDQJHUꢀWRꢀWKHꢀSXEOLFꢀLQꢀWKHꢀHYHQWꢀRIꢀDꢀIDLOXUHꢀRUꢀPDOIXQFWLRQꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀVXFKꢀDVꢀVDIHW\ꢀ
GHVLJQꢀIRUꢀKDUGZDUHꢀDQGꢀVRIWZDUHꢆꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢀUHGXQGDQF\ꢆꢀILUHꢀFRQWUROꢀDQGꢀPDOIXQFWLRQꢀSUHYHQWLRQꢆꢀDSSURSULDWHꢀWUHDWPHQWꢀIRUꢀDJLQJꢀ
GHJUDGDWLRQꢀRUꢀDQ\ꢀRWKHUꢀDSSURSULDWHꢀPHDVXUHVꢅꢀ%HFDXVHꢀWKHꢀHYDOXDWLRQꢀRIꢀPLFURFRPSXWHUꢀVRIWZDUHꢀDORQHꢀLVꢀYHU\ꢀGLIILFXOWꢀDQGꢀLPSUDFWLFDOꢆꢀ\RXꢀDUHꢀ
UHVSRQVLEOHꢀIRUꢀHYDOXDWLQJꢀWKHꢀVDIHW\ꢀRIꢀWKHꢀILQDOꢀSURGXFWVꢀRUꢀV\VWHPVꢀPDQXIDFWXUHGꢀE\ꢀ\RXꢅ
ꢔꢅ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀIRUꢀGHWDLOVꢀDVꢀWRꢀHQYLURQPHQWDOꢀPDWWHUVꢀVXFKꢀDVꢀWKHꢀHQYLURQPHQWDOꢀFRPSDWLELOLW\ꢀRIꢀHDFKꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWꢅꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀFDUHIXOO\ꢀDQGꢀVXIILFLHQWO\ꢀLQYHVWLJDWLQJꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢀWKDWꢀUHJXODWHꢀWKHꢀLQFOXVLRQꢀRUꢀXVHꢀRIꢀ
FRQWUROOHGꢀVXEVWDQFHVꢆꢀLQFOXGLQJꢀZLWKRXWꢀOLPLWDWLRQꢆꢀWKHꢀ(8ꢀ5R+6ꢀ'LUHFWLYHꢆꢀDQGꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀLQꢀFRPSOLDQFHꢀZLWKꢀDOOꢀWKHVHꢀ
DSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀGDPDJHVꢀRUꢀORVVHVꢀRFFXUULQJꢀDVꢀDꢀUHVXOWꢀRIꢀ\RXUꢀQRQFRPSOLDQFHꢀ
ZLWKꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢅ
ꢄꢅ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDQGꢀWHFKQRORJLHVꢀVKDOOꢀQRWꢀEHꢀXVHGꢀIRUꢀRUꢀLQFRUSRUDWHGꢀLQWRꢀDQ\ꢀSURGXFWVꢀRUꢀV\VWHPVꢀZKRVHꢀPDQXIDFWXUHꢆꢀXVHꢆꢀRUꢀVDOHꢀLVꢀ
SURKLELWHGꢀXQGHUꢀDQ\ꢀDSSOLFDEOHꢀGRPHVWLFꢀRUꢀIRUHLJQꢀODZVꢀRUꢀUHJXODWLRQVꢅꢀ<RXꢀVKDOOꢀFRPSO\ꢀZLWKꢀDQ\ꢀDSSOLFDEOHꢀH[SRUWꢀFRQWUROꢀODZVꢀDQGꢀUHJXODWLRQVꢀ
SURPXOJDWHGꢀDQGꢀDGPLQLVWHUHGꢀE\ꢀWKHꢀJRYHUQPHQWVꢀRIꢀDQ\ꢀFRXQWULHVꢀDVVHUWLQJꢀMXULVGLFWLRQꢀRYHUꢀWKHꢀSDUWLHVꢀRUꢀWUDQVDFWLRQVꢅ
ꢃꢂꢅ ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀEX\HUꢀRUꢀGLVWULEXWRUꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀRUꢀDQ\ꢀRWKHUꢀSDUW\ꢀZKRꢀGLVWULEXWHVꢆꢀGLVSRVHVꢀRIꢆꢀRUꢀRWKHUZLVHꢀVHOOVꢀRUꢀ
WUDQVIHUVꢀWKHꢀSURGXFWꢀWRꢀDꢀWKLUGꢀSDUW\ꢆꢀWRꢀQRWLI\ꢀVXFKꢀWKLUGꢀSDUW\ꢀLQꢀDGYDQFHꢀRIꢀWKHꢀFRQWHQWVꢀDQGꢀFRQGLWLRQVꢀVHWꢀIRUWKꢀLQꢀWKLVꢀGRFXPHQWꢅ
ꢃꢃꢅ 7KLVꢀGRFXPHQWꢀVKDOOꢀQRWꢀEHꢀUHSULQWHGꢆꢀUHSURGXFHGꢀRUꢀGXSOLFDWHGꢀLQꢀDQ\ꢀIRUPꢆꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢆꢀZLWKRXWꢀSULRUꢀZULWWHQꢀFRQVHQWꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢅ
ꢃꢁꢅ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀLIꢀ\RXꢀKDYHꢀDQ\ꢀTXHVWLRQVꢀUHJDUGLQJꢀWKHꢀLQIRUPDWLRQꢀFRQWDLQHGꢀLQꢀWKLVꢀGRFXPHQWꢀRUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWVꢅ
ꢎ1RWHꢃꢏ ꢋ5HQHVDVꢀ(OHFWURQLFVꢋꢀDVꢀXVHGꢀLQꢀWKLVꢀGRFXPHQWꢀPHDQVꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢀDQGꢀDOVRꢀLQFOXGHVꢀLWVꢀGLUHFWO\ꢀRUꢀLQGLUHFWO\ꢀFRQWUROOHGꢀ
VXEVLGLDULHVꢅ
ꢎ1RWHꢁꢏ ꢋ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢎVꢏꢋꢀPHDQVꢀDQ\ꢀSURGXFWꢀGHYHORSHGꢀRUꢀPDQXIDFWXUHGꢀE\ꢀRUꢀIRUꢀ5HQHVDVꢀ(OHFWURQLFVꢅ
ꢎ5HYꢅꢈꢅꢂꢐꢃꢀꢀ1RYHPEHUꢀꢁꢂꢃꢒꢏ
Corporate Headquarters
ContactInformation
TOYOSU FORESIA, 3-2-24 Toyosu,
For further information on a product, technology, the most up-to-date
Koto-ku, Tokyo 135-0061, Japan
version of a document, or your nearest sales office, please visit:
www.renesas.com
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas Electronics
Corporation. All trademarks and registered trademarks are the property
of their respective owners.
ꢀꢁꢂꢃꢄꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢅꢀ$OOꢀULJKWVꢀUHVHUYHGꢅ
相关型号：
ISL70218SEH
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SEHF/PROTO
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SEHX/SAMPLE
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SRH
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SRHF
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SRHMEVAL1Z
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SRHMF
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
ISL70218SRHMF
DUAL OP-AMP, 3.2MHz BAND WIDTH, CDFP10, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, FLAT PACK-10
RENESAS
ISL70218SRHMX
Rad Hard Dual 36V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers
INTERSIL
©2020 ICPDF网 联系我们和版权申明