ISL80101IR50Z-T7 [RENESAS]
FIXED POSITIVE LDO REGULATOR;
| 型号： | ISL80101IR50Z-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | FIXED POSITIVE LDO REGULATOR 输出元件 调节器 |
| 文件： | 总12页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
High Performance 1A LDO
ISL80101
Features
The ISL80101 is a low voltage, high current, single output LDO
specified at 1A output current. This LDO operates from input
voltages of 2.2V to 6V. Fixed output voltage options are
available in 1.8V, 2.5V, 3.3V and 5.0V versions. Other custom
voltage options are available upon request. For the adjustable
output version of the ISL80101, please refer to the
ISL80101-ADJ datasheet.
• ±1.8% V
accuracy guaranteed over line, load and
T = -40°C to +125°C
OUT
J
• Very low 130mV dropout voltage at V
• Very fast transient response
• Programmable soft-starting
• Power-good output
= 2.5V
OUT
A submicron BiCMOS process is utilized for this product family
to deliver the best-in-class analog performance and overall
value. This CMOS LDO consumes significantly lower quiescent
current as a function of load compared to bipolar LDOs, which
translates into higher efficiency and packages with smaller
footprints. State-of-the-art internal compensation achieves a
very fast load transient response. An external capacitor on the
soft-start pin provides an adjustable soft-starting ramp. The
ENABLE feature allows the part to be placed into a low
quiescent current shutdown mode. A power-good logic output
signals a fault condition.
• Excellent 65dB PSRR
• Current limit protection
• Thermal shutdown function
• Available in a 10 Ld DFN package
• Pb-free (RoHS compliant)
Applications
• DSP, FPGA and µP core power supplies
• Noise-sensitive instrumentation systems
Table 1 shows the differences between the ISL80101 and
others in its family:
• Post regulation of switched mode power supplies
• Industrial systems
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
• Medical equipment
PROGRAMMABLE
I
ADJ or FIXED
LIMIT
• Telecommunications and networking equipment
• Servers
PART NUMBER
ISL80101-ADJ
ISL80101
I
(DEFAULT)
V
LIMIT
No
OUT
1.75A
ADJ
• Hard disk drives (HD/HDD)
No
1.75A
1.8V, 2.5V,
3.3V, 5.0V
Related Literature
• See AN1592, “ISL80101 High Performance 1A LDO
Evaluation Board User Guide”
ISL80101A
ISL80121-5
Yes
Yes
1.62A
0.75A
ADJ
5.0V
5.4V ± 10%
10µF
5.0V ± 1.8%
10µF
1
2
10
9
140
120
100
80
V
V
V
IN
OUT
V
IN
OUT
C
C
IN
OUT
3
4
10k
R
100k
SENSE
3
R
PG
ISL80101
60
7
6
ENABLE PG
40
V
= 2.5V
20
0
OUT
SS
0.01µF
GND
C
SS
5
0
0.2
0.4
0.6
0.8
1.0
OUTPUT CURRENT (A)
FIGURE 2. DROPOUT vs LOAD CURRENT
FIGURE 1. TYPICAL APPLICATION CIRCUIT
September 25, 2015
FN6931.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL80101
Block Diagram
VIN
EN
CONTROL
LOGIC
FET DRIVER
WITH CURRENT
LIMIT
-
EA
+
REFERENCE
+
SOFT-START
THERMAL
SENSOR
VOUT
SS
PG
+
-
SENSE
PG
GND
Ordering Information
PART NUMBER
(Notes 1, 3, 4)
V
VOLTAGE
PACKAGE
(RoHS Compliant)
OUT
(Note 2)
PART MARKING
DZEB
TEMP RANGE (°C)
-40 to +125
PKG DWG. #
ISL80101IR18Z
1.8V
2.5V
3.3V
5.0V
10 Ld 3x3 DFN
L10.3x3
L10.3x3
L10.3x3
L10.3x3
ISL80101IR25Z
ISL80101IR33Z
ISL80101IR50Z
ISL80101EVAL2Z
NOTES:
DZFB
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
DZGB
-40 to +125
DZHB
-40 to +125
Evaluation Board
1. Add “-T*” for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101. For more information on MSL please see Technical Brief
TB363.
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ISL80101
Pin Configurations
ISL80101
(10 LD 3x3 DFN)
TOP VIEW
V
V
V
V
1
2
3
4
5
10
9
OUT
OUT
IN
IN
SENSE
PG
NC
8
EPAD
7
ENABLE
SS
GND
6
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
V
Regulated output voltage. A minimum 10µF X5R/X7R output capacitor is required for stability. See “External
Capacitor Requirements” on page 8 for more details.
OUT
3
4
SENSE
PG
Sense is the LDO's output feedback, providing a remote voltage sensing.
This is an open-drain logic output used to indicate the status of the output voltage. Logic low indicates V
in regulation. This pin must be grounded if not used.
is not
OUT
5
6
GND
SS
Ground
External capacitor on this pin adjusts startup ramp and controls in-rush current.
7
ENABLE
NC
V
independent chip enable. TTL and CMOS compatible.
IN
8
No connection; Leave floating.
9, 10
V
Input supply; A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External
Capacitor Requirements” on page 8 for more details.
IN
-
EPAD
EPAD at ground potential; It is recommended to solder the EPAD to the ground plane.
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ISL80101
Absolute Maximum Ratings
Thermal Information
V
V
Relative to GND (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
10 Ld DFN Package (Notes 6, 7) . . . . . . . .
JA (°C/W)
48
JC (°C/W)
IN
OUT
7
PG, ENABLE, SENSE, SS
Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22 A115C) . . . . . . . . . . . . . . . . . 250V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD78C, Class 2, Level A) . . . . ±100mA at +125°C
Recommended Operating Conditions (Notes 8, 9)
Junction Temperature Range (T ) (Note 8) . . . . . . . . . . . .-40°C to +125°C
J
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
IN
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
OUT
PG, ENABLE, SENSE, SS relative to GND . . . . . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
7. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
8. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
9. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, V
+ 0.4V, < V < 6V, T = +25°C. Applications must follow thermal guidelines
IN
OUT
J
of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379. Boldface
limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DC CHARACTERISTICS
SYMBOL
TEST CONDITIONS
(Note 10)
TYP
(Note 10) UNITS
DC Output Voltage Accuracy
DC Input Line Regulation
V
0A < I
< 1A
-1.8
-1
1.8
1
%
%
OUT
LOAD
LOAD
(V
OUT
low line-
high
V
OUT
line)/V
low
OUT
line
DC Output Load Regulation
Ground Pin Current
(V
OUT
no load- 0A < I
high
< 1A, All voltage options
-1
1
%
V
OUT
load)/V
no
OUT
load
I
I
I
= 0A
= 1A
3
5
5
7
mA
mA
µA
mV
A
Q
LOAD
LOAD
Ground Pin Current in Shutdown
Dropout Voltage (Note 11)
I
ENABLE Pin = 0.2V, V = 6V
IN
0.2
130
1.75
160
30
12
212
SHDN
V
I
= 1A, V = 2.5V
OUT
DO
LOAD
Output Short-circuit Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
AC CHARACTERISTICS
OCP
TSD
V
OUT
= 0V
°C
°C
TSDn
Input Supply Ripple Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V = 2.2V
IN
58
65
53
dB
dB
f = 120Hz, I
= 1A; V = 2.2V
IN
LOAD
Output Noise Voltage
I
= 1A, BW = 100Hz < f < 100kHz, V = 2.2V,
IN
µV
RMS
LOAD
V
= 1.8V
OUT
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ISL80101
Electrical Specifications Unless otherwise noted, V
+ 0.4V, < V < 6V, T = +25°C. Applications must follow thermal guidelines
J
IN
OUT
of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379. Boldface
limits apply across the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
SYMBOL
TEST CONDITIONS
(Note 10)
TYP
(Note 10) UNITS
0.5
10
0.8
80
1
V
Hysteresis
200
mV
µs
ENABLE Pin Turn-on Delay
ENABLE Pin Leakage Current
SOFT-START CHARACTERISTICS
SS Pin Currents (Note 12)
C
= 10µF, I
= 1A
LOAD
100
OUT
V
= 6V, ENABLE = 2.8V
1
µA
IN
IPD
V
= 3.5V, ENABLE = 0V, SS = 1V
0.5
1
1.3
mA
µA
IN
ICHG
-3.3
-2
-0.8
PG PIN CHARACTERISTICS
V
V
PG Flag Threshold
PG Flag Hysteresis
75
85
4
92
%V
OUT
OUT
%
OUT
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
V
V
= 3V, I
= 500µA
= 6V, PG = 6V
100
1
mV
µA
IN
SINK
IN
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
11. Dropout is defined as the difference in supply V and V
IN OUT
when the output is below its nominal regulation.
12. I is the internal pull-down current that discharges the external SS capacitor on disable. I
is the current from the SS pin that charges the external
PD
CHG
SS capacitor during start-up.
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ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A.
IN
OUT
IN
OUT J L
200
1.8
1.2
V
= 2.5V
OUT
180
160
140
120
I
= 1.0A
OUT
0.6
0
100
0
I
= 0.5A
= 0.1A
OUT
80
60
40
20
-0.6
-1.2
-1.8
I
OUT
-50
-25
0
25
50
75
100
125
150
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 3. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 4. V
OUT
vs TEMPERATURE
1.8
1.2
0.6
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+25°C
+125°C
+25°C
-40°C
-40°C
-0.6
-1.2
-1.8
+125°C
0
1
2
3
4
5
6
0.25
0
0.50
OUTPUT CURRENT (A)
0.75
1.00
SUPPLY VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 6. OUTPUT VOLTAGE vs OUTPUT CURRENT
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
+25°C
+125°C
-40°C
0
0.2
0.4
0.6
0.8
1.0
2
3
4
5
6
INPUT VOLTAGE (V)
LOAD CURRENT (A)
FIGURE 7. GROUND CURRENT vs LOAD CURRENT
FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE
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ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A. (Continued)
IN
OUT
IN
OUT J L
VOLTAGE RAILS AT 50mV/DIV
VOLTAGE RAILS AT 50mV/DIV
V
= 3.7V, V
= 2.9V, V
= 3.3V
= 2.5V
IN
OUT
OUT
OUT
V
IN
V
= 5.4V, V = 5.0V
OUT
IN
V
= 2.5V, V
= 1.8V
= 1A
IN
I
= 500mA
OUT
I
OUT
I
= 10mA
OUT
I
= 1mA
OUT
TIME (20µs/DIV)
di/dt = 4A/µs
TIME (50µs/DIV)
FIGURE 9A.
FIGURE 9B.
FIGURE 9. LOAD TRANSIENT RESPONSE
3.5
2.5
2.0
1.5
1.0
0.5
0
ENABLE
(2V/DIV)
V
= 6V
IN
VOUT (1V/DIV)
V
= 2.2V
IN
SS (1V/DIV)
PG (1V/DIV)
(500µs/DIV)
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 10. CURRENT LIMIT vs TEMPERATURE (V
= 0V)
FIGURE 11. ENABLE START-UP (C = 2.2nF)
SS
OUT
90
80
70
60
50
40
30
20
10
0
90
C
= 10µF
OUT
C
80
500mA
= 100µF
OUT
70
60
50
40
30
20
10
0
1A
0mA
100mA
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 13. PSRR vs FREQUENCY FOR VARIOUS OUTPUT
CAPACITORS (I = 100mA)
FIGURE 12. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENTS
OUT
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ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A. (Continued)
IN OUT
IN
OUT
J
L
10
V
= 3.8V
IN
1
V
= 2V/DIV
IN
V
= 2.25V
IN
0.1
0.01
V
V
C
= 2.2V
IN
= 1.8
= 10µF
OUT
OUT
V
= 5mV/DIV
OUT
I
= 1A
OUT
10
100
1k
10k
100k
TIME (200µs/DIV)
FREQUENCY (Hz)
FIGURE 14. LINE TRANSIENT RESPONSE
FIGURE 15. OUTPUT NOISE SPECTRAL DENSITY
C
and the feedback reference voltage is clamped to the
SS
Applications Information
voltage across it. The start-up time is set by Equation 1.
Input Voltage Requirements
The ISL80101 is capable of delivering the following fixed output
voltages: 1.8V, 2.5V, 3.3V, 5.0V. Due to the nature of an LDO, V
C
x0.5
SS
(EQ. 1)
-----------------------
=
t
start
2A
IN
Equation 2 determines the C required for a specific start-up
SS
in-rush current, where V
total capacitance on the output and I
current.
must be some margin higher than V
plus dropout at the
OUT
is the output voltage, C is the
OUT
OUT
maximum rated current of the application if active filtering
is the desired in-rush
(EQ. 2)
INRUSH
(PSRR) is expected from V to V . The generous dropout
IN OUT
specification of this family of LDOs allows applications to design
a level of efficiency.
V
xC
x2A
OUT
OUT
I
---------------------------------------------------
=
C
SS
x0.5V
INRUSH
Enable Operation
The ENABLE turn-on threshold is typically 800mV with 80mV of
hysteresis. An internal pull-up or pull-down resistor to change
these values is available upon request. As a result, this pin must
not be left floating, and should be tied to V if not used. A 1kΩ to
10kΩ pull-up resistor is required for applications that use open
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
External Capacitor Requirements
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
IN
collector or open drain outputs to control the ENABLE pin. The
ENABLE pin may be connected directly to V for applications
IN
with outputs that are always on.
OUTPUT CAPACITOR
The ISL80101 applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
Power-good Operation
PG is a logic output that indicates the status of V . The PG flag
is an open-drain NMOS that can sink up to 10mA during a fault
condition. The PG pin requires an external pull-up resistor
OUT
customer. Stable operation over full temperature, V range,
IN
V
range and load extremes are guaranteed for all capacitor
OUT
types and values assuming a minimum of 10µF X5R/X7R is used
for local bypass on V . This output capacitor must be
typically connected to the V
pin. The PG pin should not be
OUT
OUT
and GND pins of the LDO with PCB traces
pulled up to a voltage source greater than V . PG goes low when
IN
connected to the V
OUT
the output voltage drops below 84% of the nominal output
voltage or if the part is disabled. PG functions during current limit
and thermal shutdown. For applications not using this feature,
connect this pin to ground.
no longer than 0.5cm.
There is a growing trend to use very-low ESR multilayer ceramic
capacitors (MLCC) because they can support fast load transients
and also bypass very high frequency noise from other sources.
However, the effective capacitance of MLCCs drops with applied
voltage, age, and temperature. X7R and X5R dieletric ceramic
capacitors are strongly recommended as they typically maintain
a capacitance range within ±20% of nominal voltage over full
operating ratings of temperature and voltage.
Soft-start Operation
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2µA current source charges up this
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ISL80101
Additional capacitors of any value in ceramic, POSCAP,
Thermal Fault Protection
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
The power level and the thermal impedance of the package
(+45°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
Current Limit Protection
connected to the V and GND pins of the LDO with PCB traces no
IN
The ISL80101 LDO incorporates protection against overcurrent due
to any short or overload condition applied to the output pin. The LDO
performs as a constant current source when the output current
exceeds the current limit threshold noted in the “Electrical
longer than 0.5cm.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Notes 8, 9)” on
page 4. The power dissipation can be calculated by using
Equation 3:
Specifications” table on page 4. If the short or overload condition is
removed from V , then the output returns to normal voltage
OUT
regulation mode. In the event of an overload condition, the LDO may
begin to cycle on and off due to the die temperature exceeding
thermal fault condition and subsequently cooling down after the
power device is turned off.
(EQ. 3)
P
= V – V
I
+ V I
OUT IN GND
D
IN
OUT
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
A(MAX)
and the
determine the
J(MAX)
maximum allowable power dissipation, as shown in Equation 4:
(EQ. 4)
P
= T
– T
JMAX A JA
DMAX
is the junction-to-ambient thermal resistance.
JA
For safe operation, enure that the power dissipation P ,
D
calculated from Equation 3, is less than the maximum allowable
power dissipation P
.
D(MAX)
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for effective heat dissipation. Figure 16 shows a curve
for the of the DFN package for different copper area sizes.
JA
49
47
45
43
41
39
37
2
4
6
8
10 12 14 16 18 20 22 24
2
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 16. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS vs EPAD-MOUNT COPPER LAND
JA
AREA ON PCB
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ISL80101
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN6931.2
CHANGE
September 25, 2015
Applied New Intersil Standards
Removed 1st bullet in Features on page 1 which read ±0.2% initial V
accuracy
OUT
Changed 7th bullet in Features on page 1 from Excellent 58dB PSRR at 1kHz to Excellent 65dB PSRR
“Pin Descriptions” on page 3 - description reworded for clarity.
Changed temperature of Latch-up in “Absolute Maximum Ratings” on page 4 from +85°C to +125°C.
Removed “ADJ” from Sense in “Recommended Operating Conditions” on page 4.
Updated the EA amp in the “Block Diagram” on page 2 by switching the + and - terminals. The positive
terminal is now connected to the Sense pin.
Added Note 12 on page 5, “IPD is the internal pull-down current that discharges the external SS capacitor on
disable. ICHG is the current from the SS pin that charges the external SS capacitor during start-up.”
Changed Title of Figure 3 on page 6 from Dropout vs Temperature to Dropout Voltage vs Temperature
Changed y-axis in Figures 6 and 8 on page 6 from: DV
(%) to: V (%)
OUT
OUT
Changed Time Scale in Figure 9B on page 7 from 50µs to 20µs
Added V = to values in Figure 10 on page 7
IN
Changed Title in Figure 12 on page 7 from PSRR vs Frequency and Load Current to PSRR vs Frequency for
various load currents
Changed Title in Figure 13 on page 7 from PSRR vs Frequency and Output Capacitance (I
OUT
= 100mA) to
PSRR vs Frequency for various output capacitors (I
=100mA)
OUT
Updated Output Spectral Noise Density (Figure 15 on page 8)
Removed mention of “V ” in 1st sentence of “Power-good Operation” on page 8
IN
Electrical Spec ifications changes:
Electrical Spec Table conditions on page 4, changed from: V = V
+ 0.4V, V
OUT
= 1.8V, C = C
IN
= 2.2µF,
OUT
IN OUT
to: V
OUT
+ 0.4V, < V < 6V
IN
“DC Output Voltage Accuracy” on page 4, test conditions changed from: V
OUT
+ 0.4V < V < 6V, 0A < I
IN
<
LOAD
1A, to: 0A < I
< 1A
LOAD
“DC Input Line Regulation” on page 4 - changed symbol from V
/V to V
IN OUT
low line - V
OUT
high
high load)/
OUT
line)/V
OUT
low line. Removed Test Conditions.
“DC Output Load Regulation” on page 4 - changed symbol from V
/I
to V no load-V
OUT
OUT
OUT
OUT
V
no load and added MAX of 1
OUT
Ground Pin Current test conditions changed from:
ILOAD = 0A, 2.2V < VIN < 6V to: ILOAD = 0A
ILOAD = 1A, 2.2V < VIN < 6V to: ILOAD = 1A
Output Short-Circuit Current changed test conditions from: V
Thermal Shutdown Temperature - removed test conditions.
= 0V, 2.2V < V < 6V to: V
IN
= 0V
OUT
OUT
Removed “Rising Threshold” from “Thermal Shutdown Hysteresis”. Removed test conditions.
“AC CHARACTERISTICS” on page 4 changed TYP from “72” to “65” in PSRR, f = 120Hz and in Output Noise
Voltage in test conditions changed “10Hz” to “100Hz” and added V = 2.2V, V
= 1.8V. TYP changed from
IN
OUT
“63” to “53”
“Turn-on Threshold” on page 5 changed MIN from: 0.3 to: 0.5. Removed test conditions
Removed “Rising Threshold” from “Hysteresis” on page 5 and removed test conditions
Changed in “ENABLE Pin Leakage Current” on page 5 - 3V to 2.8V in test conditions
Changed in “PG Flag Low Voltage” on page 5 - test conditions from: V = 2.5V, I
IN SINK
= 500µA; to: V = 3V,
IN
I
= 500µA
SINK
Updated POD L10.3x3 to most recent revision with change as follows:
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line
up with the centers of the corner pins.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
FN6931.2
September 25, 2015
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10
ISL80101
Revision History(Continued)
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision. (Continued)
DATE
REVISION
FN6931.1
CHANGE
July 27, 2011
Added Related Literature
Main change - Deleted Adjustable Output Voltage Option Version from datasheet, now only refers to fixed
output voltage option includes removal of all graphics referring to Adjustable voltage option.
Modified page 1 by adding Table of key differences, graphics and changes to text
page 2 - Updated Ordering Information by:
Removing ADJ Device ISL80101IRAJZ plus Eval boards.
Updated Tape and Reel Note by changing "Add "-T" or "TK"…" to "Add "T*"…"
Updated Abs Max Rating and Thermal Information by adding ESD ratings and Latchup
Changed 10 Ld DFN Tja and Tjc from “45, 4” to “48, 7”
Updated DC Output Voltage Accuracy by combining Vout options
Removed Feedback Pin (Adj Option Only), Feedback Input Current Specs
Removed "(1A Version)" from Output Short-circuit Current Spec
Removed Adjustable In-Rush Current Limit Characteristics and replaced with Soft-Start Characteristics
page 5 - Electrical Spec Note changed from "Compliance to datasheet limits is assured by one or more
methods: production test, characterization and/or design." To "Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and
are not production tested."
Complete Rewrite of Applications Information
POD L10.3x3 Changed Note 4 from "Dimension b applies..." to "Lead width applies..."
Changed Note callout in Detail X from 4 to 5
Changed height in side view from 0.90 MAX to 1.00 MAX
Added Note 4 callout next to lead width in Bottom View
In Land Pattern, corrected lead shape for 4 corner pins to "L" shape (was rectangular and did not match
bottom view)
December 21, 2009
FN6931.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6931.2
September 25, 2015
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11
ISL80101
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 11, 3/15
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
0.415
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6931.2
September 25, 2015
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12
相关型号：
ISL80102IR08Z-T
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RENESAS
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