ISL80505IRAJZ [RENESAS]
High Performance 500mA LDO;
| 型号： | ISL80505IRAJZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | High Performance 500mA LDO |
| 文件： | 总17页 (文件大小：1054K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL54226
FN7614
Rev 2.00
Aug 15, 2016
High-Speed USB 2.0 (480Mbps) DPST Switch with Overvoltage Protection (OVP)
and Dedicated Charger Port Detection
The ISL54226 is a single supply, dual SPST (Single Pole/Single
Features
Throw) switch that is configured as a DPST. It can operate from a
• High-speed (480Mbps) and full-speed (12Mbps) signaling
capability per USB 2.0
single 2.7V to 5.25V supply. The part was designed for switching
or isolating a USB high-speed source or a USB high-speed and
full-speed source in portable battery powered products.
• 1.8V logic compatible (2.7V to +3.6V supply)
The 3.5ΩSPST switches were specifically designed to pass USB
full speed and USB high-speed data signals. They have high
bandwidth and low capacitance to pass USB high-speed data
signals with minimal distortion.
• OE/ALM pin to open all switches and indicate overvoltage
fault condition
• Charger interrupt indicator output
• Power OFF protection
The ISL54226 has OVP detection circuitry on the COM pins to
open the SPST switches when the voltage at these pins
exceeds 3.8V or goes negative by -0.45V. It isolates fault
voltages up to +5.25V or down to -5V from getting passed to
the other side of the switch, thereby protecting the USB down-
stream transceiver.
• COM pins overvoltage protection for +5.25V and -5V fault
voltages
• -3dB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790MHz
• Low ON capacitance @ 240MHz. . . . . . . . . . . . . . . . . . . . . 2pF
• Low ON-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5Ω
The OE/ALM logic pin is an open drain input/output that can
be driven to open the switches or monitored to tell when the
part is in an overvoltage state.
• Single supply operation (V ). . . . . . . . . . . . . . . 2.7V to 5.25V
DD
• Available in µTQFN and TDFN packages
• Pb-Free (RoHS compliant)
The part has an interrupt (INT) output pin to indicate a 1 to 1
(high/high) state on the COM lines to inform the µprocessor
when entering a dedicated charging port mode of operation.
• Compliant with USB 2.0 short circuit and overvoltage
requirements without additional external components
The ISL54226 is available in 8 Ld 1.2mmx1.4mm µTQFN and
8 Ld 2mmx2mm TDFN packages. It operates over a
temperature range of -40 to +85°C.
Applications
• MP3 and other personal media players
• Cellular/mobile phones, PDA’s
• Digital cameras and camcorders
• USB switching
3.3V
3.3V
500Ω
100kΩ
VDD
INT
OE/ALM
LOGIC
µP
CONTROL
VBUS
D-
4MΩ
D+
COM -
D-
USB
OVP
DET
COM +
HIGH-SPEED
TRANSCEIVER
D+
ISL54226
GND
GND
TIME SCALE (0.2ns/DIV)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. USB 2.0 HS EYE PATTERN WITH SWITCHES IN THE
SIGNAL PATH
FN7614 Rev 2.00
Aug 15, 2016
Page 1 of 17
ISL54226
Pin Configurations
ISL54226
(8 LD 1.2x1.4 µTQFN)
TOP VIEW
ISL54226
(8 LD 2x2 TDFN)
TOP VIEW
PD
INT
1
2
3
4
8
7
6
5
VDD
LOGIC
OE/ALM
D-
D+
OVP
4MΩ
COM+
D-
1
D+
OVP
GND
COM-
LOGIC
4MΩ
NOTE:
1. Switches Shown for OE/ALM = Logic “0”.
Pin Descriptions
Truth Table
PIN
INPUT
OUTPUT
µTQFN
TDFN
NAME
DESCRIPTION
Charger Mode Interrupt Output
USB Data Port
SIGNAL AT COM
4
5
6
7
8
1
2
1
2
3
4
5
6
7
INT
PINS
OE/ALM
D-, D+
OFF
ON
INT
OE/ALM
Low
STATE
Normal
Normal
OVP
D+
0V to 3.6V
0V to 3.6V
0
1
0
High
High
High
COM+ USB Data Port
High
GND
Ground Connection
Overvoltage
Range
OFF
Low
COM- USB Data Port
Overvoltage
Range
1
0
1
OFF
OFF
ON
High
Low
High
Low
Low
High
OVP
D-
USB Data Port
OE/ALM Switch Enable/Alarm (Open Drain)
Drive Low to Open Switches
COM Pins Tied
Together
Charger
Port (CP)
Outputs are Low when OVP is Activated
COM Pins Tied
Together
Normal
3
-
8
VDD
PD
Power Supply
PD
Thermal Pad. Tie to Ground or Float
Logic “0” when 0.5V, Logic “1” when 1.4V with a 2.7V to 3.6V Supply.
TABLE 1. OVP TRIP POINT VOLTAGE
SYSTEM VOLTAGE CONDITIONS
TRIP POINT
CODEC SUPPLY
2.7V to 3.3V
2.7V to 3.3V
SWITCH SUPPLY (V
2.7V to 5.25V
)
COMs SHORTED TO
PROTECTED
Yes
MIN
3.62V
-0.6V
MAX
3.95V
-0.29V
DD
VBUS
-5V
2.7V to 5.25V
Yes
FN7614 Rev 2.00
Aug 15, 2016
Page 2 of 17
ISL54226
Ordering Information
PACKAGE
Tape & Reel
(Pb-Free)
PART NUMBER
(Notes 2, 5)
TEMP. RANGE
(°C)
PKG.
DWG. #
PART MARKING
ISL54226IRUZ-T (Note 4) (No longer
available or supported)
U5
-40 to +85
8 Ld 1.2mmx1.4mm µTQFN
L8.1.4x1.2
ISL54226IRTZ-T (Note 3)
ISL54226IRTZ-T7A (Note 3)
ISL54226IRTZEVAL1Z
NOTES:
226
-40 to +85
-40 to +85
8 Ld 2mmx2mm TDFN
8 Ld 2mmx2mm TDFN
L8.2x2C
L8.2x2C
226
Evaluation Board
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54226. For more information on MSL please see techbrief TB363.
FN7614 Rev 2.00
Aug 15, 2016
Page 3 of 17
ISL54226
Absolute Maximum Ratings
Thermal Information
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
VDD to COMx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V
COMx to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6V
Input Voltages
D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
COM+, COM- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V
OE/ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V
Continuous Current (COM - / D-, COM + / D+) . . . . . . . . . . . . . . . . . ±40mA
Peak Current (COM-/D-, COM+/D+)
Thermal Resistance (Typical)
8 Ld µTQFN Package (Notes 7, 9) . . . . . . .
8 Ld TDFN Package (Notes 6, 8). . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(°C/W)
210
96
(°C/W)
165
19
JA
JC
Normal Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . . . . ±100mA
ESD Rating:
Human Body Model (Tested per JESD22-A114-F) . . . . . . . . . . . . >5.5kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . >250V
Charged Device Model (Tested per JESD22-C101-D). . . . . . . . . . . . >2kV
Latch-up (Tested per JEDEC; Class II Level A) . . . . . . . . . . . . . . . . at +85°C
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V
DD
Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 5.25V
Analog Signal Range
V
= 2.7V to 5.25V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3.6V
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
8. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
9. For , the “case temp” location is taken at the package top center.
JC
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: V = +3.3V, GND = 0V, V
= 1.4V,
DD
OE/ALMH
V
= 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
OE/ALML
TEMP
MIN
MAX
PARAMETER
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, r (High-Speed)
TEST CONDITIONS
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
V
V
= 2.7V, OE/ALM = 1.4V, I = 17mA, V
Dx COM+
= 0V to 400mV (see Figure 4, Note 15)
or
or
or
25
Full
25
-
3.5
5
7
Ω
Ω
ON
DD
COM-
-
-
r
Matching Between Channels, r
ON
V
V
= 2.7V, OE/ALM = 1.4V, I = 17mA, V
Dx COM+
-
0.2
0.45
0.55
1
Ω
ON
(High-Speed)
DD
= Voltage at max r , (Notes 14, 15)
COM-
ON
Full
25
-
-
Ω
r
Flatness, R
FLAT(ON)
V
V
= 2.7V, OE/ALM = 1.4V, I = 17mA, V
Dx COM+
= 0V to 400mV, (Notes 13, 15)
-
0.26
Ω
ON
(High-Speed)
DD
COM-
Full
+25
Full
25
-
-
1.2
17
22
20
-
Ω
ON-Resistance, r
V
V
= 3.3V, OE/ALM = 1.4V, I
= 17mA, V
COM+
or
-
6.8
Ω
ON
DD
COMx
= 3.3V (see Figure 4, Note 15)
COM-
-
-
Ω
OFF Leakage Current, I
V
V
= 5.25V, OE/ALM = 0V, V = 0.3V, 3.3V,
Dx
= 3.3V, 0.3V
-20
1
nA
nA
µA
µA
µA
µA
µA
Dx(OFF)
DD
COMX
Full
25
-
30
ON Leakage Current, I
V
V
= 5.25V, OE/ALM = 5.25V, V = 0.3V, 3.3V,
Dx
= 0.3V, 3.3V
-9
-
-
-
-
-
9
Dx(ON)
DD
COMX
Full
-12
12
11
22
1
Power OFF Leakage Current, I
Power OFF Logic Current, I
, I
V
= 0V, V
= 5.25V, V
COM-
= 5.25V, OE/ALM = 0V 25
25
-
-
-
COM+ COM- DD
COM+
V
V
= 0V, OE/ALM = 5.25V
OE/ALM
DD
DD
Power OFF D+/D- Current, I , I
D+ D-
= 0V, OE/ALM = V , V = V = 5.25V
25
DD D+
D-
Overvoltage Protection Detection
Positive Fault-Protection Trip Threshold,
V
= 2.7V to 5.25V, OE/ALM = V
25
25
25
25
3.62
3.8
-0.45
102
2
3.95
V
V
DD
DD
DD
V
(see Table 1 on page 2)
PFP
Negative Fault-Protection Trip Threshold,
V
= 2.7V to 5.25V, OE/ALM = V
-0.6
-0.29
DD
V
(see Table 1 on page 2)
NFP
OFF Persistence Time
Fault Protection Response Time
Negative OVP Response: V = 2.7V, OE/ALM = V
DD
V
,
-
-
-
-
ns
µs
DD
= 0V to -5V, R = 1.5kΩ
Dx L
Positive OVP Response: V = 2.7V, OE/ALM = V
V
,
DD
DD
= 0V to 5.25V, R = 1.5kΩ
Dx
L
FN7614 Rev 2.00
Aug 15, 2016
Page 4 of 17
ISL54226
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: V = +3.3V, GND = 0V, V
= 1.4V,
DD
OE/ALMH
V
= 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
OE/ALML
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
= 2.7V, OE/ALM = V , V = 0V to 5.25V or 0V to
(°C) (Notes 11, 12) TYP (Notes 11, 12) UNITS
ON Persistence Time
Fault Protection Recovery Time
V
25
-
45
-
µs
DD
-5V, R = 1.5kΩ
DD Dx
L
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
V
= 3.3V, V
= 3V, R = 50Ω, C = 50pF
25
25
25
-
-
-
160
60
-
-
-
ns
ns
ps
DD
INPUT
L
L
(see Figure 3)
Turn-OFF Time, t
OFF
V
= 3.3V, V
= 3V, R = 50Ω, C = 50pF
INPUT L L
DD
(see Figure 3)
Skew, (t
t
)
V
= 3.3V, OE/ALM = 3.3V, R = 45Ω,C = 10pF,
50
SKEWOUT - SKEWIN
DD
L
L
t
= t = 500ps at 480Mbps, (Duty Cycle = 50%)
R
F
(see Figure 7)
Rise/Fall Degradation (Propagation
Delay), t
V
= 3.3V, OE/ALM = 3.3V, R = 45Ω,C = 10pF,
25
-
250
-
ps
DD
see Figure 7)
L
L
PD
Crosstalk
V
= 3.3V, R = 50Ω, f = 240MHz (see Figure 6)
25
25
25
25
25
25
-
-
-
-
-
-
-39
-23
790
2.5
4
-
-
-
-
-
-
dB
dB
DD
DD
L
OFF-Isolation
V
= 3.3V, OE/ALM = 0V, R = 50Ω, f = 240MHz
L
-3dB Bandwidth
OFF Capacitance, C
Signal = 0dBm, 0.86VDC offset, R = 50Ω
MHz
pF
L
f = 1MHz, V = 3.3V, OE/ALM = 0V (see Figure 5)
DD
OFF
COM ON Capacitance, C
COM ON Capacitance, C
f = 1MHz, V = 3.3V, OE/ALM = 3.3V, (see Figure 5)
DD
pF
(ON)
f = 240MHz, V = 3.3V, OE/ALM = 3.3V
DD
2
pF
(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range, V
Full
25
2.7
5.25
56
59
30
34
45
50
32
38
V
DD
Positive Supply Current, I
Positive Supply Current, I
Positive Supply Current, I
Positive Supply Current, I
V
V
V
V
= 5.25V, OE/ALM = 5.25V
= 3.6V, OE/ALM = 3.6V
= 4.3V, OE/ALM = 2.6V
= 3.6V, OE/ALM = 1.4V
-
-
-
-
-
-
-
-
45
µA
µA
µA
µA
µA
µA
µA
µA
DD
DD
DD
DD
DD
DD
DD
DD
Full
25
-
23
-
Full
25
35
-
Full
25
25
-
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
V
V
V
V
V
V
V
V
= 2.7V to 3.6V
Full
Full
Full
Full
Full
Full
Full
Full
-
-
0.5
V
V
OE/ALML
DD
DD
DD
DD
DD
DD
DD
DD
Input Voltage High, V
= 2.7V to 3.6V
1.4
-
-
OE/ALMH
OE/ALML
Input Voltage Low, V
Input Voltage High, V
= 3.7V to 4.2V
-
-
0.7
V
= 3.7V to 4.2
1.7
-
-
V
OE/ALMH
OE/ALML
Input Voltage Low, V
= 4.3V to 5.25V
-
-
0.8
V
Input Voltage High, V
= 4.3V to 5.25V
2.0
-
-
-
-
V
OE/ALMH
OE/ALML
OE/ALMH
Input Current, I
Input Current, I
NOTES:
= 5.25V, OE/ALM = 0V
= 5.25V, OE/ALM = 5.25V, 4MΩ Pull-down
-
-
-8.2
1.4
nA
µA
10. V
= Input voltage to perform proper function.
LOGIC
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
14. r matching between channels is calculated by subtracting the channel with the highest max r value from the channel with lowest max r value.
ON
ON
ON
15. Limits established by characterization and are not production tested.
FN7614 Rev 2.00
Aug 15, 2016
Page 5 of 17
ISL54226
Test Circuits and Waveforms
C
V
DD
VDD
t < 20ns
r
t < 20ns
f
LOGIC
INPUT
50%
0V
V
INPUT
V
t
OUT
Dx
OFF
COMx
OE/ALM
SWITCH
INPUT
SWITCH
INPUT
V
INPUT
V
OUT
90%
90%
C
L
50pF
R
50Ω
VIN
L
GND
SWITCH
OUTPUT
0V
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
capacitance.
R
L
-----------------------
V
= V
OUT
(INPUT)
R
+ r
ON
L
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. SWITCHING TIMES
V
DD
C
r
= V /17mA
1
ON
COMx
V
HSDX
V
OE/ALM
DD
V
1
17mA
Dx
GND
Repeat test for all switches.
FIGURE 4. r TEST CIRCUIT
ON
V
DD
C
V
DD
C
SIGNAL
GENERATOR
50Ω
COM+
D+
COMx
OE/ALM
OE/ALM
IMPEDANCE
ANALYZER
VIN
0V OR
VDD
Dx
COM-
D-
ANALYZER
GND
NC
GND
R
L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 5. CAPACITANCE TEST CIRCUIT
FN7614 Rev 2.00
Aug 15, 2016
Page 6 of 17
ISL54226
Test Circuits and Waveforms(Continued)
V
DD
C
t
ri
90%
50%
V
OE/ALM
COM-
DD
10%
90%
DIN+
DIN-
t
15.8Ω
skew_i
OUT+
45Ω
D-
DIN+
DIN-
50%
10%
143Ω
15.8Ω
C
C
L
OUT-
45Ω
COM+
D+
t
fi
t
143Ω
ro
L
90%
10%
90%
50%
GND
OUT+
OUT-
t
skew_o
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
50%
10%
t
f0
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7B. TEST CIRCUIT
FIGURE 7. SKEW TEST
Application Block Diagram
3.3V
3.3V
500Ω
VDD
100kΩ
INT
OE/ALM
4MΩ
µCONTROLLER
3.6V
LOGIC
CONTROL
VBUS
D-
>1MΩ
D-
COM -
COM +
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
OVP
DET
D+
D+
GND
ISL54226
GND
PORTABLE MEDIA DEVICE
FN7614 Rev 2.00
Aug 15, 2016
Page 7 of 17
ISL54226
See Figures 11, 12, 13, 14, 15, 16 in the “Typical Performance
Curves” beginning on page 11.
Detailed Description
The ISL54226 device is a dual single pole/single throw (SPST)
analog switch configured as a DPST that operates from a single
DC power supply in the range of 2.7V to 5.25V.
The Dx switches were specifically designed to pass USB 2.0
high-speed (480Mbps) differential signals in the range of 0V to
400mV. They have low capacitance and high bandwidth to pass
the USB high-speed signals with minimum edge and phase
distortion to meet USB 2.0 high-speed signal quality
specifications. See Figure 17 in the “Typical Performance Curves”
on page 12 for USB High-speed Eye Pattern taken with switch in
the signal path.
It was designed for switching a USB high-speed or full-speed
source in portable battery powered products. It is offered in small
µTQFN and TDFN packages for use in MP3 players, cameras,
PDAs, cellphones, and other personal media players.
The part consists of two 3.5Ω high-speed SPST switches. These
switches have high bandwidth and low capacitance to pass USB
high-speed (480Mbps) differential data signals with minimal
edge and phase distortion. They can also swing from 0V to 3.6V
to pass USB full speed (12Mbps) differential data signals with
minimal distortion.
The Dx switches can also pass USB full-speed signals (12Mbps) in
the range of 0V to 3.6V with minimal distortion and meet all the
USB requirements for USB 2.0 full-speed signaling. See Figure 18
in the “Typical Performance Curves” on page 13 for USB
Full-speed Eye Pattern taken with switch in the signal path.
The part contains special overvoltage detection and protection
(OVP) circuitry on the COM+ and COM- pins. This circuitry acts to
open the USB in-line switches when the part senses a voltage on
the COM pins that is >3.8V (typ) or < -0.45V (typ). It isolates
voltages up to 5.25V and down to -5V from getting through to the
other side of the switch to protect the USB transceiver connected
at the D+ and D- pins.
The switches are active (turned ON) whenever the OE/ALM
voltage is logic “1” (High) and OFF when the OE/ALM voltage is
logic “0” (Low).
Overvoltage Protection (OVP)
The maximum normal operating signal range for the Dx switches
is from 0V to 3.6V. For normal operation the signal voltage
should not be allow to exceed these voltage levels or go below
ground by more than -0.3V.
The device has an open drain OE/ALM pin that can be driven
“Low” to open all switches. The OE/ALM pin gets internally pulled
“Low” whenever the part senses an overvoltage condition. The
pin must be externally pulled “High” with a 100kΩ pull-up resistor
and monitored for a “Low” to determine when an overvoltage
condition has occurred.
However, in the event that a positive voltage >3.8V (typ) to 5.25V,
such as the USB 5V V
voltage, gets shorted to one or both of
BUS
the COM+ and COM- pins or a negative voltage < -0.45V (typ) to
-5V gets shorted to one or both of the COM pins, the ISL54226
has OVP circuitry to detect the over voltage condition and open
the SPST switches to prevent damage to the USB down-stream
transceiver connected at the signal pins (D-, D+).
The part has charger port interrupt detection circuitry (CP) on the
COM pins that outputs a Low on the INT pin to inform the
µController or power management circuitry when entering a
dedicated charging port mode of operation. The charger mode
operation is initiated by driving the OE/ALM pin Low and
externally connecting the COM pins together which pulls the COM
lines High, triggering the INT pin to go Low and the SPST switches
to open.
The OVP and power-off circuitry allows the COM pins (COM-,
COM+) to be driven up to 5.25V while the V supply voltage is in
DD
the range of 0V to 5.25V. In this condition the part draws <100µA
of I
and I current and causes no stress to the IC. In
COMx
DD
addition the SPST switches are OFF and the fault voltage is
isolated from the other side of the switch.
The ISL54226 was designed for MP3 players, cameras,
cellphones, and other personal media player applications that
need to switch a high-speed or full-speed transceiver source. A
“Typical Application Block Diagram” of this functionality is shown
on page 7.
The OE/ALM pin gets internally pulled low whenever the part
senses an overvoltage condition. The pin must be externally
pulled “High” with a 100kΩ pull-up resistor and monitored for a
“Low” to determine when an overvoltage condition has occurred.
This output can be monitored by a µController to indicate a fault
condition to the system.
A detailed description of the SPST switches is provided in the
following section.
High-Speed (Dx) SPST Switches
The Dx switches are bi-directional switches that can pass USB
high-speed and USB full-speed signals when VDD is in the range
of 2.7V to 5.25V.
When powered with a 2.7V supply, these switches have a
nominal r of 3.5Ω over the signal range of 0V to 400mV with a
ON
r
flatness of 0.26Ω. The r matching between the switches
ON
ON
over this signal range is only 0.2Ω ensuring minimal impact by
the switches to USB high-speed signal transitions. As the signal
level increases, the r switch resistance increases. At signal
ON
level of 3.3V, the switch resistance is nominally 9.8Ω.
FN7614 Rev 2.00
Aug 15, 2016
Page 8 of 17
ISL54226
External V Series Resistor to Limit I
DD
25
20
15
10
5
DD
V
= V
= -5V
COM-
Current during Negative OVP Condition
COM+
A 100Ω to 1kΩ resistor in series with the VDD pin (see Figure 8)
5.25V
is required to limit the I current draw from the system power
DD
supply rail during a negative OVP fault event.
With a negative -5V fault voltage at both com pins, the graph in
3.6V
Figure 9 shows the I current draw for different external resistor
DD
values for supply voltages of 2.7V, 3.6V, and 5.25V. Note: With a
500Ω resistor the current draw is limited to around 5mA. When
2.7V
the negative fault voltage is removed the I current will return
DD
to it’s normal operation current of 25µA to 45µA.
0
100 200 300 400
500 600 700 800 900
RESISTOR (Ω)
1k
The series resistor also provides improved ESD and latch-up
immunity. During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate currents
can be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from the
FIGURE 9. NEGATIVE OVP I CURRENT vs RESISTOR VALUE vs
DD
V
SUPPLY
V
power supply to ground. This will result in a significant
DD
POWER
amount of current flow in the IC, which can potentially create a
latch-up state or permanently damage the IC. The external V
resistor limits the current during this overstress situation and has
been found to prevent latch-up or destructive damage for many
overvoltage transient events.
MANAGEMENT
BATTERY CHARGER
CIRCUITRY
DD
V
SUPPLY
“LOW” TO
INDICATE
CHARGER
CONNECTED
C
V
BUS
Under normal operation the low microamp I current of the IC
DD
produces an insignificant voltage drop across the series resistor
resulting in no impact to switch operation or performance.
BATTERY
CHARGER
VDD
D+
D+
COM+
CHG DET
COM-
LOGIC
USB
TRANCEIVER
200Ω
D-
D-
V
OE/ALM
SUPPLY
GND
INT
C
GND
PROTECTION
µP
RESISTOR
I
100Ω TO 1kΩ
DD
100kΩ
DRIVEN LOW BY µP
(OE/ALM = “0”)
V
DD
D+
D-
COM+
FIGURE 10. CHARGER PORT DETECTION
OVP
-5V
COM-
FAULT
VOLTAGE
LOW
TO
INDICATE
OVP
CHARGER PORT DETECTION
OE/ALM
INT
LOGIC
The ISL54226 has special charger port detection circuitry that
monitors the voltage at the com pins to detect when a battery
charger has been connected into the USB port (see Figure 10).
GND
When the battery charger is connected to the USB connector it
shorts the COM+ and COM- pins together. The shorting of the pins
is sensed by the ISL54226 IC and it pulls the COM+ and COM-
lines high and as long as the OE/ALM pin is driven low
FIGURE 8. V SERIES RESISTOR TO LIMIT I CURRENT DURING
DD DD
NEGATIVE OVP AND FOR ENHANCED ESD AND LATCH-
UP IMMUNITY
(OE/ALM = “0”) by the µP, it will drive its INT logic output “Low” to
tell the power management circuitry that a battery charger is
connected at the port and not a USB host transceiver. The power
management circuitry will then set the appropriate current level
and use the USB connector VBUS line to charge the battery.
FN7614 Rev 2.00
Aug 15, 2016
Page 9 of 17
ISL54226
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS
ISL54226 Operation
The following will discuss using the ISL54226 shown in the
“Application Block Diagram” on page 7.
LOGIC = “0” (LOW)
OE/ALM
LOGIC = “1” (HIGH)
V
SUPPLY RANGE
2.7V to 3.6V
OE/ALM
DD
0.5V
or
1.4V
Power
floating
The power supply connected at the VDD pin provides the DC bias
voltage required by the ISL54226 part for proper operation. The
3.7V to 4.2V
0.7V
or
floating
1.7V
2.0V
ISL54226 can be operated with a V voltage in the range of
DD
2.7V to 5.25V.
4.3V to 5.25V
0.8V
or
floating
For lowest power consumption you should use the lowest VDD
supply.
A 0.01µF or 0.1µF decoupling capacitor should be connected
from the VDD pin to ground to filter out any power supply noise
from entering the part. The capacitor should be located as close
to the VDD pin as possible.
Normal Operation Mode
With a signal level in the range of 0V to 3.6V the switches will be
ON when the OE/ALM pin = Logic “1” and will be OFF (high
impedance) when the OE/ALM pin = Logic “0”.
In a typical application, V will be in the range of 2.8V to 4.3V
DD
and will be connected to the battery or LDO of the portable
media device.
USB 2.0 V
Short Requirements
BUS
The USB specification in section 7.1.1 states a USB device must
Logic Control
The state of the ISL54226 device is determined by the voltage at
the OE/ALM pin and the signal voltage at the COM pins. Refer to
“Truth Table” on page 2.
be able to withstand a V short (4.4V to 5.25V) or a -1V short to
the D+ or D- signal lines when the device is either powered off or
powered on for at least 24 hours.
BUS
The ISL54226 part has special power-off protection and OVP
detection circuitry to meet these short circuit requirements. This
circuitry allows the ISL54226 to provide protection to the USB
down-stream transceiver connected at its signal pins (D-, D+) to
meet the USB specification short circuit requirements.
The OE/ALM pin is internally pulled low through 4MΩresistors to
ground and can be tri-stated by a µProcessor.
The OE/ALM pin is an open drain connection. It should be pulled
high through an external 100kΩ pull-up resistor. The OE/ALM pin
can then be driven “Low” by a µProcessor to open all switches or
it can be monitored by the µProcessor for a “Low” when the part
goes into an overvoltage condition.
The power-off protection and OVP circuitry allows the COM pins
(COM-, COM+) to be driven up to 5.25V or down to -5V while the
V
supply voltage is in the range of 0V to 5.25V. In these
DD
overvoltage conditions with a 500Ω external VDD resistor the
part draws <55µA of current into the COM pins and causes no
stress/damage to the IC. In addition all switches are OFF and the
The ISL54226 is designed to minimize I current consumption
DD
when the logic control voltage is lower than the V supply
DD
voltage. With V = 3.6V and the OE/ALM logic pin is at 1.4V the
DD
shorted V
voltage will be isolated from getting through to the
BUS
part typically draws only 25µA. With V = 4.3V and the OE/ALM
other side of the switch channels, thereby protecting the USB
transceiver.
DD
logic pin is at 2.6V the part typically draws only 35µA. Driving the
logic pin to the V supply rail minimizes power consumption.
DD
The OE/ALM pin can be driven with a voltage higher than the V
DD
supply voltage. It can be driven up to 5.25V with a V supply in
DD
the range of 2.7V to 5.25V.
FN7614 Rev 2.00
Aug 15, 2016
Page 10 of 17
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
16
14
12
10
8
3.4
3.3
3.2
3.1
3.0
2.9
I
= 17mA
I
= 17mA
COM
COM
2.7V
3.0V
2.7V
3.3V
3.0V
6
3.6V
4.3V
4
5.25V
3.3V
3.0
2
5.25V
0
0
0.6
1.2
1.8
2.4
3.6
0
0.1
0.2
0.3
0.4
V
(V)
V
(V)
COM
COM
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH
VOLTAGE
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH
VOLTAGE
4.5
18
V+ = 2.7V
V+ = 2.7V
I
= 17mA
COM
16
14
12
10
8
I
= 17mA
COM
4.0
3.5
3.0
2.5
2.0
1.5
+85°C
+25°C
-40°C
+85°C
+25°C
-40°C
6
4
2
0
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
0
0.1
0.2
0.3
0.4
V
(V)
COM
COM
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
4.0
3.5
3.0
2.5
2.0
9
8
7
6
5
4
3
2
1
V+ = 3.3V
I
= 17mA
COM
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
V+ = 3.3V
I
= 17mA
COM
0
0.1
0.2
0.3
0.4
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.6
V
(V)
COM
COM
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
FN7614 Rev 2.00
Aug 15, 2016
Page 11 of 17
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
V
= 3.3V
DD
TIME SCALE (0.2ns/DIV)
FIGURE 17. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
FN7614 Rev 2.00
Aug 15, 2016
Page 12 of 17
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
V
= 3.3V
DD
TIME SCALE (10ns/DIV)
FIGURE 18. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
5.0
4.5
4.0
V
= 5.25V
V
= 3.3V
DD
DD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
= 5.25V
DD
V
= 3.3V
DD
0
1
2
3
4
5
0
1
2
3
4
5
V
VOLTAGE (V)
V
VOLTAGE (V)
OL
OH
FIGURE 20. I vs V vs V for INT
OL OL DD
FIGURE 19. I vs V vs V for INT
OH OH DD
FN7614 Rev 2.00
Aug 15, 2016
Page 13 of 17
ISL54226
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
-10
1
R
= 50Ω
= 0dBm, 0.2V
L
0
-20
-30
V
BIAS
DC
IN
-1
-2
-3
-4
-40
-50
-60
-70
-80
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
-90
-100
-110
1M
10M
100M
1G
0.001
0.01
0.1
1M
10M
100M
500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. FREQUENCY RESPONSE
FIGURE 22. OFF-ISOLATION
-10
Die Characteristics
R
= 50Ω
= 0dBm, 0.2V
L
-20
-30
V
BIAS
DC
IN
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL
(POWERED UP):
GND
-40
TRANSISTOR COUNT:
-50
1297
-60
PROCESS:
-70
Submicron CMOS
-80
-90
-100
-110
0.001
0.01
0.1
1M
10M
100M
500M
FREQUENCY (Hz)
FIGURE 23. CROSSTALK
FN7614 Rev 2.00
Aug 15, 2016
Page 14 of 17
ISL54226
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN7614.2
CHANGE
August 15, 2016
Updated Ordering Information on page 3.
Updated About Intersil Verbiage.
Updated POD L8.2X2C with most current version. Revision change is as follows:
Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
September 12, 2013
FN7614.1
Page 2, Pin Description table OE/ALM Description: changed the last line from: “Outputs a Low when OTV is
Activated” to: “Outputs are Low when OVP is Activated”
Page 4 - Updated ESD ratings from:
Human Body Model (Tested per JESD22-A114-F)..........>2kV
Machine Model (Tested per JESD22-A115-A)................>150V
Charged Device Model (Tested per JESD22-C101-D)......>2kV
to:
Human Body Model (Tested per JESD22-A114-F)..........>5.5kV
Machine Model (Tested per JESD22-A115-A)................>250V
Charged Device Model (Tested per JESD22-C101-D)......>2kV
July 29, 2010
FN7614.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2010-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7614 Rev 2.00
Aug 15, 2016
Page 15 of 17
ISL54226
Package Outline Drawing
L8.2x2C
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD
Rev 1, 5/15
2.00
6
A
PIN #1 INDEX AREA
6
B
PIN 1
INDEX AREA
8
1
0.50
1.45±0.050
Exp.DAP
(4X)
0.15
0.25
( 8x0.30 )
0.10
C A B
M
TOP VIEW
0.80±0.050
Exp.DAP
BOTTOM VIEW
( 8x0.20 )
( 8x0.30 )
Package Outline
SEE DETAIL "X"
( 6x0.50 )
C
0.10
C
0 . 75 ( 0 . 80 max)
1.45
2.00
BASE PLANE
SEATING PLANE
0.08
C
SIDE VIEW
( 8x0.25 )
0.80
2.00
TYPICAL RECOMMENDED LAND PATTERN
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature and may
5.
be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
FN7614 Rev 2.00
Aug 15, 2016
Page 16 of 17
ISL54226
Package Outline Drawing
L8.1.4x1.2
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/09
0.80
REF
4X 0.40 BSC
1.40
A
PIN 1 INDEX AREA
8
PIN 1
B
6
INDEX AREA
0.30
1
C0.10
5
0.40
0.60
7X 0.30
±0.05
0.10
4
2
2X
0.10
0.05
M
M
C
C
A B
0.40 BSC
TOP VIEW
8 X 0.20
4
BOTTOM VIEW
SEE DETAIL "X"
0.80
REF
MAX. 0.50
4X 0.40
PKG OUTLINE
0.10
C
C
SEATING PLANE
0.08
C
8 X 0.20
SIDE VIEW
0.60
0.60
7X 0.50
0 . 2 REF
C
0.70
0.60
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7614 Rev 2.00
Aug 15, 2016
Page 17 of 17
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