ISL95338EVAL1Z_技术文档

DATASHEET

ISL95338

Bidirectional Buck-Boost Voltage Regulator

FN8896

Rev.2.00

Nov 30, 2017

The ISL95338 is a bidirectional, buck-boost voltage

regulator that provides buck-boost voltage regulation and

protection features. Intersil’s advanced R3™ Technology

is used to provide high light-load efficiency, fast transient

response, and seamless DCM/CCM transitions.

Features

• Bidirectional buck, boost, and buck-boost operation

• Input voltage range 3.8V to 24V (no dead zone)

• Output voltage up to 20V

The ISL95338 takes input power from a wide range of

DC power sources (conventional AC/DC ADPs, USB PD

ports, travel ADPs, etc.) and safely converts it to a

regulated voltage up to 24V. The ISL95338 can also

convert a wide range DC power source connected at its

output (system side) to a regulated voltage to its input

(ADP side). This bidirectional buck-boost regulation

feature makes its application very flexible.

• Up to 1MHz switching frequency

• Programmable soft-start time

• LDO output for VDD and VDDP

• System status alert function

• Bidirectional internal discharge function

• Active switching for negative voltage transitions

• Bypass mode in both directions

The ISL95338 includes various system operation

functions such as Forward mode enable, Reverse mode

enable, programmable soft-start time, and adjustable

• Forward mode enable, Reverse mode enable

• OCP, OVP, UVP, and OTP protection

V

in both the forward direction and reverse direction.

OUT

The protection functionalities include OCP, OVP, UVP,

OTP, etc.

2

• SMBus and auto-increment I C compatible

• Pb-free (RoHS compliant)

• 32 Ld 4x4 TQFN Package

The ISL95338 has serial communication through

2

SMBus/I C that allows programming of many critical

parameters to deliver a customized solution. These

programming parameters include, but are not limited to:

output current limit, input current limit, and output

voltage setting.

Applications

• Tablet, ultrabook, power bank, mobile devices, and

USB-C

Related Literature

• For a full list of related documents, visit our website

• ISL95338 product page

FN8896 Rev.2.00

Nov 30, 2017

Page 1 of 48

ISL95338

Rs1

20m

Rs2

VSYS (SYSTEM SIDE)

V

(ADAPTER SIDE )

IN

10m

Q1

Q2

Q4

Q3

L1

CSOP

CSON

SCL

CSIN

CSIP

ADP

SDA

ADPS

FRWEN

RVSEN

VOUT

ISL95338

VOUTS

ADDR0

PROCHOT #

RVSPG

GND

ADDR1

REF

FRWPG

V

IN

OUT

Figure 1. Typical Application Circuit

FN8896 Rev.2.00

Nov 30, 2017

Page 2 of 48

ISL95338

Contents

1.

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

1.3

1.4

1.5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.

Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

2.3

2.4

2.5

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Recommended Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SMBus Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.

4.

Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General SMBus Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

4.2

4.3

4.4

4.5

4.6

Data Validity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SMBus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

SMBus and I C Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.

ISL95338 SMBus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

Setting System Side Current Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Setting Input Current Limit in Forward Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Setting System Regulating Voltage in Forward Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Setting PROCHOT# Threshold for ADP Side Overcurrent Condition . . . . . . . . . . . . . . . . . . . 25

Setting PROCHOT# Threshold for System Side Overcurrent Condition. . . . . . . . . . . . . . . . . 25

Setting PROCHOT# Debounce Time and Duration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Regulating Voltage Register in Reverse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Output Current Limit Register in Reverse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Input Voltage Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.

Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1

6.2

6.3

6.4

6.5

R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

ISL95338 Bidirectional Buck-Boost Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

FN8896 Rev.2.00

Nov 30, 2017

Page 3 of 48

ISL95338

6.6

Forward Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Reverse Mode for USB OTG (On-the-Go). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Fast REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Fast Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Way Overcurrent Protection (WOCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

ADP Input Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

System Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

System Output Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

ADP Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

ADP Output Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Switching Power MOSFET Gate Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

ADP Side Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.7

6.8

6.9

6.10

6.11

6.12

6.13

6.14

6.15

6.16

6.17

6.18

7.

General Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1

7.2

7.3

7.4

7.5

Select the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Select the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Select the Switching Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Select the Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Select the Resistor Divider for VOUTS and ADPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.

9.

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10. About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

FN8896 Rev.2.00

Nov 30, 2017

Page 4 of 48

ISL95338

1. Overview

1.1

Block Diagram

VOUT

ADP

VOUT

DRV

+

DCIN

FWRPG

FWREN

CMP

4.1V

-

5V

LDO

+

-

LOW

PWR

LDO

0.8V

VDD

+

CMP

DRV

RVSPG

RVSEN

-

3.8V

2.7V

+

-

+

~1V

CMP

-

DAC

AND

CNTL

LOGIC

FOR OC/

OV/UV/

OT

PROG

SMBUS/I²C

DIGITAL

CONTROL

AND

FUSE

LOGIC

BOOT1

ADDR0

ADDR1

UGATE1

PHASE1

SCL

SDA

BUF

+

LGATE1

GND

SoftStart

OV

CMP

-

+

CMP

-

-1100mV+

LGATE2

Fwd

VDAC

+fwd:820mV-

+rev:1200mV

+

CMP

UV

VDDP

-

+

-

PHASE2

1uA

REF

Rev VDAC

VREF

UGATE2

+

-

VOUTs

ADPs

Fwd

Rev

BOOT2

COMPf

VINDAC

CSIP

+

Fwd

Rev

-

COMP

LOOP

-

CSIP

CSIN

ACDAC

18x

SELECTOR

+

-

COMPr

+

Rev

Fwd

ACFB

-

18x

ERROR

+

AMPLIFIER

+

CSOP

CSON

18x

IFB2DAC

IFB2

Fwd

Rev

-

+

-

+

18x

-

+

-

CMP

DCHOTDAC

DRV

PROCHOT#

+

-

Figure 2. Block Diagram

FN8896 Rev.2.00

Nov 30, 2017

Page 5 of 48

ISL95338

1. Overview

1.2

Simplified Application Circuit

Rs1

Rs2

10m

VSYS (SYSTEM SIDE)

V

IN

(ADAPTER SIDE)

20m

Q1

Q2

Q4

Q3

L1

CSOP

CSON

SCL

CSIN

CSIP

ADP

SDA

ADPS

FRWEN

RVSEN

VOUT

ISL95338

VOUTS

ADDR0

PROCHOT#

GND

ADDR1

REF

RVSPG

FRWPG

3.3V

FRWPG

RVSPG

SCL

SDA

V

IN

V

OUT

Figure 3. Simplified Application Diagram

1.3

Ordering Information

Part Number

(Notes 3, 4)

Temp. Range

(°C)

Package

Pkg.

Dwg. #

Part Marking

95338H

(RoHS Compliant)

32 Ld 4x4 TQFN

ISL95338HRTZ (Note 1)

ISL95338IRTZ (Note 2)

ISL95338EVAL1Z

Notes:

-10 to +100

-40 to +100

L32.4x4A

95338I

Evaluation board

1. Add “-T7A” suffix for 250 unit,“-TK” suffix for 1k unit, or “-T” suffix for 6k unit tape and reel options. Refer to TB347 for details on

reel specifications.

2. Add “-TK” suffix for 1k unit or “-T” suffix for 6k unit tape and reel options. Refer to TB347 for details on reel specifications.

3. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), see the product information page for ISL95338. For more information on MSL, refer to

TB363.

FN8896 Rev.2.00

Nov 30, 2017

Page 6 of 48

ISL95338

1. Overview

1.4

Pin Configuration

ISL95338

(32 Ld 4x4 TQFN)

Top View

32 31 30 29 28 27 26 25

CSON

CSOP

FRWPG

PROCHOT#

SCL

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

VOUTS

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

SDA

GND

(BOTTOM PAD)

RVSEN

FRWEN

VDD

DCIN

9

10 11

12 13 14 15 16

1.5

Pin Descriptions

Pin Number

Pin Name

Description

BOTTOM

PAD

GND

CSON

CSOP

Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. It should also

be used as the thermal pad for heat dissipation.

1

Forward V_OUTcurrent sense “-” input. Connect to VOUT current resistor negative input. Place a 0.1µF

ceramic capacitor between CSOP and CSON to provide differential mode filtering.

2

Forward V_OUTcurrent sense “+” input. Connect to VOUT current resistor positive input. Place a 0.1µF

ceramic capacitor between CSOP and CSON to provide differential mode filtering.

3

4

VOUTS

BOOT2

Forward VSYS feedback voltage. Use a resistor divider externally to configure forward VSYS voltage.

High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 pin and the

PHASE2 pin. The boot capacitor is charged through an internal boot diode connected from the VDDP pin

to the BOOT2 pin when the PHASE2 pin drops below VDDP minus the voltage drop across the internal

boot diode.

5

6

UGATE2

PHASE2

High-side MOSFET Q4 gate drive.

Current return path for the high side MOSFET Q4 gate drive. Connect this pin to the node consisting of

the high-side MOSFET Q4 source, the low-side MOSFET Q3 drain, and the one terminal of the inductor.

7

8

LGATE2

VDDP

Low-side MOSFET Q3 gate drive.

Power supply for the gate drivers. Connect to VDD pin through a 4.7Ω resistor and connect a 1µF ceramic

capacitor to GND.

9

LGATE1

PHASE1

Low-side MOSFET Q2 gate drive.

10

Current return path for the high side MOSFET Q1 gate drive. Connect this pin to the node consisting of

the high-side MOSFET Q1 source, the low-side MOSFET Q2 drain, and the input terminal of the inductor.

11

UGATE1

High-side MOSFET Q1 gate drive.

FN8896 Rev.2.00

Nov 30, 2017

Page 7 of 48

ISL95338

1. Overview

Pin Number

Pin Name

Description

12

BOOT1

High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 pin and the

PHASE1 pin. The boot capacitor is charged through an internal boot diode connected from the VDDP pin

to the BOOT1 pin when the PHASE1 pin drops below VDDP minus the voltage drop across the internal

boot diode.

13

14

15

ADPS

CSIN

CSIP

Reverse output voltage feedback. Use a resistor divider externally to configure the reverse output voltage.

ADP current sense “-” input.

ADP current sense “+” input. The modulator also uses this for sensing input voltage in Forward mode and

output voltage in Reverse mode.

16

17

18

ADP

DCIN

VDD

Used to sense ADP voltage. When ADP voltage is higher than 4.1V, Forward mode can be enabled.

The ADP pin is also one of the two internal low power LDO inputs.

Input of an internal LDO providing power to the IC. Connect a diode OR from ADP and system outputs.

Bypass this pin with an MLCC capacitor.

Output of the internal LDO; provide the bias power for the internal analog and digital circuit. Connect a

1µF ceramic capacitor to GND.

If VDD is pulled below 2.7V, the ISL95338 will reset all the SMBus register values to the default.

19

20

21

22

23

FRWEN

RVSEN

SDA

Forward mode enable, analog signal input. Forward mode is valid if the FRWEN pin voltage is greater

than 0.8V.

Reverse mode enable, digital signal input. Reverse mode is valid if the signal is “1” (logic high), otherwise,

Reverse mode is disabled.

SMBus data I/O. Connect to the data line from the host controller. Connect a 10k pull-up resistor

according to the SMBus specification.

SCL

SMBus clock I/O. Connect to the clock line from the host controller. Connect a 10k pull-up resistor

according to the SMBus specification.

PROCHOT# Open-drain output. Pulled low when input currentis detected as hot in Forward and Reverse mode.

SMBus command to pull low (refer to Table 8 on page 25 and Table 10 on page 26 for Control 2 Register

0x3DH and Control4 Register 0x4EH).

24

25

26

27

28

29

FRWPG

ADDR0

RVSPG

PROG

COMPF

REF

Open-drain output. Indicator output to indicate the forward modulator is enabled.

Address setting pin for the IC. The IC address is set by ADDR0 and ADDR1 logic voltage levels.

Open-drain output. Indicator output to indicate the reverse modulator is enabled.

A resistor from PROG pin to GND sets the default forward system output voltage.

Forward mode error amplifier output. Connect a compensation network externally from COMPF to GND.

Output voltage soft-start reference. A ceramic capacitor from REF to GND is set to the desired soft-start

time. In Forward mode, forward output voltage (VOUTS) reference soft-start time is set. In Reverse mode,

reverse output voltage (ADPS) reference soft-start time is set.

30

31

32

COMPR

VOUT

Reverse mode error amplifier output. Connect a compensation network externally from COMPR to GND.

Forward V_OUTsense voltage for modulator and PHASE 2 zero-current comparator.

ADDR1

Address setting pin for the IC. The IC address is set by ADDR0 and ADDR1 logic voltage levels.

FN8896 Rev.2.00

Nov 30, 2017

Page 8 of 48

ISL95338

2. Specifications

2.1

Absolute Maximum Ratings

Parameter

Minimum

-0.3

Maximum

+30

Unit

V

CSIP, CSIN, DCIN, ADPS, ADP

CSIP

0.3

ADP + 2

+30

V

PHASE1

GND - 0.3

GND - 2 (<20ns)

PHASE1 - 0.3

GND - 0.3

GND - 2 (<20ns)

PHASE2 - 0.3

GND - 0.3

GND - 2 (<20ns)

-0.3

V

PHASE1

+30

V

UGATE1

BOOT1 + 0.3

+30

V

PHASE2

V

PHASE2

+30

V

UGATE2

BOOT2 + 0.3

VDDP + 0.3

+27

V

LGATE1, LGATE2

V

LGATE1, LGATE2

V

VOUT, VOUTS, CSOP, CSON

VDD, VDDP

V

-0.3V

+6.5

V

BOOT1, BOOT2

- 0.3

VDDP + 27

PHASE1 + 6.5

PHASE2 + 6.5

+6.5

V

BOOT1

(PHASE1 - 0.3)

(PHASE2 - 0.3)

-0.3

V

BOOT2

V

COMPR, COMPF, REF, PROG

RVSEN, FRWEN, ADDR0, ADDR1

FRWPG, PROCHOT#, RVSPG

SCL, SDA

V

-0.3

+6.5

V

-0.3

+6.5

V

-0.3

+6.5

V

BOOT1-PHASE1, BOOT2-PHASE2

CSIP-CSIN, CSOP-CSON

ESD Rating

-0.3

+0.3

V

2

mA

Unit

kV

V

Rating

2

Human Body Model (Tested per JS-001-2014)

Machine Model (Tested per JESD22-A115C)

Charged Device Model (Tested per JS-002-2014)

Latch-Up (Tested per JESD78E)

200

1

kV

mA

100

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may

adversely impact product reliability and result in failures not covered by warranty.

FN8896 Rev.2.00

Nov 30, 2017

Page 9 of 48

ISL95338

2. Specifications

2.2

Thermal Information

Thermal Resistance (Typical)

_JA(°C/W)



_JC(°C/W)

32 Ld TQFN Package (Notes 5, 6)

Notes:

37

2

5. _JAis measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”

features. See TB379.

6. For _JC, the “case temp” location is the center of the ceramic on the package underside.

Parameter

Minimum

Maximum

Unit

Junction Temperature Range (T_J)

-10

+125

°C

Storage Temperature Range (T_S)

Pb-Free Reflow Profile

-65

+150

°C

Refer to TB493

2.3

Recommended Operation Conditions

Parameter

Minimum

Maximum

+100

Unit

°C

V

Ambient Temperature - HRTZ

Ambient Temperature - IRTZ

ADP Input Voltage

-10

-40

+4

+100

+24

V_OUTInput Voltage

+4

+20

V

2.4

Electrical Specifications

Operating conditions: ADP = CSIP = CSIN = 4V and 23V, VOUTS = VOUT = CSOP = CSON = 8V, unless otherwise noted. Boldface

limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified.

Min

Max

Parameter

UVLO/ACOK

Symbol

Test Conditions

(Note 7) Typ (Note 7) Unit

VADP UVLO Rising

VADP UVLO Hysteresis

V_OUTUVLO Rising

VADP_UVLO_r

VADP_UVLO_h

VOUT_UVLO_r

VOUT_UVLO_h

VDD_2P7_r

3.9

2.5

4.2

530

4.2

4.55

2.9

V

mV

V

V_OUTUVLO Hysteresis

300

2.7

mV

V

VDDA 2P7 Rising, SMBus Active

(Note 8)

VDDA 2P7 POR Hysteresis

(Note 8)

VDD_2P7_h

VDD_3P8_r

150

3.8

mV

V

VDDA 3P8 POR Rising,

3.6

3.9

Modulator, and Gate Driver Active

VDD 3P8 Hysteresis

FRWEN Rising

VDD_3P8_h

FRWEN_r

FRWEN_h

150

0.8

50

mV

V

0.775

0.825

FRWEN Hysteresis

Bias Current

mV

Forward Supply Current, Disable

State

ADP, ADPS CSIN, CSIP, VDDP, DCIN = 5V,

FWREN = Low

130

70

200

150

µA

Reverse Supply Current, Disable

State

V_OUT, VOUTS CSON, CSOP, VDDP,

DCIN = 5V, RVSEN = Low

Forward Supply Current, Enable

State

ADP, ADPS CSIN, CSIP, DCIN = 20V,

FWREN = High

3000

3300

FN8896 Rev.2.00

Nov 30, 2017

Page 10 of 48

ISL95338

2. Specifications

Operating conditions: ADP = CSIP = CSIN = 4V and 23V, VOUTS = VOUT = CSOP = CSON = 8V, unless otherwise noted. Boldface

limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)

Min

Max

Parameter

Symbol

Test Conditions

(Note 7) Typ (Note 7) Unit

Reverse Supply Current, Enable

State

VOUT, VOUTS CSON, CSOP, DCIN = 20V,

RVSEN = High

3000

1600

3300

2000

µA

Forward Supply Current, Enable

State

DCIN only (does not include gate driver

current)

Reverse Supply Current, Enable

State

DCIN only (does not include gate driver

current)

Linear Regulator

VDDA Output Voltage

VDDA Dropout Voltage

VDD Overcurrent Threshold

VDD

6V < V_ADP< 23V, no load

30mA, V_DCIN= 4V

4.5

90

5.1

100

135

5.5

V

VDD_dp

VDD_OC

mV

mA

165

ADP Current Regulation, R_ADP= 20mΩ

Input Current Accuracy

|CSIP - CSIN| = 80mV

4

A

%

-3

-4

+3

+4

|CSIP - CSIN| = 40mV

2

A

%

|CSIP - CSIN| = 10mV

0.5

A

-10

-3.0

-6.0

+10

+3.0

+6.0

%

ADP Current PROCHOT#

Threshold

R_s1= 20mΩ

I_{ADP_HOT_TH10}

ACProchot = 0x0A80H (2688mA)

ACProchot = 0x0400H (1024mA)

2688

1024

mA

%

mA

%

Voltage Regulation

Output Voltage Accuracy Forward

Output Voltage Accuracy Reverse

Output Voltage Accuracy Forward

Output Voltage Accuracy Reverse

Minimum Input Voltage Accuracy

HRTZ

IRTZ

Measured at VOUTS, 8V and up

Measured at VOUTS, 4V to 8V

Measured at ADPS, 8V and up

Measured at ADPS, 4V to 8V

Measured at VOUTS, 8V and up

Measured at VOUTS, 4V to 8V

Measured at ADPS, 8V and up

Measured at ADPS, 4V to 8V

Measured at ADPS

-1

-1.5

-1

+1

+1.5

+1

%

V

-1.5

-2

+1.5

+2

IRTZ

-1.5

-2

+1.5

+2

IRTZ

-3

+3

-3

+3

V

Current Regulation, R_s2= 10mΩ

OUT

V_OUTCurrent Accuracy

|CSOP - CSON| = 60mV

|CSOP - CSON| = 20mV

|CSOP - CSON| = 10mV

|CSOP - CSON| = 5mV

6

2

A

%

A

-3

-5

+3

+5

%

A

1

-10

-20

0

+10

+20

27

%

A

0.5

%

ADP Current-Sense Amplifier, R_ADP= 20mΩ

CSIP/CSIN Input Voltage Range

V_CSIP/N

V

FN8896 Rev.2.00

Nov 30, 2017

Page 11 of 48

ISL95338

2. Specifications

Operating conditions: ADP = CSIP = CSIN = 4V and 23V, VOUTS = VOUT = CSOP = CSON = 8V, unless otherwise noted. Boldface

limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)

Min

Max

Parameter

Symbol

Test Conditions

(Note 7) Typ (Note 7) Unit

V_OUTCurrent-Sense Amplifier, R_BAT= 10mΩ

System Side Current PROCHOT#

Threshold, R_s2= 10mΩ

I_{SYS_HOT}

SystemSideProchot = 0x1000H (4096mA)

4096

mA

%

-5

+5

RVSEN

High-Level Input Voltage

Low-Level Input Voltage

Input Leakage Current

PROCHOT#, RVSPG, FWRPG

Output Sinking Current

Leakage Current

0.9

V

0.35

1

V_RVSEN= 3.3V, 5V

Pin at 0.4V

µA

37

mA

µA

1

PROCHOT#

PROCHOT# Debounce Time

(Note 8)

PROCHOT# Debounce register

PROCHOT# Duration register

-15

15

%

PROCHOT# Duration Time

(Note 8)

Protection

ADP Overvoltage Rising

Hysteresis

Forward mode

25.5

0.85

0.9

26.4

27

V

ADP Overvoltage Hysteresis

0.35

1.1

V

VOUTS Overvoltage Rising

Threshold

Forward mode VOUTS-12xREF

Reverse mode ADPS-12xREF

Forward mode VOUTS-12xREF

Reverse mode ADPS-12xREF

1.45

1.5

VOUTS Overvoltage Hysteresis

0.55

1.2

V

ADPS Overvoltage Rising

Threshold

ADPS Overvoltage Hysteresis

0.6

V

VOUTS Undervoltage Falling

Threshold

-1.15

-1.55

140

-0.85

-0.55

-0.85

160

VOUTS Undervoltage Hysteresis

0.6

V

ADPS Undervoltage Falling

Threshold

-1.2

ADPS Undervoltage Hysteresis

0.4

V

Over-Temperature Threshold

(Note 8)

150

°C

Oscillator

Oscillator Frequency, Digital Core

Only

0.85

-15

1

1.15

15

MHz

%

Digital Debounce Time Accuracy

PV Debounce and UV Debounce for

FWRPG and RVSPG delay

Miscellaneous

Switching Frequency Accuracy

All programmed f_SWsettings, CCM, and no

period stretching

-15

15

%

ADP Discharge Current

ADP = 5V

6.5

8.5

0.7

14

mA

µA

V_OUTDischarge Current

REF Pin Sink/Source Current

REF Pin Fast Sink Current

REF Pin Fast Source Current

V_OUT= 5V

Control1 <3> = 0

Control1 <3> = 1

FN8896 Rev.2.00

Nov 30, 2017

Page 12 of 48

ISL95338

2. Specifications

Operating conditions: ADP = CSIP = CSIN = 4V and 23V, VOUTS = VOUT = CSOP = CSON = 8V, unless otherwise noted. Boldface

limits apply across the junction temperature range, -10°C to +125°C unless otherwise specified. (Continued)

Min

Max

Parameter

Symbol

Test Conditions

(Note 7) Typ (Note 7) Unit

SMBus

SDA/SCL Input Low Voltage

SDA/SCL Input High Voltage

SDA/SCL Input Bias Current

SDA, Output Sink Current (Note 8)

SMBus Frequency

3.3V

0.8

1

V

3.3V

2

3.3V

µA

mA

kHz

SDA = 0.4V

4

f_SMB

10

400

1200

475

1200

450

1200

450

1200

450

Gate Driver

UGATE1 Pull-Up Resistance

UGATE1 Source Current

UGATE1 Pull-Down Resistance

UGATE1 Sink Current

UG1_RPU

UG1_SRC

UG1_RPD

UG1_SNK

100mA source current

UGATE1 - PHASE1 = 2.5V

100mA sink current

800

2

mΩ

A

1.3

1.9

1.3

2.3

1.3

2.3

1.3

350

2.8

800

2

mΩ

A

UGATE1 - PHASE1 = 2.5V

100mA source current

LGATE1 - GND = 2.5V

100mA sink current

LGATE1 Pull-Up Resistance

LGATE1 Source Current

LG1_RPU

mΩ

A

LG1_SRC

LGATE1 Pull-Down Resistance

LGATE1 Sink Current

LG1_RPD

300

3.5

800

2

mΩ

A

LG1_SNK

LGATE1 - GND = 2.5V

100mA source current

LGATE2 - GND = 2.5V

100mA sink current

LGATE2 Pull-Up Resistance

LGATE2 Source Current

LG2_RPU

mΩ

A

LG2_SRC

LGATE2 Pull-Down Resistance

LGATE2 Sink Current

LG2_RPD

300

3.5

800

2

mΩ

A

LG2_SNK

LGATE2 - GND = 2.5V

100mA source current

UGATE2 - PHASE2 = 2.5V

100mA sink current

UGATE2 Pull-Up Resistance

UGATE2 Source Current

UGATE2 Pull-Down Resistance

UGATE2 Sink Current

UG2_RPU

UG2_SRC

UG2_RPD

UG2_SNK

mΩ

A

300

3.5

20

mΩ

A

UGATE2 - PHASE2 = 2.5V

2.3

10

UGATE1 to LGATE1 Dead Time

LGATE1 to UGATE1 Dead Time

LGATE2 to UGATE2 Dead Time

UGATE2 to LGATE2 Dead Time

t_UG1LG1DEAD

t_LG1UG1DEAD

t_LG2UG2DEAD

t_UG2LG2DEAD

40

ns

20

FN8896 Rev.2.00

Nov 30, 2017

Page 13 of 48

ISL95338

2. Specifications

2.5

SMBus Timing Specification

Min

Max

Parameters

Symbol

F_SMB

Test Conditions

(Note 7)

Typ

(Note 7) Unit

SMBus Frequency

10

4.7

4

400

kHz

µs

Bus-Free Time

t_BUF

Start Condition Hold Time from SCL

t_HD:STA

t_SU:STA

µs

Start Condition Set-Up Time from

SCL

4.7

µs

Stop Condition Set-Up Time from

SCL

t_SU:STO

4

µs

SDA Hold Time from SCL

SDA Set-Up Time from SCL

SCL Low Period

t_HD:DAT

t_SU:DAT

t_LOW

300

250

4.7

4

ns

µs

s

SCL High Period

t_HIGH

SMBus Inactivity Timeout

Maximum charging period without an SMBus Write

to MaxSystemVoltage or ADPCurrent register

175

Notes:

7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.

PWM

t_LGFUGR

t

FU

t

RU

1V

UGATE

LGATE

1V

t

RL

t

FL

t_UGFLGR

Figure 4. Gate Driver Timing Diagram

FN8896 Rev.2.00

Nov 30, 2017

Page 14 of 48

ISL95338

3. Typical Performance Curves

Figure 6. Reverse Mode, Soft-Start, 12V_ADP, 5V_SYS

Figure 5. Forward Mode Soft-Start, 12V_ADP, 20V_SYS

Figure 7. V_SYSVoltage Ramps Up in Forward Mode,

Buck -> Buck-Boost -> Boost Operation Mode Transition

Figure 8. ADP Voltage Ramps Up in Reverse Mode, Buck

-> Buck-Boost -> Boost Operation Mode Transition

Figure 9. Reverse Mode, 5V_ADPto 20V_ADP

Figure 10. Reverse Mode, 20V_ADPto 5V_ADP

FN8896 Rev.2.00

Nov 30, 2017

Page 15 of 48

ISL95338

3. Typical Performance Curves

Figure 12. Forward Mode, 20V_SYSto 5V_SYS

Figure 11. Forward Mode, 5V_SYSto 20V_SYS

Figure 14. Forward Mode, Output Voltage Loop to

Adapter Voltage Loop Transition. 6V_ADP, Input Voltage

Limit = 5.12V, 12V_SYS, System Load 0A to 0.78A Step,

System Current Limit = 5A, Input Current Limit=5A

Figure 13. Forward Mode, Output Voltage Loop to ADP

Current Loop Transition. 5V_ADP, 12V_SYS, System Load

0A to 0.65A Step, ADP Current Limit = 1.5A

Figure 15. Forward Mode, Force Buck-Boost Mode to

Boost Mode. 10V_ADP, 12V_SYS

Figure 16. Reverse Mode, Force Buck-Boost Mode to

Boost Mode. 12V_ADP, 10V_SYS

FN8896 Rev.2.00

Nov 30, 2017

Page 16 of 48

ISL95338

3. Typical Performance Curves

Figure 17. Forward Mode, 5V_ADP, 12V_SYS, 0-2A Transient

Load

Figure 18. Reverse Mode, 20V_ADP, 12V_SYS, 0-2A

Transient Load

FN8896 Rev.2.00

Nov 30, 2017

Page 17 of 48

ISL95338

4. General SMBus Architecture

VDD SMB

SMBUS SLAVE

SCL

INPUT

CONTROL

OUTPUT

INPUT

STATE

MACHINE

REGISTERS

MEMORY

etc.

SMBUS MASTER

INPUT

SCL

SDA

CONTROL

OUTPUT

INPUT

OUTPUT

INPUT

CPU

SDA

CONTROL

SMBUS SLAVE

OUTPUT

SCL

CONTROL

OUTPUT

INPUT

STATE

MACHINE

REGISTERS

MEMORY

etc.

SDA

CONTROL

SCL SDA

OUTPUT

TO OTHER

SLAVE DEVICES

Figure 19. General SMBus Architecture

4.1

Data Validity

The data on the SDA line must be stable during the HIGH period of the SCL, unless generating a START or STOP

condition. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Refer to Figure 20.

SDA

SCL

DATA LINE

STABLE

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 20. Data Validity

4.2

START and STOP Conditions

As Figure 21 shows, the START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.

The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be

sent before each START condition.

SDA

SCL

S

P

START

STOP

CONDITION

Figure 21. Start and Stop Waveforms

FN8896 Rev.2.00

Nov 30, 2017

Page 18 of 48

ISL95338

4. General SMBus Architecture

4.3

Acknowledge

Each address and data transmission uses nine clock pulses. The ninth pulse is the acknowledge bit (ACK). After the

start condition, the master sends seven slave address bits and an R/W bit during the next eight clock pulses. During

the nine clock pulse, the device that recognizes its own address holds the data line low to acknowledge (refer to

Figure 22). The acknowledge bit is also used by both the master and the slave to acknowledge receipt of register

addresses and data.

MSB

SDA

SCL

1

2

8

9

START

ACKNOWLEDGE

FROM SLAVE

Figure 22. Acknowledge on the SMBus

4.4

SMBus Transactions

All transactions start with a control byte sent from the SMBus master device. The control byte begins with a

START condition, followed by seven bits of slave address (refer to Table 1 on page 20), and the R/W bit. The R/W

bit is “0” for a WRITE or “1” for a READ. If any slave device on the SMBus bus recognizes its address, it will

acknowledge by pulling the Serial Data (SDA) line low for the last clock cycle in the control byte. If no slave exists

at that address or it is not ready to communicate, the data line will be “1”, indicating a Not Acknowledge condition.

After the control byte is sent and the ISL95338 acknowledges it, the second byte sent by the master must be a

register address byte such as 0x14 for the SystemCurrentLimit register. The register address byte tells the

ISL95338 which register the master will write or read. See Table 2 on page 20 for details of the registers. After the

ISL95338 receives a register address byte, it will respond with an acknowledge.

4.5

Byte Format

Every byte put on the SDA line must be eight bits long and must be followed by an acknowledge bit. Data is

transferred with the Most Significant Bit (MSB) first and the Least Significant Bit (LSB) last. The LO BYTE data

is transferred before the HI BYTE data. For example, when writing 0x41A0, 0xA0 is written first and 0x41 is

written second.

WRITE TO A REGISTER

SLAVE

ADDR + W

REGISTER

ADDR

LO BYTE

DATA

HI BYTE

DATA

S

A

A P

READ FROM A REGISTER

SLAVE

ADDR + W

REGISTER

ADDR

SLAVE

LO BYTE

DATA

HI BYTE

DATA

A

P

S

A

N P

ADDR + R

DRIVEN BY THE

MASTER

S

P

A

N

START

STOP

ACKNOWLEDGE

NO

P

DRIVEN BY THE IC

ACKNOWLEDGE

Figure 23. SMBus Read and Write Protocol

2

4.6

SMBus and I C Compatibility

2

The ISL95338 SMBus minimum input logic high voltage is 2V, so it is compatible with I C with higher than 2V

pull-up power supply.

2

The ISL95338 SMBus registers are 16 bits, so it is compatible with 16 bits I C or 8 bits I C with auto-increment

capability. The chip will not acknowledge SMBus communication unless either ADP or VOUT is higher than 4.1V.

FN8896 Rev.2.00

Nov 30, 2017

Page 19 of 48

ISL95338

5. ISL95338 SMBus Commands

The ISL95338 receives control inputs from the SMBus interface after Power-On Reset (POR). The serial interface

complies with the System Management Bus Specification, which can be downloaded from www.smbus.org. The

ISL95338 uses the SMBus Read-word and Write-word protocols (see Figure 23 on page 19) to communicate with the

host system. The ISL95338 is an SMBus slave device and does not initiate communication on the bus. The ISL95338

address is programmable through ADDR0 and ADDR1 voltage levels (see Table 1) to support multiple ISL95338s

sharing a common SMBus. Connect the ADDR0 and ADDR1 pins to either ground or VDD.

Bits 1 and 2 are for ADDR0 and ADDR1 pins, respectively. The “1” means the pin voltage is high, while the “0”

means the pin voltage is low. From Bits 3 to 7, the value is fixed as 10010. The address is latched at rising VDD 2P7

POR threshold.

Table 1. Address Table

Read/

Write

Binary

Address

Hex

Address

ADDR0

ADDR1

0

1

0

1

0

1

0

1

0

1

0

1

0

1001,0001

1001,0000

1001,0101

1001,0100

1001,0011

1001,0010

1001,0111

1001,0110

0X91H

0X90H

0X95H

0X94H

0X93H

0X92H

0X97H

0X96H

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up

resistors for SDA and SCL to achieve rise times according to the SMBus specifications.

The illustration in this datasheet is based on current sensing-resistors R = 20mΩand R = 10mΩ, unless otherwise

s1

s2

specified.

Table 2. Register Summary

Register Read/ Number

Address Write of Bits

Register Names

Description

Default

SystemCurrentLimit

0X14

R/W

11

[12:2]11-bit, LSB size 4mA, total range 6080mA, with 10mΩ 1.5A

R_S1

ForwardRegulatingVoltage

0X15

R/W

12

[14:3]12-Bit, LSB size 12mV, see PROG Table 21 on page 38 5.004V

9.000V

12.000V

16.008V

20.004V

Control0

0X39

0X3A

0X3C

0X3D

0X3F

R/W

R

16

11

Configure various options

Indicate various status

0x0000h

Information1

Control1

R/W

Configure various options

Control2

ForwardInputCurrent

[12:2]11-bit, LSB size 4mA, total range 6080mA, with

20mΩ R_S1

Set by

PROG pin

ADPInputCurrentProchot#

0X47

0X48

R/W

6

[12:7] ADP input current Prochot# threshold. Default 3.072A, 3.072A

128mA resolution for 20mΩ R_s1, only for Forward mode.

SystemInputCurrentProchot#

[13:8] System current towards switcher Prochot# threshold.

Default 4.096A, 256mA resolution for 10mΩ R_s2

4.096A

.

FN8896 Rev.2.00

Nov 30, 2017

Page 20 of 48

ISL95338

5. ISL95338 SMBus Commands

Table 2. Register Summary (Continued)

Register Read/ Number

Register Names

Address Write of Bits

Description

Default

ReverseRegulatingVoltage

ReverseOutputCurrent

InputVoltageLimit

0X49

0X4A

0X4B

R/W

12

6

[14:3] 12-bit, LSB size 12mV

Reverse mode regulating voltage reference

5.004V

[12:7] 6-bit, LSB size 128mA, total range 4.096A

Reverse mode maximum current limit

0.512A

4.096V

6

[13:8] 6-bit, LSB size 512mV

Forward low V_INloop voltage reference

Control3

0X4C

0X4D

0X4E

0XFE

0XFF

R/W

R

16

8

Configure various options

Indicate various status

0x0000h

0x00h

Information2

Control4

R/W

R

[7:0] 8-bit, configure various options

Manufacturers ID register

Device ID register - 0x0D

ManufacturerID

DeviceID

8

0x49h

R

8

0x0Dh

5.1

Setting System Side Current Limit

To set the system side current limit, which is the output current in Forward mode or the input current in Reverse

mode, write a 16-bit SystemCurrentLimit command (0X14H or 0b00010100) using the Write-word protocol shown

in Figure 5 on page 15 and the data format shown in Table 3 for a 10mΩ Rs2 or Table 4 for a 5mΩ Rs2.

The ISL95338 limits the system current by limiting the CSOP-CSON voltage. By using the recommended current-

sense resistor value Rs2 = 10mΩ, the register’s LSB always translates to 4mA of output current. The

SystemCurrentLimit register accepts any output current command but only the valid register bits will be written to

the register and the maximum value is clamped at 6080mA for Rs2 = 10mΩ.

After POR, the SystemCurrentLimit register is reset to 0x05DCH (1.5A). The SystemCurrentLimit register can be

read back to verify its content.

Table 3. SystemCurrentLimit Register 0x14H (11-Bit, 4mA Step, 10mΩ Sense Resistor, x36)

Bit

<1:0>

<2>

Description

Not used

0 = Add 0mA of system current limit.

1 = Add 4mA of system current limit.

<3>

<4>

<5>

<6>

<7>

<8>

<9>

<10>

<11>

0 = Add 0mA of system current limit.

1 = Add 8mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 16mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 32mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 64mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 128mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 256mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 512mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 1024mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 2048mA of system current limit.

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Table 3. SystemCurrentLimit Register 0x14H (11-Bit, 4mA Step, 10mΩ Sense Resistor, x36) (Continued)

Bit

Description

<12>

0 = Add 0mA of system current limit.

1 = Add 4096mA of system current limit.

<13:15>

Not used

Maximum

<12:2> = 10111110000 6080mA

Note: The gain for the system side current-sensing amplifiers is different for Forward mode and Reverse mode. The gain in Reverse

mode is half of that in Forward mode. Therefore, in Reverse mode, the sensing current value needs to be doubled compared to the

value set in the SystemCurrentLimit register.

Table 4. ForwardOutputCurrentLimit Register 0x14H (11-Bit, 8mA Step, 5mΩ Sense Resistor, x36)

Bit

<1:0>

<2>

Description

Not used

0 = Add 0mA of system current limit.

1 = Add 8mA of system current limit.

<3>

<4>

0 = Add 0mA of system current limit.

1 = Add 16mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 32mA of system current limit.

<5>

0 = Add 0mA of system current limit.

1 = Add 64mA of system current limit.

<6>

0 = Add 0mA of system current limit.

1 = Add 128mA of system current limit.

<7>

0 = Add 0mA of system current limit.

1 = Add 256mA of system current limit.

<8>

0 = Add 0mA of system current limit.

1 = Add 512mA of system current limit.

<9>

0 = Add 0mA of system current limit.

1 = Add 1024mA of system current limit.

<10>

<11>

<12>

0 = Add 0mA of system current limit.

1 = Add 2048mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 4096mA of system current limit.

0 = Add 0mA of system current limit.

1 = Add 8192mA of system current limit.

<13:15>

Not used

Maximum

<12:2> = 10111110000 12160mA

5.2

Setting Input Current Limit in Forward Mode

To set the input current limit in Forward mode, write a 16-bit ForwardInputCurrent command (0x3FH or

0b00111111) using the Write-word protocol shown in Figure 5 on page 15 and the data format shown in Table 5 for

a 20mΩ Rs1 or Table 6 on page 23 for a 10mΩ Rs1.

The ISL95338 limits the input current in Forward mode by limiting the CSIP-CSIN voltage. By using the

recommended current-sense resistor values, the register’s LSB always translates to 4mA of input current. Any

input current limit command will be accepted but only the valid register bits will be written to the

ForwardInputCurrent register and the maximum values are clamped at 6080mA for Rs1 = 20mΩ.

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5. ISL95338 SMBus Commands

.

Table 5. ForwardInputCurrent Register 0x3FH (11-Bit, 4mA Step, 20mΩ Sense Resistor, x18)

Bit

<1:0>

<2>

Description

Not used

0 = Add 0mA of input current limit in Forward mode.

1 = Add 4mA of input current limit in Forward mode.

<3>

<4>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 8mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 16mA of input current limit in Forward mode.

<5>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 32mA of input current limit in Forward mode.

<6>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 64mA of input current limit in Forward mode.

<7>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 128mA of input current limit in Forward mode.

<8>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 256mA of input current limit in Forward mode.

<9>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 512mA of input current limit in Forward mode.

<10>

<11>

<12>

<13:15>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 1024mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 2048mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 4096mA of input current limit in Forward mode.

Not used

Maximum

<12:4> = 10111110000 6080mA.

Table 6. ForwardInputCurrent Register 0x3FH (11-BIT, 8mA STEP, 10mΩ Sense Resistor, x18)

Bit

<1:0>

<2>

Description

Not used

0 = Add 0mA of input current limit in Forward mode.

1 = Add 8mA of input current limit in Forward mode.

<3>

<4>

<5>

<6>

<7>

<8>

<9>

<10>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 16mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 32mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 64mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 128mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 256mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 512mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 1024mA of input current limit in Forward mode.

0 = Add 0mA of input current limit in Forward mode.

1 = Add 2048mA of input current limit in Forward mode.

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Table 6. ForwardInputCurrent Register 0x3FH (11-BIT, 8mA STEP, 10mΩ Sense Resistor, x18) (Continued)

Bit

Description

<11>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 4096mA of input current limit in Forward mode.

<12>

0 = Add 0mA of input current limit in Forward mode.

1 = Add 8192mA of input current limit in Forward mode.

<13:15>

Not used

Maximum

<12:4> = 10111110000 12160mA

5.3

Setting System Regulating Voltage in Forward Mode

To set the regulating voltage in Forward mode, write a 16-bit ForwardRegulatingVoltage command (0x15H or

0b00010101) using the Write-word protocol shown in Figure 5 on page 15 and the data format as shown in Table 7.

The output regulating voltage range in Forward mode is 2V to 24V. The ForwardRegulatingVoltage register accepts

any voltage command, but only the valid register bits will be written to the register. The maximum value is clamped

at 24.576V. The ISL95338 accepts a 0V command, but the register value does not change. The VOUTS pin is the

output voltage regulation sense point in Forward mode.

In Forward mode, the customer also can configure the regulating output voltage by setting the external voltage

divider on the VOUTS pin without changing the ForwardRegulatingVoltage register value.

Table 7. ForwardRegulatingVoltage Register 0x15H (12mV Step)

Bit

<2:0>

<3>

Description

Not used

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 12mV of regulating voltage in Forward mode.

<4>

<5>

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 24mV of regulating voltage in Forward mode.

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 48mV of regulating voltage in Forward mode.

<6>

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 96mV of regulating voltage in Forward mode.

<7>

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 192mV of regulating voltage in Forward mode.

<8>

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 384mV of regulating voltage in Forward mode.

<9>

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 768mV of regulating voltage in Forward mode.

<10>

<11>

<12>

<13>

<14>

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 1536mV of regulating voltage in Forward mode.

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 3072mV of regulating voltage in Forward mode.

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 6144mV of regulating voltage in Forward mode.

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 12288mV of regulating voltage in Forward mode.

0 = Add 0mV of regulating voltage in Forward mode.

1 = Add 24576mV of regulating voltage in Forward mode.

<15>

Not used

24576mV

Maximum

Note: The default reading value of this register is 6.288V when the chip is powering up without writing any values because of the

DAC initial value. Thus, write the needed value in this register before enabling forward output voltage.

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5. ISL95338 SMBus Commands

5.4

Setting PROCHOT# Threshold for ADP Side Overcurrent Condition

To set the PROCHOT# assertion threshold for ADP side input overcurrent condition in Forward mode, write a

16-bit ADPsideProchot# command (0x47H or 0b01000111) using the Write-word protocol shown in Table 5 on

page 23 and the data format shown in Table 8. By using the recommended current-sense resistor values, the

register’s LSB always translates to 128mA of input current. The ADPsideProchot# register accepts any current

command, but only the valid register bits will be written to the register. The maximum values are clamped at

6400mA for Rs1 = 20mΩ.

After POR, the ADPsideProchot# register is reset to 0x0C00H. The ADPsideProchot# register can be read back to

verify its content.

If the input current exceeds the ADPsideProchot# register setting, PROCHOT# signal will assert after the

debounce time programmed by the Control2 register Bit<10:9> and latch on for a minimum time programmed by

Control2 register Bit<8:6>.

Table 8. ADPsideProchot# Register 0x47H (20mΩ Sensing Resistor, 128mA Step, x18 Gain)

Bit

<6:0>

<7>

Description

Not used

0 = Add 0mA of ADPsideProchot# threshold.

1 = Add 128mA of ADPsideProchot# threshold.

<8>

<9>

0 = Add 0mA of ADPsideProchot# threshold.

1 = Add 256mA of ADPsideProchot# threshold.

0 = Add 0mA of ADPsideProchot# threshold.

1 = Add 512mA of ADPsideProchot# threshold.

<10>

<11>

<12>

0 = Add 0mA of ADPsideProchot# threshold.

1 = Add 1024mA of ADPsideProchot# threshold.

0 = Add 0mA of ADPsideProchot# threshold.

1 = Add 2048mA of ADPsideProchot# threshold.

0 = Add 0mA of ADPsideProchot# threshold.

1 = Add 4096mA of ADPsideProchot# threshold.

<15:13>

Not used

Maximum

<12:7> = 110010, 6400mA

5.5

Setting PROCHOT# Threshold for System Side Overcurrent Condition

To set the PROCHOT# signal assertion threshold for system side input overcurrent condition in Reverse mode,

write a 16-bit SystemsideProchot# command (0x48H or 0b01001000) using the Write-word protocol shown in

Table 5 on page 23 and the data format shown in Table 9. By using the recommended current-sense resistor values,

the register’s LSB always translates to 256mA of system side current. The SystemsideProchot# register accepts any

current command, but only the valid register bits will be written to the register. The maximum values are clamped

at 12.8A for Rs2 = 10mΩ.

After POR, the SystemsideProchot# register is reset to 0x1000H. The SystemsideProchot# register can be read

back to verify its content.

If the system side current exceeds the SystemsideProchot# register setting, the PROCHOT# signal will assert after

the debounce time programmed by the Control2 register Bit<10:9> and latch on for a minimum time programmed

by Control2 register Bit<8:6>.

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Table 9. SystemsideProchot# Register 0x48H (10mΩ Sensing Resistor, 256mA Step, x18 Gain)

Bit

<7:0>

<8>

Description

Not used

0 = Add 0mA of SystemsideProchot# threshold.

1 = Add 256mA of SystemsideProchot# threshold.

<9>

0 = Add 0mA of SystemsideProchot# threshold.

1 = Add 512mA of SystemsideProchot# threshold.

<10>

<11>

<12>

<13>

0 = Add 0mA of SystemsideProchot# threshold.

1 = Add 1024mA of SystemsideProchot# threshold.

0 = Add 0mA of SystemsideProchot# threshold.

1 = Add 2048mA of SystemsideProchot# threshold.

0 = Add 0mA of SystemsideProchot# threshold.

1 = Add 4096mA of SystemsideProchot# threshold.

0 = Add 0mA of SystemsideProchot# threshold.

1 = Add 8192mA of SystemsideProchot# threshold.

<15:14>

Not used

Maximum

<13:8> = 110010, 12800mA

5.6

Setting PROCHOT# Debounce Time and Duration Time

Control2 register Bit<10:9> configures the PROCHOT# signal debounce time before its assertion for

ADPsideProchot# and SystemsideProchot#.

Control2 register Bit<8:6> configures the minimum duration of Prochot# signal once asserted.

5.7

Control Registers

Control0, Control1, Control2, Control3, and Control4 registers configure the operation of the ISL95338. To change

certain functions or options after POR, write a 16-bit control command to Control0 register (0x39H or 0b00111001),

and a 16-bit control command to Control1 register (0x3CH or 0b00111100), Control2 register (0x3DH or

0b00111101), Control3 register (0x4CH or 0b00111100), or Control4 register (0x4EH or 0b00111101) using the

Write-word protocol shown in Figure 5 and the data format shown in Tables 10, 11, 12, 13, and 14, respectively.

Table 10. Control0 Register 0x39H

Bit

Bit Name

Description

<15:13> Forward Buck and

Buck-boost Phase

Comparator Threshold

Offset

Bit<15:13> adjusts phase comparator threshold offset for forward buck and buck-boost

000 = 0mV

001 = 1mV

010 = 2mV

011 = 3mV

100 = -4mV

101 = -3mV

110 = -2mV

111 = -1mV

<12:10> Forward and Reverse

Boost Phase

Bit<12:10> adjusts phase comparator threshold offset for forward and reverse boost

000 = 0mV

Comparator Threshold

Offset

001 = 0.5mV

010 = 1mV

011 = 1.5mV

100 = -2mV

101 = -1.5mV

110 = -1mV

111 = -0.5mV

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Table 10. Control0 Register 0x39H

Bit

Bit Name

Description

<9:7>

Reverse Buck and

Buck-boost Phase

Comparator Threshold

Offset

Bit<9:7> adjusts phase comparator threshold offset for reverse buck and buck-boost

000 = 0mV

001 = 1mV

010 = 2mV

011 = 3mV

100 = -4mV

101 = -3mV

110 = -2mV

111 = -1mV

<6:5>

High-Side FET Short

Detection Threshold

Bit<6:5> configures the high-side FET short detection PHASE node voltage threshold during

low-side FET turning on.

00 = 400mV (default)

01 = 500mV

10 = 600mV

11 = 800mV

<4:3>

<2>

Not used

Disable Input Voltage

Regulation Loop

Bit<2> disables or enables the input voltage regulation loop.

0 = Enable input voltage regulation loop (default)

1 = Disable input voltage regulation loop

<1>

<0>

ADP Side Discharge

Bit<1> enable or disable ADP side charger function

0 = Disable (default)

1 = Enable

System Side Discharge Bit<0> enable or disable system side charger function

0 = Disable (default)

1 = Enable

Table 11. Control1 Register 0x3CH

Bit

Bit Name

Description

<15>

Disable Diode-

Emulation Comparator

Bit<15> enables or disables diode-emulation comparator.

0 = Diode-emulation comparator enabled (default)

1 = Diode-emulation comparator disabled

<14>

<13>

Allow Sinking Current

During Negative DAC

Transition

Bit<14> enables or disables sinking current during negative DAC transition.

0 = Sinking current during negative DAC transition enabled (default)

1 = Sinking current during negative DAC transition disabled

Skip Trim During Restart Bit<13> enables or disables trim read during restart. Make sure to program this bit when PGOOD

is high.

0 = Read trim during restart

1 = Skip trim during restart

<12>

Skip Autozero During

Restart

Bit<12> enables or disables autozero during restart. Make sure to program this bit when PGOOD

is high.

0 = Autozero during restart

1 = Skip autozero during restart

<11>

<10>

Reverse Mode Function Bit<11> enables or disables Force Reverse mode function.

0 = Disable Force Reverse mode function (default)

1 = Enable Force Reverse mode function

Audio Filter

Bit<10> enables or disables the audio filter function. No audio filter function in Buck-Boost mode.

0 = Disable (default)

1 = Enable

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Table 11. Control1 Register 0x3CH (Continued)

Description

Bit

Bit Name

<9:7>

Switching Frequency

Bit<9:7> configures the switching frequency.

000 = 1000khz

001 = 910kHz

010 = 850kHz

011 = 787kHz

100 = 744kHz

101 = 695kHz

110 = 660kHz

111 = 620kHz

<6>

<5>

Not used

Disable System Side

Current-Amp When in

Bit<5> enables or disables the system side current amplifier when in FWD mode without ADP.

0 = Enable system side current amplifier (default)

FWD Mode without ADP 1 = Disable system side current amplifier

<4>

<3>

<2>

Bypass Mode

Bit<4> enables or disables the Bypass mode.

0 = Disable (default)

1 = Enable

Fast REF mode

Bit<3> enables or disables the fast REF mode.

0 = Disable (default)

1 = Enable

Stop Switching in FWD Bit<2> enables or disables the buck-boost switching V_OUToutput. When disabled, ISL95338

Mode

stops switching and REF drops to OV. Only valid in Forward mode.

0 = Enable switching (default)

1 = Disable switching

<1>

<0>

OV Enable or Disable

During Slew-Down

Bit<1> enable or disable OV fault when VDAC slew rate down in Forward and Reverse mode.

0 = Enable OV (default)

1 = Disable OV

Force 5.04V VDAC

Bit<0> enable or disable force 5.04VDAC in Forward and Reverse mode.

0 = Disable force 5.04V VDAC (default)

1 = Enable force 5.04V VDAC

Table 12. Control2 Register 0x3DH

Description

Bit

Bit Name

<15>

OV Control

OV enable or disable

0 = Enable OV (default)

1 = Disable OV

<14>

<13>

UV Control

Bit<14> enable or disable UV

0 = Enable UV (default)

1 = Disable UV

Fault Restart Debounce

for Reverse Enable

Bit<13> configures fault restart debounce for reverse enable.

0 = Debounce time is 1.3s (default)

1 = Debounce time is 150ms

<12>

Fault Restart Debounce

Bit<13> configures fast fault restart debounce.

0 = Debounce time is 1.3s or 150ms, depends on bit<13> setting (default)

1 = Debounce time is 200us or 10us, depends on bit<13> setting

<11>

Forward Restart

Debounce for Forward

Enable

Bit<13> configures fault restart debounce for forward enable.

0 = Debounce time is 1.3s (default)

1 = Debounce time is 150ms

<10:9>

PROCHOT# Debounce

Bit<10:9> configures the Prochot# debounce time before its assertion for ADPsideProchot#

and SystemsideProchot#.

00: 7µs (default)

01: 100µs

10: 500µs

11: 1ms

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Table 12. Control2 Register 0x3DH (Continued)

Description

Bit

Bit Name

<8:6>

PROCHOT# Duration

Bit<8:6> configures the minimum duration of Prochot# signal once asserted.

000 = 10ms (default)

001 = 20ms

010 = 15ms

011 = 5ms

100 = 1ms

101 = 500µs

110 = 100µs

111 = 0s

<5>

<4>

Not used

Reverse Fast Swap

Forward Fast Swap

Bit<4> configures reverse fast swap.

0 = Disable reverse fast swap (default)

1 = Enable reverse fast swap

<3>

Bit<3> configures forward fast swap.

0 = Disable forward fast swap (default)

1 = Enable forward fast swap

<2>

<1>

Not used

Disable WOC Fault

Bit<1> enables and disables WOC fault.

0 = Enable WOC (default)

1 = Disable WOC

<0>

System Side WOC

Threshold

Bit<0> configures the System Side WOC fault comparator value.

0 = 20mV (default)

1 = 30mV

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Table 13. Control3 Register 0x4CH

Bit

Bit Name

Description

<15>

Re-Read PROG Pin

Resistor

Bit<15> re-read PROG pin resistor or not before switching.

0 = Re-read PROG pin resistor (default)

1 = Do not re-read PROG pin resistor

<14>

<13>

<12>

Not used

Reverse Startup

Debounce Time

Bit<12> configures startup debounce time for reverse mode.

0 = Debounce time is 200us (default)

1 = Debounce time is 10us

<11>

Forward Startup

Debounce Time

Bit<11> configures startup debounce time for forward mode.

0 = Debounce time is 200us (default)

1 = Debounce time is 10us

<10:8>

Force Operating Mode

Bit<10:8> enables or disables Force Operating mode.

0XX: No effect

100: No switching, do not use

101: Buck mode

110: Boost mode

111: Buck-Boost mode

<7>

<6>

Not used

Current Loop Feedback

Gain

Bit<6> configures current loop feedback gain for high current.

0 = Gain x 1 (default)

1 = Gain x 0.5

<5>

Input Current Limit Loop

Bit<5> disables input current limit loop.

0 = Enable input current limit loop (default)

1 = Disable input current limit loop

<4>

<3>

Not Used

Not used

Disabled REF Amplifier

for Use with External

Reference

Bit<5> disables REF amplifier.

0 = Enable REF amplifier (default)

1 = Disable REF amplifier

<2>

<1>

<0>

Digital Reset

Bit<2> resets all SMBus register values to POR default value and restarts switching.

0 = Idle (default)

1 = Reset

Buck-Boost Switching

Period

Bit<1> configures switching period in Buck-Boost mode.

0 = Period x 1 (default)

1 = Period x 2 (half switching frequency)

PGOOD Setting

Bit<0> configures PGGOD assert condition.

0 = PGOOD suppressed until VREF equals to VDAC (default)

1 = PGOOD assert when switching starts

Table 14. Control4 Register 0x4EH

Bit

<15:8>

7

Bit Name

Description

Not used

Reverse Mode Current

PROCHOT#

Bit<7> enables or disables trigger PROCHOT# with current in Reverse mode.

0 = Enable (default)

1 = Disable

6

Forward Sleep Mode

Bit<7> enables or disables Chip Sleep mode in Forward mode regardless of ADP voltage.

RVSEN pin or Control1 bit <11> can override this function.

0 = Disable (default)

1 = Enable

<5:2>

Not used

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Table 14. Control4 Register 0x4EH (Continued)

Description

Bit

Bit Name

1

PROCHOT# Clear

Bit<1> clears PROCHOT#.

0 = Idle (default)

1 = Clear PROCHOT#

0

PROCHOT# Latch

Bit<0> manually resets PROCHOT#.

0 = PROCHOT# signal auto-clear

1 = hold PROCHOT# low once tripped

5.8

Regulating Voltage Register in Reverse Mode

The ReverseRegulatingVoltage register contains SMBus readable and writable Reverse mode output regulation

voltage reference. The default value is 5.004V. This register accepts any voltage command but only the valid

register bits will be written to the register. However, the register shouldn’t be programmed higher than the

recommended operating voltage.

In Reverse mode, the user also can configure the regulating output voltage on the ADP side by setting the external

voltage divider on the ADP pin, without changing the ReverseRegulatingVoltage register value.

Table 15. ReverseRegulatingVoltage Register 0x49H

Bit

<2:0>

<3>

Description

Not used

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 12mV of regulating voltage in Reverse mode.

<4>

<5>

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 24mV of regulating voltage in Reverse mode.

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 48mV of regulating voltage in Reverse mode.

<6>

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 96mV of regulating voltage in Reverse mode.

<7>

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 192mV of regulating voltage in Reverse mode.

<8>

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 384mV of regulating voltage in Reverse mode.

<9>

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 768mV of regulating voltage in Reverse mode.

<10>

<11>

<12>

<13>

<14>

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 1536mV of regulating voltage in Reverse mode.

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 3072mV of regulating voltage in Reverse mode.

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 6144mV of regulating voltage in Reverse mode.

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 12288mV of regulating voltage in Reverse mode.

0 = Add 0mV of regulating voltage in Reverse mode.

1 = Add 24576mV of regulating voltage in Reverse mode.

<15>

Not used

27456mV

Maximum

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5. ISL95338 SMBus Commands

5.9

Output Current Limit Register in Reverse Mode

The ReverseCurrentLimit register contains SMBus readable and writable reverse current limit. The default is

512mA. This register accepts any current command, but only the valid register bits will be written to the register. The

maximum values are clamped at 4096mA for R = 20mΩ.

s1

Table 16. ReverseCurrentLimit Register 0x4AH

Bit

<6:0>

<7>

Description

Not used

0 = Add 0mA of output current limit in Reverse mode.

1 = Add 128mA of output current limit in Reverse mode.

<8>

<9>

0 = Add 0mA of output current limit in Reverse mode.

1 = Add 256mA of output current limit in Reverse mode.

0 = Add 0mV of output current limit in Reverse mode.

1 = Add 512mA of output current limit in Reverse mode.

<10>

<11>

<12>

0 = Add 0mV of output current limit in Reverse mode.

1 = Add 1024mA of output current limit in Reverse mode.

0 = Add 0mV of output current limit in Reverse mode.

1 = Add 2048mA of output current limit in Reverse mode.

0 = Add 0mV of output current limit in Reverse mode.

1 = Add 4096mA of output current limit in Reverse mode.

<15:13>

Not used

4096mA

Maximum

5.10 Input Voltage Limit Register

The InputVoltageLimit register contains SMBus readable and writable input voltage limits. The default is 4.096V.

This register accepts any command, but only the valid register bits will be written to the register. The maximum

values are clamped at 18V.

Table 17. InputVoltageLimit Register 0x4BH

Bit

<7:0>

<8>

Description

Not used

0 = Add 0mV of input voltage limit.

1 = Add 512mV of input voltage limit.

<9>

0 = Add 0mA of input voltage limit.

1 = Add 1024mV of input voltage limit.

<10>

<11>

<12>

<13>

0 = Add 0mV of input voltage limit.

1 = Add 2048mV of input voltage limit.

0 = Add 0mV of input voltage limit.

1 = Add 4096mV of input voltage limit.

0 = Add 0mV of input voltage limit.

1 = Add 8192mV of input voltage limit.

0 = Add 0mV of input voltage limit.

1 = Add 16384mV of input voltage limit.

<15:14>

Not used

18000mV

Maximum

FN8896 Rev.2.00

Nov 30, 2017

Page 32 of 48

ISL95338

5. ISL95338 SMBus Commands

5.11 Information Register

The Information Register contains SMBus readable information about manufacture and operating modes.

Tables 18 and 19 identify the bit locations of the information available.

Table 18. Information1 Register 0x3AH

Bit

Description

<3:0>

<4>

Not used

<6:5>

<9:7>

<10>

<11>

Bit<11> indicates if SystemSideProchot# is tripped or not.

0 = SystemSideProchot# is not tripped

1 = SystemSideProchot# is tripped

<12>

Bit<12> indicates if ADPsideProchot# is tripped or not.

0 = ADPSideProchot# is not tripped

1 = ADPSideProchot# is tripped

<14:13>

Bit<14:13> indicates the active control loop.

00 = Voltage control loop is active

01 = System current loop is active

10 = ADP current limit loop is active

11 = Input voltage loop is active

<15>

Bit<15> indicates if the internal reference circuit is active or not. Bit<15> = 0 indicates that ISL95338 is in low

power mode.

0 = Reference is not active

1 = Reference is active

Table 19. Information2 Register 0x4DH

Bit

Description

<4:0>

<7:5>

Program Resister read out

Bit<7:5> indicates the ISL95338 operation mode.

001: Forward Boost

010: Forward Buck

011: Forward Buck-Boost

101: Reverse Boost

110: Reverse Buck

111: Reverse Buck-Boost

<11:8>

Bit<11:8> indicates the ISL95338 state machine status.

0000 = OFF

0010 = ADP

0100 = VSYS

0110 = Enable Reverse mode

1000 = Enable LDO5

1110 = WAIT

<12>

<13>

<14>

Not used

Bit<14> indicates forward switching enable.

0 = Not enabled

1 = Enabled

<15>

Not used

FN8896 Rev.2.00

Nov 30, 2017

Page 33 of 48

ISL95338

6. Application Information

6.1

R3 Modulator

COMP

+

-

S

R

V

CR

PWM

Q

L

PWM

V

O

+

-

VW

PHASE

V

W

I

L

C

O

HYSTERETIC

WINDOW

+

GM

V

CR

-

C

R

COMP

Figure 25. R3 Modulator Operation Principles in Steady

State

Figure 24. R3 Modulator

PWM

PHASE

VW

UGATE

LGATE

COMP

VCR

IL

Figure 26. R3 Modulator Operation Principles in

Dynamic Response

Figure 27. Diode Emulation

FN8896 Rev.2.00

Nov 30, 2017

Page 34 of 48

ISL95338

6. Application Information

CCM/DCM BOUNDARY

VW

V_CR

I_L

LIGHT DCM

VW

V_CR

I_L

DEEP DCM

VW

V_CR

I_L

Figure 28. Period Stretching

The ISL95338 uses Intersil’s patented Robust Ripple Regulator (R3) modulation scheme. The R3 modulator

combines the best features of fixed frequency PWM and hysteretic PWM, while eliminating many of their

shortcomings. Figure 24 on page 34 conceptually shows the R3 modulator circuit and Figure 25 on page 34 shows

the operation principles in steady state.

The fixed voltage window between VW and COMP is called the VW window in the following discussion. The

modulator charges the ripple capacitor C with a current source equal to g (V - V ) during PWM on-time and

R

m

IN

O

discharges the ripple capacitor C with a current source equal to g V during PWM off-time, where g is a gain

R

m

O

m

factor. The C voltage V , therefore, emulates the inductor current waveform. The modulator turns off the PWM

r

CR

pulse when V reaches VW and turns on the PWM pulse when it reaches COMP.

CR

Because the modulator works with V , which is a large amplitude and noise-free synthesized signal, it achieves

cr

lower phase jitter than a conventional hysteretic mode modulator.

Figure 26 on page 34 shows the operation principles during dynamic response. The COMP voltage rises during

dynamic response, turning on PWM pulses earlier and more frequently temporarily, which allows for higher

control loop bandwidth than a conventional fixed frequency PWM modulator at the same steady-state switching

frequency.

The R3 modulator can operate in Diode Emulation (DE) mode to increase light-load efficiency. For example, in

Buck DE mode the low-side MOSFET conducts when the current is flowing from source-to-drain and does not

allow reverse current, emulating a diode. As shown in Figure 27 on page 34, when LGATE is on, the low-side

MOSFET carries current, creating negative voltage on the phase node due to the voltage drop across the

ON-resistance. The IC monitors the current by monitoring the phase node voltage. It turns off LGATE when the

phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating

unnecessary power loss. Similar operations apply for other modes, such as Boost and Buck-boost mode.

If the load current is light enough, as Figure 27 shows, the inductor current will reach and stay at zero before the

next phase node pulse. At this stage, the regulator is in Discontinuous Conduction Mode (DCM). If the load current

is heavy enough, the inductor current will never reach 0A and the regulator will be in CCM, although the controller

will be in DE mode.

Figure 28 shows the operation principle in Diode Emulation mode at light load. The load gets incrementally lighter

in the three cases from top to bottom. The PWM on-time is determined by the VW window size, therefore, it is the

same, making the inductor current triangle the same in the three cases. The R3 modulator clamps the ripple

FN8896 Rev.2.00

Nov 30, 2017

Page 35 of 48

ISL95338

6. Application Information

capacitor voltage V in DE mode to make it mimic the inductor current. It takes the COMP voltage longer to hit

CR

V

, naturally stretching the switching period. The inductor current triangles move further apart from each other,

CR

such that the inductor current average value is equal to the load current. The reduced switching frequency helps

increase light-load efficiency.

6.2

ISL95338 Bidirectional Buck-Boost Voltage Regulator

The ISL95338 bidirectional buck-boost voltage regulator drives an external N-channel MOSFET bridge comprised

of two transistor pairs as shown in Figure 2. The first pair, Q1 and Q2, is a buck arrangement with the transistor

center tap connected to an inductor “input”, as is the case with a buck converter in Forward mode. The second

transistor pair, Q3 and Q4, is a boost arrangement with the transistor center tap connected to the same inductor’s

“output”, as is the case with a boost converter in Forward mode. This arrangement supports the same operation

mode in reverse direction.

• In Forward Buck mode, Q1 and Q2 turn on and off alternatively, while Q3 remains off and Q4 remains on.

• In Forward Boost mode, Q3 and Q4 turn on and off alternatively, while Q1 remains on and Q2 remains off.

• In Forward Buck-Boost mode, Q1 and Q3 turn on at the same time, Q3 turns off and Q4 turns on, Q1 turns off and

Q2 turns on, and after Q2 and Q4 turn off at the same time, and Q1 and Q3 turn on again.

• In Forward Bypass mode, Q1 and Q4 are always on, while Q2 and Q3 are always off.

• In Reverse Buck mode, Q3 and Q4 turn on and off alternatively, while Q2 remains off and Q1 remains on.

• In Reverse Boost mode, Q1 and Q2 turn on and off alternatively, while Q4 remains on and Q3 remains off.

• In Reverse Buck-Boost mode, Q4 and Q2 turn on at the same time, Q2 turns off and Q1 turns on, Q4 turns off and

Q3 turns on, and after Q3 and Q1 turn off at the same time and Q4 and Q2 turn on again.

• In Reverse Bypass mode, Q1 and Q4 are always on, except during the needed refresh time, while Q2 and Q3 are

always off.

• In Reverse mode the output sensing point is CSIP pin.

Table 20. Operation Mode

Mode

Forward Buck

Q1

Control FET

ON

Q2

Sync. FET

OFF

Q3

OFF

Q4

ON

Forward Boost

Control FET

OFF

Sync. FET

ON

Forward Buck-Boost

Forward Bypass

Reverse Buck

Control FET

ON

Sync. FET

OFF

ON

OFF

Sync. FET

OFF

Control FET

ON

Reverse Boost

Sync. FET

ON

Control FET

OFF

Reverse Buck-Boost

Reverse Bypass

Sync. FET

OFF

Control FET

ON

5_6ꢀ

&6,1

9$'3

&6,3

9287

5_6ꢂ

&621 6<67(0

/2$'

&623

4ꢃ

4ꢁ

4ꢀ

4ꢂ

/ꢀ

Figure 29. Buck-Boost Regulator Topology

FN8896 Rev.2.00

Nov 30, 2017

Page 36 of 48

ISL95338

6. Application Information

The ISL95338 optimizes the operation mode transition algorithm by considering the input and output voltage ratio

and the load condition. When ADP voltage V is rising and is higher than 94% of the system bus voltage VSYS,

ADP

the ISL95338 will transit from Boost mode to Buck-Boost mode. If V

is higher than 120% of VSYS, the

ADP

ISL95338 will transit from Buck-Boost mode to Buck mode under any circumstance. At a heavier load, the mode

transition point changes accordingly to accommodate the duty cycle change due to the power loss on the voltage

regulator circuit.

When the ADP voltage V

is falling and is lower than 106% of the system bus voltage VSYS, the ISL95338 will

ADP

transit from Buck mode to Buck-Boost mode. If V

is lower than 80% of VSYS, the ISL95338 will transit from

ADP

Buck-Boost mode to Boost mode.

VADP

BUCK

120%

BUCK-BOOST

106%

VSYS

94%

BUCK-BOOST

BOOST

80%

BOOST

VADP

Figure 30. Operation Mode

When the reverse function is enabled with the SMBus command or RVSEN pin, and if reverse voltage VSYS is

higher than 4.1V, the ISL95338 operates in Reverse mode.

The customer can enable Bypass mode with Control1 register Bit 4. When the Bypass mode control bit is enabled,

the REF will ramp to the input voltage, and the switcher will continue switching until the output voltage is in the

300mV window to the input. When the regulating voltage is within the 300mV window to the input voltage, the

latch will be set to stop the switching, Q1 and Q4 will be always on while Q2 and Q3 will be always off, and UV

and OV will be disabled. To exit Bypass mode, unprogram control1 register Bit 4, then the REF will ramp to DAC

and the switching will resume.

6.3

Soft-Start

The ISL95338 includes a low power LDO with nominal 5V output, which input is OR-ed from the VOUT pin and

ADP pin. The ISL95338 also includes a high power LDO with nominal 5V output, which input is from the DCIN

pin connected to the ADP and the system bus, through an external OR-ing diode circuit. Both LDO outputs are tied

to the VDD pin to provide the bias power and gate drive power for ISL95338. The VDDP pin is the ISL95338 gate

drive power supply input. Use an R-C filter to generate the VDDP pin voltage from the VDD pin voltage.

When VDD > 2.7V, the ISL95338 digital block is activated. The soft-start time can be set by the external capacitor

on REF pin. The ISL95338 sources 1µA current out of the REF pin to charge this external capacitor. Its voltage will

be used as the output voltage reference in the soft-start procedure.

6.4

Programming Options

The resistor from the PROG pin to GND programs the forward output voltage configuration of the ISL95338.

Table 21 shows the programing options.

FN8896 Rev.2.00

Nov 30, 2017

Page 37 of 48

ISL95338

6. Application Information

Table 21. Prog Pin Programming Options

Prog-GND

Resistance

(kΩ)

Default Forward

Min

0

Max

28

Regulating Voltage

5.004

35.7

82.5

147

237

71.5

133

215

open

9.000

12.000

16.008

20.004

The switching frequency can be changed through SMBus Control1 register Bit<9:7> after POR. Refer to SMBus

Control1 register programming table for a detailed description.

After POR, the ISL95338 will source 10µA current out of the PROG pin and read the PROG pin voltage to determine

the resistor value. If ISL95338 is powered up from reverse side, it will not read PROG resistor. Once FRWEN is

enabled, ISL95338 will reset the forward regulating voltage register to its default values according to the PROG

pin setting.

By default, the ADP current-sensing resistor R is 20mΩ and VSYS current-sensing resistor R is 10mΩ. Using

s1

s2

these R = 20mΩand R = 10mΩ options would result in 4mA/LSB correlation in the SMBus current commands.

s1

s2

If R and R values are different from these R = 20mΩand R = 10mΩ options, the SMBus command needs to

s1

s2

s1

s2

be scaled accordingly to obtain the correct current. Smaller current-sense resistor values reduce the power loss

whereas larger current-sense resistor values give better accuracy.

The illustration in this datasheet is based on current-sensing resistors R = 20mΩ and R = 10mΩ unless specified

s1

s2

otherwise.

6.5

DE Operation

In DE mode of operation, the ISL95338 employs a phase comparator to monitor the PHASE node voltage to the

ground or VOUT or ADP voltage during the low-side switching FET on-time to detect the inductor current zero

crossing, depending on the operation mode (Buck, Buck-Boost and Boost) and power delivery direction (Forward

or reverse direction), refer to the Table 22. The phase comparator needs a minimum on-time of the low-side

switching FET for it to recognize inductor current zero crossing. If the low-side switching FET on-time is too short

for the phase comparator to successfully recognize the inductor zero crossing, the ISL95338 may lose diode

emulation ability. To prevent such a scenario, the ISL95338 employs a minimum low-side switching FET on-time.

When the intended low-side switching FET on-time is shorter than the minimum value, the ISL95338 stretches the

switching period to keep the low-side switching FET on-time at the minimum value, which causes the CCM

switching frequency to drop below the set point.

Table 22. Voltage Comparator for DE Operation

Mode

Buck

Direction

Forward

Reverse

Voltage Comparator

PHASE 1to GND

PHASE 1to VOUT

PHASE 2 to GND

PHASE 1to ADP

Boost

Buck-Boost

Buck

Boost

Buck-Boost

FN8896 Rev.2.00

Nov 30, 2017

Page 38 of 48

ISL95338

6. Application Information

6.6

Forward Mode

When the forward function is enabled with the SMBus command or FRWEN pin (voltage is higher than 0.8V) and

DCIN is powered by ADP, and if the ADP is plugged in and its value is higher than 4.1V, the ISL95338 can operate

in Forward Buck mode, Forward Boost mode, Forward Buck-Boost mode, or Forward Bypass mode. After the

forward output voltage reaches the regulating output voltage range set by register 0X15H Bit<14:3>, forward

power-good FWGPG will assert to High.

6.7

Reverse Mode for USB OTG (On-the-Go)

When the reverse function is enabled with the SMBus command (Control1 Bit 11) or RVSEN pin, and if an

external voltage is on system side and its value is higher than 4.1V, the ISL95338 can operate in Reverse Buck

mode, Reverse Boost mode, Reverse Buck-Boost mode, or Reverse Bypass mode. RVSEN is the digital input pin.

The 1.3s or 150ms debounce time can be set by Control2 register Bit<13>. After the reverse output voltage reaches

the output voltage set by register 0X49H Bit<14:3>, reverse power-good RVSPG will assert to High.

Before Reverse mode starts switching, the CSIP pin voltage needs to drop below the reverse output overvoltage

protection threshold (ReverseRegulatingVoltage + 1177mV) first.

The default reverse output voltage is 5V and programmable up to 20V in Reverse Buck, Reverse Buck-Boost, and

Reverse Boost mode. In Reverse Bypass mode, the maximum value of reverse output voltage is programmable up

to 20V. The reverse voltage register 0X49H can be used to configure the reverse output voltage.

6.8

Fast REF

To achieve fast REF in some applications, the fast REF function can be programmed by Control1 Bit3. If this bit is

programmed, 1uA current source for REF pin will be replaced with 5k impedance to get faster transitions for REF

voltage.

6.9

Fast Swap

The ISL95338 provides fast swap function in Forward mode and Reverse mode. Users can implement the fast swap

function in Forward mode in one of two ways (pin reverse or software reverse) by following the steps below:

• Pin reverse fast swap enable:

(1) Program Control2 Bit4 (Reverse Fast Swap).

(2) Skip trim during restart by programming control1 Bit 13.

(3) Skip autozero during restart by programming control1 Bit 12.

(4) Enable RVSEN pin.

• Software reverse fast swap enable:

(1) Program Control1 Bit0 (Force 5.04V VDAC).

(2) Program Control1 Bit3 (Fast REF).

(3) Skip trim during restart with programming control1 Bit 13.

(4) Skip autozero during restart with programming control1 Bit 12.

(5) Program Control1 Bit11 (Force Reverse mode).

Similarly, users can implement the fast swap function in Reverse mode in one of two ways (pin reverse or software

reverse) by following the steps below:

• Pin forward fast swap enable:

(1) Program Control2 Bit3 (Forward Fast Swap).

(2) Skip trim during restart by programming control1 Bit 13.

(3) Skip autozero during restart by programming control1 Bit 12.

(4) Disable RVSEN pin.

(5) Enable FWREN pin.

• Software forward fast swap enable:

FN8896 Rev.2.00

Nov 30, 2017

Page 39 of 48

ISL95338

6. Application Information

(1) Program Control1 Bit0 (Force 5.04V VDAC).

(2) Program Control1 Bit3 (Fast REF).

(3) Skip trim during restart by programming control1 Bit 13.

(4) Skip autozero during restart by programming control1 Bit 12.

(5) Un-program Control1 Bit11 (Force Reverse mode).

6.10 Way Overcurrent Protection (WOCP)

The ISL95338 provides Way Overcurrent Protection (WOCP) against the MOSFET short, system side and ADP

side short, and inductor short scenarios. The ISL95338 monitors the CSIP-CSIN voltage and CSON-CSOP voltage

and compares them to the WOCP threshold 12A for ADP current and 20A for system side current in Forward

mode.

When the WOC comparator is tripped, the ISL95338 counts one time within each 10µs window. If the ISL95338

counts WOC to 7 times in 50ms, it stops switching immediately. After the 1.3s or 150ms debounce time is set by

Control2 register Bit<12>, the ISL95338 goes through the start-up sequence to retry.

The WOCP function can be disabled through Control2 register Bit<1>.

6.11 ADP Input Overvoltage Protection

If the ADP pin input voltage exceeds 26.4V for more than 10µs, the ISL95338 will declare an ADP overvoltage

condition and stop switching. When the ADP voltage drops below 25.608V for more than 100µs, the ISL95338

will start to switch.

6.12 System Output Overvoltage Protection

The ISL95338 provides system rail output overvoltage protection. If the system voltage VOUTS is 1095mV higher

than the ForwardRegulatingVoltage register set value for more than 100us, it will declare the system overvoltage,

de-assert FWRPG, and stop switching. It will resume switching with the 100us debounce when VOUTS is less than

542mV plus the setting reference voltage for forward.

6.13 System Output Undervoltage Protection

The ISL95338 provides system rail output undervoltage protection. If the system voltage VOUTS is 818mV lower

than the ForwardRegulatingVoltage register set value for more than 1ms, it will declare the system undervoltage,

de-assert FWRPG, and restart.

6.14 ADP Output Overvoltage Protection

The ISL95338 provides ADP rail output overvoltage protection. If the ADP voltage ADPS is 1177mV higher than

the ReverseRegulatingVoltage register set value for more than 100us, it will declare the ADP overvoltage, de-assert

RVSPG, and stop switching. The ISL95338 will resume switching with the 100us debounce when ADPS is less

than 583mV plus the setting reference voltage for reverse.

6.15 ADP Output Undervoltage Protection

The ISL95338 provides ADP rail output undervoltage protection. If the ADP voltage VADPS is 1177mV lower

than the ReverseRegulatingVoltage register set value for more than 1ms, it will declare the ADP undervoltage, de-

assert RVSPG, and stop switching.

6.16 Over-Temperature Protection

The ISL95338 will stop switching for self protection when the junction temperature exceeds +140°C.

When the temperature falls below +120°C, and after a 100µs delay, the ISL95338 will start switching.

FN8896 Rev.2.00

Nov 30, 2017

Page 40 of 48

ISL95338

6. Application Information

6.17 Switching Power MOSFET Gate Capacitance

The ISL95338 includes an internal 5V LDO output at the VDD pin, which can be used to provide the switching

MOSFET gate driver power through the VDDP pin with an R-C filter. The 5V LDO output overcurrent protection

threshold is 115mA nominal. When selecting the switching power MOSFET, the MOSFET gate capacitance should

be considered carefully to avoid overloading the 5V LDO, especially in Buck-Boost mode when four MOSFETs

are switching at the same time. For one MOSFET, the gate drive current can be estimated by Equation 1:

(EQ. 1)

I

= Q  f

g

SW

driver

where:

• Q is the total gate ADP which can be found in the MOSFET datasheet

g

• f is switching frequency

SW

6.18 ADP Side Input Filter

The ADP cable parasitic inductance and capacitance could cause some voltage ringing or an overshoot spike at the

ADP connector node when the ADP is hot plugged in. This voltage spike could damage the ISL95338 pins

connecting to the ADP connector node. One low cost solution is to add an RC snubber circuit at the ADP connector

node to clamp the voltage spike as shown in Figure 31. A practical value of the RC snubber is 2.2Ω to 2.2µF;

however, the appropriate values and power rating should be carefully characterized based on the actual design.

Additionally, it is not recommended to add a pure capacitor at the ADP connector node, which can cause an even

bigger voltage spike due to the ADP cable or the ADP current path parasitic inductance.

ADAPTER

CONNECTOR

R_i

2.2

C_i

ACIN

2.2µF

RC SNUBBER

ISL95338

Figure 31. Adapter Input RC Snubber Circuit

FN8896 Rev.2.00

Nov 30, 2017

Page 41 of 48

ISL95338

7. General Application Information

This design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase

power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in

the following section. In addition to this guide, Intersil provides complete reference designs that include

schematics, bill of materials, and example board layouts.

7.1

Select the LC Output Filter

The duty cycle of an ideal buck converter in CCM is a function of the input and the output voltage. This

relationship is written by Equation 2:

V

OUT

(EQ. 2)

(EQ. 3)

---------------

D =

V

IN

The output inductor peak-to-peak ripple current is written by Equation 3:

V

OUT ^{ 1 – D}

-------------------------------------

=

I

P-P

f

SW ^{ L}

A typical step-down DC/DC converter will have an I of 20% to 40% of the maximum DC output load current for

P-P

a practical design. The value of I is selected based upon several criteria such as MOSFET switching loss,

P-P

inductor core loss, and the resistive loss of the inductor winding.

The DC copper loss of the inductor can be estimated by Equation 4:

2

(EQ. 4)

P

= I

 DCR

COPPER

LOAD

where I

is the converter output DC current.

LOAD

The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider

when choosing the inductor is its saturation characteristics at elevated temperatures. A saturated inductor could

cause destruction of circuit components.

A DC/DC buck regulator must have output capacitance C , into which ripple current I can flow. Current I

P-P

O

P-P

develops a corresponding ripple voltage V across C which is the sum of the voltage drop across the capacitor

P-P

O,

ESR and of the voltage change stemming from ADP moved in and out of the capacitor. These two voltages are

written by Equations 5 and 6:

(EQ. 5)

V

= I

P-P ^{ ESR}

ESR

I

P-P

-----------------------------

(EQ. 6)

V

=

C

8 C

O ^{ f}

SW

If the output of the converter has to support a load with high pulsating current, several capacitors will need to be

paralleled to reduce the total ESR until the required V is achieved. The inductance of the capacitor can cause a

P-P

brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors should be

considered in this scenario. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that

I

is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS

P-P

current at f . Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage

SW

across it increases.

FN8896 Rev.2.00

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Page 42 of 48

ISL95338

7. General Application Information

7.2

Select the Input Capacitor

The important parameters for the input capacitance are the voltage rating and the RMS current rating. For reliable

operation, select capacitors with voltage and current ratings above the maximum input voltage and capable of

supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25 times

greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. The “Typical

Application Circuit” on page 2 is a graph of the input capacitor RMS ripple current, normalized relative to output

load current, as a function of duty cycle and is adjusted for converter efficiency. The normalized RMS ripple

current calculation is written as Equation 7:

2

D  k

12

(EQ. 7)

--------------

 D  1 – D +

-----------------------------------------------------------------------

I

MAX

I

=

RMS,NORMALIZED

C

I

IN

MAX

where:

• I

is the maximum continuous I

of the converter

LOAD

MAX

• k is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a ratio of I

(0 to 1)

MAX

• D is the duty cycle that is adjusted to take into account the efficiency of the converter, which is written as

Equation 8:

V

OUT

 EFF

(EQ. 8)

--------------------------

D =

V

IN

In addition to the capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain

of the high-side MOSFET and the source of the low-side MOSFET.

0.60

0.48

k = 0.25

k = 0.5

k = 0

0.36

k = 1

k = 0.75

0.24

V_S= ±2.5V

0.12

0

0.1

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.2

Duty Cycle

Figure 32. Normalized RMS Input Current at EFF = 1

FN8896 Rev.2.00

Nov 30, 2017

Page 43 of 48

ISL95338

7. General Application Information

7.3

Select the Switching Power MOSFET

Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain-to-source voltage rating.

The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum

of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET

switches off.

Several power MOSFETs are readily available that are optimized for DC/DC converter applications. The preferred

high-side MOSFET emphasizes low gate ADP so that the device spends the least amount of time dissipating power

in the linear region. Unlike the low-side MOSFET, which has the drain-to-source voltage clamped by its body

diode during turn off, the high-side MOSFET turns off with a VDS of approximately V - V

, plus the spike

IN

OUT

across it. The preferred low-side MOSFET emphasizes low r

when fully saturated to minimize conduction

DS(ON)

loss. It should be noted that this is an optimal configuration of MOSFET selection for low duty cycle applications

(D < 50%). For higher output, low input voltage solutions, a more balanced MOSFET selection for high- and

low-side devices may be warranted.

For the low-side (LS) MOSFET, the power loss can be assumed to be conductive only and is written as Equation 9:

2

(EQ. 9)

P

 I

 r

DSON_LS ^{ 1 – D}

CON_LS

LOAD

For the high-side (HS) MOSFET, the conduction loss is written as Equation 10:

2

(EQ. 10)

(EQ. 11)

P

= I

 r

DSON_HS ^{ D}

CON_HS

LOAD

For the high-side MOSFET, the switching loss is written as Equation 11:

IN ^{ I}VALLEY ^{ t}SWON ^{ f}

IN ^{ I}PEAK ^{ t}SWOFF ^{ f}

V

SW

------------------------------------------------------------------------------ --------------------------------------------------------------------------

P

=

+

SW_HS

2

where:

• I

is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current

VALLEY

is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current

PEAK

• t

is the time required to drive the device into saturation

SW(ON)

SW(OFF)

• t

is the time required to drive the device into cut-off

7.4

Select the Bootstrap Capacitor

The selection of the bootstrap capacitor is written by Equation 12:

Q

g

-----------------------

(EQ. 12)

C

=

BOOT

V

BOOT

where:

• Q is the total gate ADP required to turn on the high-side MOSFET

g

• V

is the maximum allowed voltage decay across the boot capacitor each time the high-side MOSFET is

BOOT

switched on

As an example, suppose the high-side MOSFET has a total gate ADP Q of 25nC at V = 5V and a V

BOOT

of

g

GS

200mV. The calculated bootstrap capacitance is 0.125µF; for a comfortable margin, select a capacitor that is double

the calculated capacitance. In this example, 0.22µF will suffice. Use an X7R or X5R ceramic capacitor.

FN8896 Rev.2.00

Nov 30, 2017

Page 44 of 48

ISL95338

7. General Application Information

7.5

Select the Resistor Divider for VOUTS and ADPS

ISL95338

VOUTS

VSYS

ADPS

R₄

VADP

R₁

R₂

R₃

1M

1.5M 1.5M

1M

Figure 33. Resistor Divider for VOUTS and ADPS

ADPS and VOUTS are output voltage feedback pins, in Reverse mode and Forward mode, respectively, which

allow the customer to change output voltage by the resistor divider (R , R , and R , R ), as shown in Figure 2.

1

2

3

4

There are two parallel resistors (1M and 1.5M) inside from VOUTS and ADPS to ground. For example, in Forward

mode, VSYS voltage magnitude can be revised by tuning R and R values, written by Equation 13. Thus, there is

1

2

no need to change the Forward Regulating Voltage register (0x15H) through GUI. The same process can be applied

at the ADPS pin.

1.5M\\1M\\R 

2

--------------------------------------------------------

(EQ. 13)

V

= V

SYS

OUTS

1.5M\\1M\\R  + R

2

1

FN8896 Rev.2.00

Nov 30, 2017

Page 45 of 48

ISL95338

8. Revision History

Rev.

2.00

1.00

0.00

Date

Description

Added Way Overcurrent Protection (WOCP) function to datasheet.

Removed Way Overcurrent Protection (WOCP) function

Initial release

Nov 30, 2017

Oct 5, 2017

Aug 15, 2017

FN8896 Rev.2.00

Nov 30, 2017

Page 46 of 48

ISL95338

9. Package Outline Drawing

For the most recent package outline drawing, see L32.4x4A.

9. Package Outline Drawing

L32.4x4A

32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 2/16

8X 0.36

8X 0.179

6

4.00 ±0.05

2.80

6

A

B

PIN 1

PIN #1

28X 0.40

INDEX AREA

8X 0.179

(4X)

0.15

24X 0.40

32X 0.20

4

0.10

M

C

A B

TOP VIEW

BOTTOM VIEW

(3.80)

(2.80)

SEE DETAIL “X”

0.90 ±0.10

//

0.10C

C

BASE PLANE

SEATING PLANE

0.08

C

SIDE VIEW

(28X 0.40)

(32X 0.20)

5

C

0.2 REF

(32X 0.60)

TYPICAL RECOMMENDED LAND PATTERN

0.00 MIN

0.05 MAX

DETAIL “X”

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3. Unless otherwise specified, tolerance: Decimal ±0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.25mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN8896 Rev.2.00

Nov 30, 2017

Page 47 of 48

ISL95338

10. About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The

company's products address some of the largest markets within the industrial and infrastructure, mobile computing,

and high-end consumer markets.

For the most updated datasheet, application notes, related documentation, and related parts, see the respective product

information page found at www.intersil.com.

For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.

You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice,

provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned

to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no

responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8896 Rev.2.00

Nov 30, 2017

Page 48 of 48


型号：	ISL95338EVAL1Z
厂家：	RENESAS TECHNOLOGY CORP
描述：	Bidirectional Buck-Boost Voltage Regulator 开关
文件：	总48页 (文件大小：1808K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL95338EVAL1Z [RENESAS]

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