M306N5MCV-XXXFP [RENESAS]
Renesas MCU; 瑞萨MCU
| 型号： | M306N5MCV-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Renesas MCU |
| 文件： | 总88页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Under development
This document is under development and its contents are subject to change
M16C/6N Group (M16C/6N5)
REJ03B0004-0240
Rev.2.40
Renesas MCU
Aug 25, 2006
1. Overview
The M16C/6N Group (M16C/6N5) of MCUs are built using the high-performance silicon gate CMOS process
using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These
MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of
address space, they are capable of executing instructions at high speed. Being equipped with one CAN
(Controller Area Network) module in the M16C/6N Group (M16C/6N5), the MCU is suited to drive automotive
and industrial control systems. The CAN module complies with the 2.0B specification. In addition, this MCU
contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable
for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/
logic operations.
1.1 Applications
• Automotive, industrial control systems and other automobile, other (T/V-ver. product)
• Car audio and industrial control systems, other (Normal-ver. product)
Specifications written in this manual are believed to be accurate, but are not
guaranteed to be entirely free of error. Specifications in this manual may be
changed for functional or performance improvements. Please make sure your
manual is the latest edition.
Rev.2.40 Aug 25, 2006 page 1 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
1.2 Performance Overview
Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N5).
Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N5)
Specification
Item
Normal-ver.
T/V-ver.
CPU
Number of fundamental
instructions
91 instructions
Minimum instruction
execution time
Operating mode
Address space
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Single-chip, memory expansion, and microprocessor modes
1 Mbyte
Memory capacity
Peripheral Ports
Refer to Table 1.2 Product Information
Input/Output: 87 pins, Input: 1 pin
Timer A: 16 bits ✕ 5 channels
Function
Multifunction timers
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
3 channels
Serial interfaces
(2)
Clock synchronous, UART, I2C-bus (1), IEBus
1 channel
Clock synchronous
A/D converter
D/A converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits ✕ 2 channels
2 channels
CRC calculation circuit
CAN module
Watchdog timer
Interrupts
CRC-CCITT
1 channel with 2.0B specification
15 bits ✕ 1 channel (with prescaler)
Internal: 29 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Electrical
Characteristics
Supply voltage
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Consumption Mask ROM 18 mA (f(BCLK) = 24 MHz,
16 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
18 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
current
PLL operation, no division)
Flash memory 20 mA (f(BCLK) = 24 MHz,
PLL operation, no division)
Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory 0.8 µA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 0.3 V or 5.0 0.5 V
5.0 0.5 V
Version
I/O
Programming and erasure endurance 100 times
I/O withstand voltage
5.0 V
Characteristics Output current
5 mA
Operating Ambient Temperature
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
Device Configuration
Package
CMOS high-performance silicon gate
100-pin molded-plastic QFP, LQFP
NOTES:
1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
Rev.2.40 Aug 25, 2006 page 2 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
System clock generation circuit
A/D converter
(10 bits ✕ 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Timer (16 bits)
On-chip oscillator
UART or
Clock synchronous serial I/O
(3 channels)
Output (timer A): 5
Input (timer B): 6
Clock synchronous serial I/O
(8 bits ✕ 1 channel)
CRC calculation circuit (CCITT)
(Polynomial: X16+X12+X5+1)
CAN module
(1 channel)
Three-phase motor
control circuit
Watchdog timer
(15 bits)
M16C/60 Series CPU core
Memory
R0H
R1H
R0L
R1L
SB
USP
ISP
ROM (1)
RAM (2)
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
Multiplier
D/A converter
(8 bits ✕ 2 channels)
FB
NOTES:
1: ROM size depends on MCU type.
2: RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.2.40 Aug 25, 2006 page 3 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
1.4 Product Information
Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages.
Table 1.2 Product Information
Type No.
ROM Capacity RAM Capacity Package Type (2)
M306N5FCFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A Flash
As of Aug. 2006
Remarks
Normal-ver.
M306N5FCGP
PLQP0100KB-A memory
PRQP0100JB-A version (1) T-ver.
PLQP0100KB-A
M306N5FCTFP
M306N5FCTGP
M306N5FCVFP
PRQP0100JB-A
V-ver.
M306N5FCVGP
PLQP0100KB-A
M306N5MC-XXXGP
M306N5MCT-XXXFP
M306N5MCT-XXXGP
M306N5MCV-XXXFP
128 Kbytes
5 Kbytes
PLQP0100KB-A Mask
PRQP0100JB-A ROM
PLQP0100KB-A version
PRQP0100JB-A
Normal-ver.
T-ver.
V-ver.
M306N5MCV-XXXGP (D)
(D): Under development
NOTES:
PLQP0100KB-A
1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A).
2. The correspondence between new and old package types is as follows.
PRQP0100JB-A: 100P6S-A
PLQP0100KB-A: 100P6Q-A
Type No. M30 6N 5 M C T
XXX FP
Package type:
FP : Package PRQP0100JB-A (100P6S-A)
GP: Package PLQP0100KB-A (100P6Q-A)
ROM No.
Omitted on flash memory version
Characteristics
(no): Normal-ver.
T
V
: T-ver. (Automotive 85°C version)
: V-ver. (Automotive 125°C version)
ROM capacity:
C: 128 Kbytes
Memory type:
M: Mask ROM version
F : Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
Figure 1.2 Type Number, Memory Size, and Package
Rev.2.40 Aug 25, 2006 page 4 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
1.5 Pin Assignments
Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.3 and 1.4 list the List of Pin Names.
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
M16C/6N Group
(M16C/6N5)
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P10_2/AN2
P10_1/AN1
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG
NOTE:
Package: PRQP0100JB-A (100P6S-A)
1. P7_1 and P9_1 are N channel open-drain pins.
Figure 1.3 Pin Assignments (Top View) (1)
Rev.2.40 Aug 25, 2006 page 5 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
77
78
79
80
81
82
83
84
85
86
87
M16C/6N Group
(M16C/6N5)
88
89
90
91
92
93
94
95
96
97
98
99
100
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
31
30
VREF
AVCC
P9_7/ADTRG
P9_6/ANEX1/CTX0
P9_5/ANEX0/CRX0
29
28
27
26
NOTE:
Package: PLQP0100KB-A (100P6Q-A)
1. P7_1 and P9_1 are N channel open-drain pins.
Figure 1.4 Pin Assignments (Top View) (2)
Rev.2.40 Aug 25, 2006 page 6 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
Table 1.3 List of Pin Names (1)
CAN Module Bus Control Pin
Pin
Analog
Pin
Pin No. Control
Interrupt
Pin
Port
Timer Pin
UART Pin
FP GP
Pin
1
2
99
100
1
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
ANEX1 CTX0
ANEX0 CRX0
DA1
3
TB4IN
4
2
TB3IN
TB2IN
TB1IN
TB0IN
DA0
5
3
SOUT3
6
4
SIN3
7
5
CLK3
8
6
BYTE
CNVSS
XCIN
9
7
10
11
8
P8_7
9
XCOUT P8_6
____________
12 10 RESET
13 11 XOUT
14 12 VSS
15 13 XIN
16 14 VCC1
17 15
_______
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P7_7
P7_6
P7_5
P7_4
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
NMI
________
18 16
INT2
INT1
INT0
ZP
19 17
20 18
___
21 19
TA4IN/U
TA4OUT/U
TA3IN
22 20
23 21
24 22
TA3OUT
____
25 23
TA2IN/W
26 24
TA2OUT/W
___
__________ __________
27 25
TA1IN/V
CTS2/RTS2
28 26
TA1OUT/V
CLK2
29 27
TA0IN/TB5IN RXD2/SCL2
30 28
TA0OUT
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
31 29
32 30
33 31
CLK1
_________ _________ _________
34 32
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
35 33
36 34
RXD0/SCL0
37 35
CLK0
__________ __________
38 36
CTS0/RTS0
________
39 37
RDY/CLKOUT
40 38
ALE
__________
41 39
HOLD
__________
42 40
HLDA
43 41
BCLK
_____
44 42
RD
_________
45 43
WRH/_B__H___E__
________ ______
46 44
WRL/WR
_______
47 45
CS3
_______
48 46
CS2
_______
49 47
CS1
_______
50 48
CS0
FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A)
Rev.2.40 Aug 25, 2006 page 7 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
Table 1.4 List of Pin Names (2)
Analog
Pin
Pin No. Control
Interrupt
Pin
Port
Timer Pin
UART Pin
CAN Module Bus Control Pin
Pin
FP GP
51 49
52 50
53 51
54 52
55 53
56 54
57 55
58 56
59 57
60 58
61 59
Pin
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
62 60 VCC2
63 61
P3_0
A8(/-/D7)
64 62 VSS
65 63
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
D15
66 64
67 65
68 66
69 67
70 68
71 69
72 70
________
73 71
INT5
________
74 72
INT4
D14
________
75 73
INT3
D13
76 74
D12
77 75
D11
78 76
D10
79 77
D9
80 78
D8
81 79
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
D7
82 80
D6
83 81
D5
84 82
D4
85 83
D3
86 84
D2
87 85
D1
88 86
D0
______
89 87
P10_7 KI3
______
90 88
P10_6 KI2
AN6
______
91 89
P10_5 KI1
AN5
______
92 90
P10_4 KI0
P10_3
AN4
93 91
AN3
94 92
P10_2
AN2
95 93
P10_1
AN1
96 94 AVSS
97 95
P10_0
AN0
98 96 VREF
99 97 AVCC
100 98
_____________
P9_7
ADTRG
FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A)
Rev.2.40 Aug 25, 2006 page 8 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
1.6 Pin Functions
Tables 1.5 to 1.7 list the Pin Functions.
Table 1.5 Pin Functions (1)
Signal Name
Power supply VCC1, VCC2,
VSS
Pin Name
I/O Type
I
Description
Apply 4.2 to 5.5 V (T/V-ver.), 3.0 to 5.5 V (Normal-ver.) to the VCC1
and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is
input
that VCC2 = VCC1 (1)
.
I
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
Analog power AVCC, AVSS
supply input
_____________
The MCU is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1
to start up in microprocessor mode.
Reset input
RESET
I
I
CNVSS
CNVSS
Switches the data bus in external memory space. The data bus
is 16-bit long when the this pin is held “L” and 8-bit long when
the this pin is held “H”. Set it to either one. Connect this pin to
VSS when single-chip mode.
External data BYTE
bus width
select input
I
Inputs and outputs data (D0 to D7) when these pins are set as
the separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data
bus is set as the separate bus.
Bus control
pins
D0 to D7
I/O
I/O
D8 to D15
Output address bits (A0 to A19).
A0 to A19
O
Input and output data (D0 to D7) and output address bits (A0 to
A7) by time-sharing when external 8-bit data bus are set as the
multiplexed bus.
A0/D0 to A7/D7
I/O
Input and output data (D0 to D7) and output address bits (A1 to
A8) by time-sharing when external 16-bit data bus are set as the
multiplexed bus.
A1/D0 to A8/D7
I/O
_______
_______
Output _C__S___0_ to _C__S___3_ signals. _C__S___0_ to _C__S___3_ are chip-select signals
to specify an external space.
O
O
CS0 to CS3
_________ ______
Output _W___R___L_ , W____R___H__, (_W___R__, _B__H___E__), _R__D__ signals. _W___R___L_ and _W___R___H__ or
WRL/WR
_________ ________
________
BHE, and _W___R__ can be switched by program.
WRH/BHE
______
_________
• _W___R___L_, WRH, and _R__D__ are selected
RD
________
The WRL signal becomes “L” by writing data to an even address
in an external memory space.
_________
The WRH signal becomes “L” by writing data to an odd address
in an external memory space.
_____
The RD pin signal becomes “L” by reading data in an external
memory space.
• _W___R__, _B__H___E__, and _R__D__ are selected
______
The WR signal becomes “L” by writing data in an external
memory space.
_____
The RD signal becomes “L” by reading data in an external
memory space.
________
The BHE signal becomes “L” by accessing an odd address.
______
Select WR, _B__H___E__, and _R__D__ for an external 8-bit data bus.
ALE is a signal to latch the address.
While the HOLD pin is held “L”, the MCU is placed in a hold
O
I
ALE
HOLD
__________
__________
state.
__________
In a hold state, _H__L__D___A__ outputs a “L” signal.
While applying a “L” signal to the _R__D___Y__ pin, the MCU is placed in
a wait state.
O
I
H___L__D___A
RDY
I: Input
NOTE:
O: Output
I/O: Input/Output
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
Rev.2.40 Aug 25, 2006 page 9 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
Table 1.6 Pin Functions (2)
Signal Name
Main clock
input
Pin Name
I/O Type
I
Description
I/O pins for the main clock oscillation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (1)
XIN
.
Main clock
output
XOUT
XCIN
O
I
To use the external clock, input the clock from XIN and leave
XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a crystal
Sub clock
input
oscillator between XCIN and XCOUT (1)
.
To use the external clock, input the clock from XCIN and leave
XCOUT open.
Sub clock
output
XCOUT
O
Outputs the BCLK signal.
BCLK output
Clock output
BCLK
O
O
I
The clock of the same cycle as fC, f8, or f32 is output.
CLKOUT
______
________
________
Input pins for the INT interrupt.
INT interrupt input INT0 to INT5
_______
_______
________
Input pin for the NMI interrupt.
NMI interrupt NMI
I
input
______
______
Input pins for the key input interrupt.
Key input
interrupt input
Timer A
KI0 to KI3
I
These are timer A0 to timer A4 I/O pins.
These are timer A0 to timer A4 input pins.
Input pin for the Z-phase.
TA0OUT to TA4OUT
TA0IN to TA4IN
ZP
I/O
I
I
These are timer B0 to timer B5 input pins.
These are Three-phase motor control output pins.
Timer B
TB0IN to TB5IN
____
I
___
___
Three-phase motor U, U, V, V, W, W
control output
O
__________
__________
These are transmit control input pins.
These are receive control output pins.
These are transfer clock I/O pins.
These are serial data input pins.
Serial interface
I
O
I/O
I
CTS0 to CTS2
__________
__________
RTS0 to RTS2
CLK0 to CLK3
RXD0 to RXD2
SIN3
These are serial data input pins.
I
These are serial data output pins.
These are serial data output pins.
This is output pin for transfer clock output from multiple pins
function.
TXD0 to TXD2
SOUT3
O
O
O
CLKS1
I2C mode
These are serial data I/O pins.
SDA0 to SDA2
SCL0 to SCL2
I/O
I/O
These are transfer clock I/O pins. (however, SCL2 for the
N-channel open drain output.)
Applies the reference voltage for the A/D converter and D/A
converter.
Reference
VREF
I
I
voltage input
A/D converter
Analog input pins for the A/D converter.
AN0 to AN7
AN0_0 to AN0_7
AN2_0 to AN2_7
_____________
This is an A/D trigger input pin.
ADTRG
ANEX0
I
This is the extended analog input pin for the A/D converter,
and is the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
These are the output pins for the D/A converter.
This is the input pin for the CAN module.
I/O
ANEX1
DA0, DA1
CRX0
I
D/A converter
CAN module
O
I
This is the output pin for the CAN module.
CTX0
O
I: Input
NOTE:
O: Output
I/O: Input/Output
1. Ask the oscillator maker the oscillation characteristic.
Rev.2.40 Aug 25, 2006 page 10 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
1. Overview
Table 1.7 Pin Functions (3)
Signal Name
I/O port
Pin Name
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
I/O Type
I/O
Description
8-bit I/O ports in CMOS, having a direction register to select
an input or output.
Each pin is set as an input port or output port. An input port
can be set for a pull-up or for no pull-up in 4-bit unit by
program.
P4_0
P4_7
to
P5_0 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
P9_0 to P9_7
P10_0 to P10_7
P8_5
(however, P7_1 and P9_1 for the N-channel open drain
output.)
_______
Input port
I
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I: Input
O: Output
I/O: Input/Output
Rev.2.40 Aug 25, 2006 page 11 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R3
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
Data Registers (1)
R2
R3
A0
A1
FB
Address Registers (1)
Frame Base Registers (1)
b19
b15
b0
Interrupt Table Register
INTBH
INTBL
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b0
b0
Program Counter
PC
b15
b15
USP
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b0
FLG
Flag Register
b15
b8 b7
U
b0
C
IPL
I
O
B
S
Z
D
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.2.40 Aug 25, 2006 page 12 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set
to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write 0. When read, its content is undefined.
Rev.2.40 Aug 25, 2006 page 13 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
3. Memory
3. Memory
Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a
5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The Special Function Registers (SFRs) are allocated to the addresses from 00000h to 003FFh. Peripheral
function control registers are located here. Of the SFR, any area which has no functions allocated is reserved
for future use and cannot be accessed by user.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
00000h
SFR
00400h
Internal RAM
XXXXX
h
FFE00h
FFFDCh
FFFFFh
Reserved area (1)
0F000h
Internal ROM
(data flash) (3)
Special page
vector table
0FFFFh
10000h
External area
Reserved area
External area
27000h
28000h
Undefined instruction
Overflow
BRK instruction
Address match
Single step
80000h
Reserved area (2)
Oscillation stop and re-oscillation
detection / watchdog timer
Internal RAM
Internal ROM (4)
YYYYY
h
DBC
NMI
Reset
Internal ROM
Capacity Address XXXXX
h
Capacity Address YYYYYh
(program area) (4)
5 Kbytes
017FF
h
128 Kbytes
E0000h
FFFFFh
NOTES:
1. During memory expansion mode or microprocessor mode, cannot be used.
2. In memory expansion mode, cannot be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. When using the masked ROM version, write nothing to internal ROM area.
5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 (block A enabled, addresses 10000h to
26FFFh for CS2 area).
M16C/6N Group (M16C/6N5) has no device model expanded over 192 Kbytes of the internal ROM.
Accordingly, set the PM13 bit to 0.
Figure 3.1 Memory Map
Rev.2.40 Aug 25, 2006 page 14 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (Special Function Register) is a control register for a peripheral function.
Tables 4.1 to 4.12 list the SFR Information.
Table 4.1 SFR Information (1) (3)
Address
0000h
0001h
0002h
0003h
Register
Symbol
After Reset
00000000b (CNVSS pin is "L")
00000011b (CNVSS pin is "H")
00001000b
0004h
Processor Mode Register 0 (1)
PM0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Processor Mode Register 1
PM1
CM0
CM1
CSR
AIER
PRCR
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
Oscillation Stop Detection Register (2)
CM2
0X000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
WDTS
WDC
XXh
00XXXXXXb
00h
Address Match Interrupt Register 0
RMAD0
00h
X0h
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
Chip Select Expansion Control Register
PLL Control Register 0
CSE
PLC0
00h
0001X010b
Processor Mode Register 2
DMA0 Source Pointer
PM2
XXX00000b
XXh
XXh
XXh
SAR0
XXh
XXh
XXh
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DAR0
XXh
XXh
TCR0
DM0CON
00000X00b
XXh
XXh
XXh
DMA1 Source Pointer
SAR1
XXh
XXh
XXh
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
DAR1
XXh
XXh
TCR1
DM1CON
00000X00b
X: Undefined
NOTES:
1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.
2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.
3. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 15 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.2 SFR Information (2) (1)
Address
0040h
0041h
0042h
0043h
0044h
0045h
Register
Symbol
After Reset
CAN0 Wake-up Interrupt Control Register
C01WKIC
C0RECIC
C0TRMIC
INT3IC
TB5IC
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
INT5 Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
TB4IC
U1BCNIC
TB3IC
XXXXX000b
0046h
XXXXX000b
0047h
0048h
0049h
U0BCNIC
INT5IC
S3IC
INT4IC
U2BCNIC
DM0IC
DM1IC
C01ERRIC
ADIC
KUPIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
XX00X000b
XX00X000b
004Ah
004Bh
004Ch
004Dh
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
DMA1 Interrupt Control Register
CAN0 Error Interrupt Control Register
A/D Conversion Interrupt Control Register
Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
004Eh
XXXXX000b
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
XXh
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
INT1 Interrupt Control Register
INT2 Interrupt Control Register
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 0: Identifier / DLC
CAN0 Message Box 0: Data Field
CAN0 Message Box 0: Time Stamp
CAN0 Message Box 1: Identifier / DLC
CAN0 Message Box 1: Data Field
CAN0 Message Box 1: Time Stamp
X: Undefined
NOTE:
1. Blank space is reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 16 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.3 SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 2: Identifier / DLC
CAN0 Message Box 2: Data Field
CAN0 Message Box 2: Time Stamp
CAN0 Message Box 3: Identifier / DLC
CAN0 Message Box 3: Data Field
CAN0 Message Box 3: Time Stamp
CAN0 Message Box 4: Identifier / DLC
CAN0 Message Box 4: Data Field
CAN0 Message Box 4: Time Stamp
CAN0 Message Box 5: Identifier / DLC
CAN0 Message Box 5: Data Field
CAN0 Message Box 5: Time Stamp
X: Undefined
Rev.2.40 Aug 25, 2006 page 17 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.4 SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 6: Identifier / DLC
CAN0 Message Box 6: Data Field
CAN0 Message Box 6: Time Stamp
CAN0 Message Box 7: Identifier / DLC
CAN0 Message Box 7: Data Field
CAN0 Message Box 7: Time Stamp
CAN0 Message Box 8: Identifier / DLC
CAN0 Message Box 8: Data Field
CAN0 Message Box 8: Time Stamp
CAN0 Message Box 9: Identifier / DLC
CAN0 Message Box 9: Data Field
CAN0 Message Box 9: Time Stamp
X: Undefined
Rev.2.40 Aug 25, 2006 page 18 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.5 SFR Information (5)
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 10: Identifier / DLC
CAN0 Message Box 10: Data Field
CAN0 Message Box 10: Time Stamp
CAN0 Message Box 11: Identifier / DLC
CAN0 Message Box 11: Data Field
CAN0 Message Box 11: Time Stamp
CAN0 Message Box 12: Identifier / DLC
CAN0 Message Box 12: Data Field
CAN0 Message Box 12: Time Stamp
CAN0 Message Box 13: Identifier / DLC
CAN0 Message Box 13: Data Field
CAN0 Message Box 13: Time Stamp
X: Undefined
Rev.2.40 Aug 25, 2006 page 19 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.6 SFR Information (6) (1)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 14: Identifier /DLC
CAN0 Message Box 14: Data Field
CAN0 Message Box 14: Time Stamp
CAN0 Message Box 15: Identifier /DLC
CAN0 Message Box 15: Data Field
CAN0 Message Box 15: Time Stamp
CAN0 Global Mask Register
C0GMR
CAN0 Local Mask A Register
CAN0 Local Mask B Register
C0LMAR
C0LMBR
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 20 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.7 SFR Information (7) (2)
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Register
Symbol
After Reset
Flash Memory Control Register 1 (1)
Flash Memory Control Register 0 (1)
Address Match Interrupt Register 2
FMR1
0X00XX0Xb
FMR0
00000001b
00h
00h
X0h
XXXXXX00b
00h
RMAD2
AIER2
RMAD3
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
00h
X0h
X: Undefined
NOTES:
1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.
2. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 21 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.8 SFR Information (8) (1)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Register
Symbol
TBSR
After Reset
000XXXXXb
Timer B3, B4, B5 Count Start Flag
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
TA11
TA21
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
INVC0
INVC1
IDB0
IDB1
DTT
00111111b
00111111b
XXh
Timer B2 Interrupt Generation Frequency Set Counter
ICTB2
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Timer B3 Register
Timer B4 Register
Timer B5 Register
TB3
TB4
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Source Select Register 0
Interrupt Source Select Register 1
SI/O3 Transmit/Receive Register
TB3MR
TB4MR
TB5MR
IFSR0
IFSR1
S3TRR
00XX0000b
00XX0000b
00XX0000b
00XXX000b
00h
XXh
SI/O3 Control Register
SI/O3 Bit Rate Register
S3C
S3BRG
01000000b
XXh
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
U2BRG
XXh
XXh
XXh
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
00001000b
00000010b
XXh
UART2 Receive Buffer Register
U2RB
XXh
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 22 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.9 SFR Information (9) (1)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Register
Symbol
After Reset
00h
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X0000001b
XX0X0000b
00h
X0000001b
00h
CAN0 Control Register
C0CTLR
C0STR
C0SSTR
C0ICR
CAN0 Status Register
CAN0 Slot Status Register
CAN0 Interrupt Control Register
CAN0 Extended ID Register
00h
00h
00h
00h
00h
XXh
XXh
00h
C0IDR
CAN0 Configuration Register
C0CONR
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
C0RECR
C0TECR
00h
00h
00h
CAN0 Time Stamp Register
C0TSR
X0000001b
XX0X0000b
CAN1 Control Register
C1CTLR
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 23 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.10 SFR Information (10) (1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
to
Register
Symbol
After Reset
XXh
XXh
CAN0 Acceptance Filter Support Register
C0AFS
Peripheral Clock Select Register
CAN0 Clock Select Register
PCLKR
CCLKR
00h
00h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
X: Undefined
NOTE:
1. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 24 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.11 SFR Information (11) (2)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
00h
0XXXXXXXb
00h
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
00h
00h (1)
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
Timer A0 Register
Timer A1 Register
Timer A2 Register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
Register
Register
Register
Register
Register
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
U0MR
U0BRG
00h
XXh
XXh
U0TB
UART0 Transmit Buffer Register
XXh
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
00001000b
00XX0010b
XXh
U0RB
UART0 Receive Buffer Register
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
00001000b
00XX0010b
XXh
XXh
X0000000b
U1RB
UART1 Receive Buffer Register
UART Transmit/Receive Control Register 2
UCON
DMA0 Request Source Select Register
DMA1 Request Source Select Register
DM0SL
DM1SL
00h
00h
XXh
XXh
XXh
CRC Data Register
CRC Input Register
CRCD
CRCIN
X: Undefined
NOTES:
1. Bits TA2P to TA4P in the UDF register are set to 0 after reset. However, the contents in these bits are undefined when read.
2. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 25 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
4. Special Function Registers (SFRs)
Table 4.12 SFR Information (12) (2)
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
Register
Symbol
AD0
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
00000XXXb
00h
00h
D/A Register 1
DA1
00h
00h
D/A Control Register
DACON
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
P0
P1
PD0
PD1
P2
XXh
XXh
00h
00h
XXh
XXh
00h
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
00h
XXh
XXh
00h
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
PD4
PD5
P6
00h
XXh
XXh
00h
Port P7 Register
P7
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
PD6
PD7
P8
00h
XXh
XXh
00X00000b
00h
Port P9 Register
P9
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
PD8
PD9
P10
XXh
Port P10 Direction Register
PD10
00h
00h
00000000b (1)
00000010b
00h
Pull-up Control Register 0
Pull-up Control Register 1
PUR0
PUR1
03FDh
Pull-up Control Register 2
Port Control Register
PUR2
PCR
03FEh
03FFh
00h
X: Undefined
NOTES:
1. At hardware reset, the register is as follows:
00000000b where "L" is input to the CNVSS pin
00000010b where "H" is input to the CNVSS pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
00000000b where bits PM01 to PM00 in the PM0 register are 00b (single-chip mode)
00000010b where bits PM01 to PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode)
2. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006 page 26 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
5. Electrical Characteristics
5.1 Electrical Characteristics (T/V-ver.)
Table 5.1 Absolute Maximum Ratings
Condition
Rated Value
–0.3 to 6.5
Unit
V
Symbol
Parameter
VCC
AVCC
VI
Supply voltage (VCC1 = VCC2)
VCC = AVCC
VCC = AVCC
Analog supply voltage
–0.3 to 6.5
V
_____________
Input
–0.3 to VCC+0.3
V
RESET, CNVSS, BYTE,
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
VREF, XIN
–0.3 to 6.5
V
V
P7_1, P9_1
VO
Output
voltage
–0.3 to VCC+0.3
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, XOUT
P7_1, P9_1
–0.3 to 6.5
700
V
Pd
Power dissipation
Topr = 25°C
mW
°C
Topr
Operating ambient During MCU operation
temperature
T version: –40 to 85
V version: –40 to 125 (option)
0 to 60
During flash memory program and
erase operation
Storage temperature
Tstg
–65 to 150
°C
option: All options are on request basis.
Rev.2.40 Aug 25, 2006 page 27 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Table 5.2 Recommended Operating Conditions (1) (1)
Standard
Unit
Symbol
Parameter
Min.
4.2
Typ.
5.0
VCC
0
Max.
5.5
VCC
Supply voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog supply voltage
Supply voltage
AVSS
VIH
Analog supply voltage
HIGH input
0
VCC
0.8 VCC
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
voltage
P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, XIN, _R__E___S__E___T__, CNVSS, BYTE
P7_1, P9_1
6.5
VCC
V
V
0.8 VCC
0.8 VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
VCC
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
0.5 VCC
0
0.2 VCC
VIL
LOW input
voltage
P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
_____________
XIN, RESET, CNVSS, BYTE
V
V
0.2 VCC
0.16 VCC
–10.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
0
0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
mA
IOH(peak)
HIGH peak
output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
mA
IOH(avg)
–5.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
HIGH average
output current
mA
mA
IOL(peak)
IOL(avg)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
10.0
5.0
LOW peak
output current
LOW average
output current
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.
2. Average output current values during 100 ms period.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.
The total IOH(peak) for ports P3, P4, and P5 must be –40 mA max.
The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be –40 mA max.
Rev.2.40 Aug 25, 2006 page 28 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Table 5.3 Recommended Operating Conditions (2) (1)
Standard
Unit
Symbol
f(XIN)
Parameter
Min.
0
Typ.
Max.
16
Main clock input oscillation No wait Mask ROM version VCC = 4.2 to 5.5 V
MHz
(2) (3) (4)
frequency
Flash memory version
f(XCIN)
f(Ring)
f(PLL)
Sub clock oscillation frequency
On-chip oscillation frequency
PLL clock oscillation frequency
CPU operation clock
32.768
1
50
kHz
MHz
MHz
MHz
ms
16
0
20
20
20
f(BCLK)
tsu(PLL)
VCC = 4.2 to 5.5 V
PLL frequency synthesizer stabilization wait time
NOTES:
Main clock input oscillation frequency
(Mask ROM version / Flash memory
version: no wait)
1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless
otherwise specified.
16.0
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 5.0 0.5 V.
4. When using over 16 MHz, use PLL clock. PLL clock oscillation
frequency which can be used is 16 MHz or 20 MHz.
0.0
4.2
5.5
VCC [V] (main clock: no division)
Rev.2.40 Aug 25, 2006 page 29 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Standard
Table 5.4 Electrical Characteristics (1) (1)
Symbol
VOH
Parameter
Measuring Condition
Unit
V
Min. Typ. Max.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5 mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
V
CC-2.0
VCC
HIGH output
voltage
P9_2 to P9_7, P10_0 to P10_7
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
VOH
HIGH output
voltage
IOH = –200 µA
V
CC-0.3
IOH = –1 mA
VCC
VCC
3.0
3.0
V
V
V
XOUT
HIGHPOWER
LOWPOWER
VOH
VOL
HIGH output
voltage
IOH = –0.5 mA
With no load applied
With no load applied
IOL = 5 mA
2.5
1.6
XCOUT HIGHPOWER
HIGH output
voltage
LOWPOWER
2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW output
voltage
V
IOL = 200 µA
0.45
VOL
VOL
LOW output
voltage
V
V
V
IOL = 1 mA
LOW output
voltage
XOUT
HIGHPOWER
LOWPOWER
2.0
2.0
IOL = 0.5 mA
0
0
With no load applied
With no load applied
LOW output
voltage
XCOUT HIGHPOWER
LOWPOWER
_________
HOLD, _R__D__Y__, TA0IN to TA4IN, TB0IN to TB5IN,
1.0
Hysteresis
0.2
0.2
VT+-VT-
I_N___T__0__ to INT5, NMI, ADTRG, C___T__S__0__ to CTS2,
________ _______ _____________
_________
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,
TA0OUT to TA4OUT, _K__I_0_ to KI3,
_____
RXD0 to RXD2, SIN3
_____________
Hysteresis
V
2.5
5.0
VT+-VT-
IIH
RESET
HIGH input
current
µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 5 V
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
LOW input
current
µA
–5.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
IIL
VI = 0 V
VI = 0 V
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
Pull-up
resistance
kΩ
170
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7
50
RPULLUP
30
Feedback resistance
Feedback resistance
RAM retention voltage
MΩ
MΩ
V
XIN
XCIN
1.5
15
RfXIN
RfXCIN
VRAM
2.0
At stop mode
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.
Rev.2.40 Aug 25, 2006 page 30 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Table 5.5 Electrical Characteristics (2) (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Mask ROM f(BCLK) = 20 MHz,
Min. Typ. Max.
ICC
Power supply
current
16
28
mA
In single-chip mode,
the output pins are
PLL operation,
No division
(VCC= 4.2 to 5.5 V) open and other pins
are VSS.
On-chip oscillation,
No division
1
mA
mA
Flash memory f(BCLK) = 20 MHz,
PLL operation,
18
30
No division
On-chip oscillation,
No division
1.8
15
25
25
mA
mA
mA
µA
Flash memory f(BCLK) = 10 MHz,
program
VCC = 5 V
Flash memory f(BCLK) = 10 MHz,
erase
VCC = 5 V
Mask ROM
f(BCLK) = 32 kHz,
Low power dissipation
(2)
mode, ROM
Flash memory f(BCLK) = 32 kHz,
Low power dissipation
25
µA
µA
(2)
mode, RAM
f(BCLK) = 32 kHz,
Low power dissipation
mode,
420
(2)
Flash memory
Mask ROM
Flash memory Wait mode
f(BCLK) = 32 kHz,
On-chip oscillation,
50
µA
µA
8.5
(3)
Wait mode
,
Oscillation capacity High
f(BCLK) = 32 kHz,
3.0
0.8
µA
µA
(3)
Wait mode
,
Oscillation capacity Low
Stop mode,
3.0
Topr = 25°C
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
Rev.2.40 Aug 25, 2006 page 31 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Table 5.6 A/D Conversion Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
Bit
–
Resolution
VREF = VCC
10
3
LSB
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
INL
Integral
nonlinearity
error
10 bits
VREF
= VCC
= 5 V
LSB
LSB
LSB
7
2
3
8 bits
VREF = AVCC = VCC = 5 V
ANEX0, ANEX1 input, AN0 to AN7 input,
–
Absolute
accuracy
10 bits
VREF
= VCC
= 5 V
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
LSB
LSB
LSB
LSB
LSB
kΩ
7
2
8 bits
VREF = AVCC = VCC = 5 V
DNL
–
Differential nonlinearity error
Offset error
1
3
–
Gain error
3
10
RLADDER
tCONV
Resistor ladder
VREF = VCC
40
µs
3.3
10-bit conversion time,
sample & hold available
8-bit conversion time,
sample & hold available
Sampling time
VREF = VCC = 5 V, φAD = 10 MHz
µs
2.8
VREF = VCC = 5 V, φAD = 10 MHz
µs
V
tSAMP
VREF
0.3
2.0
0
Reference voltage
Analog input voltage
VCC
VIA
VREF
V
NOTES:
1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250kHz or more in addition to a limit of NOTE 2.
When sample & hold is enabled, φAD frequency must be 1MHz or more in addition to a limit of NOTE 2.
Table 5.7 D/A conversion Characteristics (1)
Standard
Symbol
Parameter
Measuring condition
Unit
Min.
Max.
8
Typ.
–
Resolution
Bits
%
–
Absolute accuracy
1.0
3
tsu
µs
Setup time
RO
IVREF
4
10
20
1.5
kΩ
mA
Output resistance
(NOTE 2)
Reference power supply input current
NOTES:
1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.
The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the
ADCON1 register.
Rev.2.40 Aug 25, 2006 page 32 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Table 5.8 Power Supply Circuit Timing Characteristics
Standard
Typ.
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
2
td(P-R)
td(R-S)
td(W-S)
Time for internal power supply stabilization during powering-on VCC = 4.2 to 5.5 V
STOP release time
ms
µs
µs
150
150
Low power dissipation mode wait mode release time
td(P-R)
Time for internal power supply
stabilization during powering-on
VCC
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
td(R-S)
STOP release time
(b) Wait mode release
td(W-S)
Low power dissipation mode
wait mode release time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 5.1 Power Supply Circuit Timing Diagram
Rev.2.40 Aug 25, 2006 page 33 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.9 External Clock Input (XIN Input)
Standard
Symbol
tC
Parameter
Unit
Min.
62.5
25
Max.
External clock input cycle time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 5.10 Memory Expansion Mode and Microprocessor Mode
Standard
Unit
Symbol
Parameter
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
(NOTE 1) ns
(NOTE 2) ns
(NOTE 3) ns
Data input access time (when accessing multiplexed bus area)
40
30
40
0
ns
ns
ns
ns
ns
ns
Data input setup time
________
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
th(BCLK-RDY)
th(BCLK-HOLD)
0
RDY input hold time
__________
0
HOLD input hold time
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 45 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 45 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
Rev.2.40 Aug 25, 2006 page 34 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.11 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
100
40
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
40
Table 5.12 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
400
200
200
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.13 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
200
100
100
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
tw(TAH)
Parameter
Unit
Min.
100
100
Max.
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
tw(TAL)
Table 5.15 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
tc(UP)
Parameter
Unit
Min.
2000
1000
1000
400
Max.
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
TAiOUT input hold time
Table 5.16 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
800
200
200
Max.
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
ns
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Rev.2.40 Aug 25, 2006 page 35 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.17 Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.18 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.19 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.20 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
_____________
tC(AD)
ADTRG input cycle time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG input LOW pulse width
Table 5.21 Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
70
90
RXDi input setup time
RXDi input hold time
_______
Table 5.22 External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
_______
tw(INH)
tw(INL)
INTi input HIGH pulse width
ns
ns
_______
INTi input LOW pulse width
Rev.2.40 Aug 25, 2006 page 36 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.2
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
NOTES:
HLDA output delay time
40
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
C
by a circuit of the right figure.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
30 pF
Figure 5.2 Port P0 to P10 Measurement Circuit
Rev.2.40 Aug 25, 2006 page 37 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.2
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
HLDA output delay time
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
– 40 [ns]
f(BCLK)
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
C
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Rev.2.40 Aug 25, 2006 page 38 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.25 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.2
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
25
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
25
40
RD signal output hold time
0
0
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
HLDA output delay time
40
15
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
–4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdZ(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 40 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 25 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 15 [ns]
Rev.2.40 Aug 25, 2006 page 39 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
t
h(TIN—UP) su(UP—TIN)
t
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
CLKi
tc(CK)
tw(CKH)
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 5.3 Timing Diagram (1)
Rev.2.40 Aug 25, 2006 page 40 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 5 V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Measuring conditions :
VCC = 5 V
Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V
Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V
Figure 5.4 Timing Diagram (2)
Rev.2.40 Aug 25, 2006 page 41 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 5 V
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
t
h(RD-AD)
-4ns.min
25ns.max
0ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac1(RD-DB)
(0.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
t
h(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
25ns.max
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.5 Timing Diagram (3)
Rev.2.40 Aug 25, 2006 page 42 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
h(RD-AD)
t
h(BCLK-ALE)
t
d(BCLK-ALE)
0ns.min
-4ns.min
25ns.max
ALE
RD
t
d(BCLK-RD)
th(BCLK-RD)
0ns.min
25ns.max
t
ac2(RD-DB)
(1.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
h(RD-DB)
tSU(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
-4ns.min
25ns.max
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.6 Timing Diagram (4)
Rev.2.40 Aug 25, 2006 page 43 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.7 Timing Diagram (5)
Rev.2.40 Aug 25, 2006 page 44 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
tac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.8 Timing Diagram (6)
Rev.2.40 Aug 25, 2006 page 45 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
Read timing
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
th(RD-CS)
tcyc
(0.5 ✕ tcyc-10)ns.min
CSi
td(AD-ALE)
th(ALE-AD)
(0.5 ✕ tcyc-25)ns.min
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Address
Address
Data input
tdZ(RD-AD)
8ns.max
th(RD-DB)
0ns.min
tac3(RD-DB)
tSU(DB-RD)
40ns.min
(1.5 ✕ tcyc-45)ns.max
td(AD-RD)
0ns.min
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(RD-AD)
25ns.max
(0.5 ✕ tcyc-10)ns.min
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
Write timing
BCLK
th(BCLK-CS)
4ns.min
th(WR-CS)
tcyc
td(BCLK-CS)
25ns.max
(0.5 ✕ tcyc-10)ns.min
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
40ns.max
ADi
Address
Data output
Address
/DBi
td(DB-WR)
(1.5 ✕ tcyc-40)ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
td(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
td(AD-WR)
0ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.9 Timing Diagram (7)
Rev.2.40 Aug 25, 2006 page 46 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (T/V-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
Read timing
tcyc
BCLK
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Data input
Address
t
h(RD-DB)
0ns.min
t
dZ(RD-AD)
t
ac3(RD-DB)
t
d(BCLK-AD)
8ns.max
t
SU(DB-RD)
40ns.min
td(AD-RD)
t
h(BCLK-AD)
4ns.min
25ns.max
(2.5 ✕ tcyc-45)ns.max
0ns.min
ADi
BHE
(no multiplex)
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-DB)
4ns.min
t
d(BCLK-DB)
40ns.max
ADi
/DBi
Address
Data output
t
d(AD-ALE)
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-40)ns.min
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex) td(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.10 Timing Diagram (8)
Rev.2.40 Aug 25, 2006 page 47 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
5.2 Electrical Characteristics (Normal-ver.)
Table 5.26 Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated Value
–0.3 to 6.5
Unit
V
VCC
AVCC
VI
Supply voltage (VCC1 = VCC2)
VCC = AVCC
VCC = AVCC
Analog supply voltage
–0.3 to 6.5
V
_____________
Input
–0.3 to VCC+0.3
V
RESET, CNVSS, BYTE,
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
VREF, XIN
–0.3 to 6.5
V
V
P7_1, P9_1
VO
Output
voltage
–0.3 to VCC+0.3
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, XOUT
P7_1, P9_1
–0.3 to 6.5
700
V
Pd
Power dissipation
Topr = 25°C
mW
°C
Topr
Operating ambient During MCU operation
–40 to 85
0 to 60
temperature
During flash memory program and
erase operation
Storage temperature
Tstg
–65 to 150
°C
Rev.2.40 Aug 25, 2006 page 48 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Table 5.27 Recommended Operating Conditions (1) (1)
Standard
Unit
Symbol
Parameter
Min.
3.0
Typ.
5.0
VCC
0
Max.
5.5
VCC
Supply voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog supply voltage
Supply voltage
AVSS
VIH
Analog supply voltage
HIGH input
0
VCC
0.8 VCC
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
voltage
P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, XIN, _R__E___S__E___T__, CNVSS, BYTE
P7_1, P9_1
6.5
VCC
V
V
0.8 VCC
0.8 VCC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
VCC
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,
0.5 VCC
0
0.2 VCC
VIL
LOW input
voltage
P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
_____________
XIN, RESET, CNVSS, BYTE
V
V
0.2 VCC
0.16 VCC
–10.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(During single-chip mode)
0
0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(Data input during memory expansion and microprocessor modes)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
mA
IOH(peak)
HIGH peak
output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
mA
IOH(avg)
–5.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,
P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
HIGH average
output current
mA
mA
IOL(peak)
IOL(avg)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
10.0
5.0
LOW peak
output current
LOW average
output current
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.
2. Average output current values during 100 ms period.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.
The total IOH(peak) for ports P3, P4, and P5 must be –40 mA max.
The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be –40 mA max.
Rev.2.40 Aug 25, 2006 page 49 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Table 5.28 Recommended Operating Conditions (2) (1)
Standard
Unit
Symbol
f(XIN)
Parameter
Min.
0
Typ.
Max.
16
Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V
MHz
(2) (3) (4)
frequency
Flash memory version
f(XCIN)
f(Ring)
f(PLL)
Sub clock oscillation frequency
On-chip oscillation frequency
PLL clock oscillation frequency
CPU operation clock
32.768
1
50
kHz
MHz
MHz
MHz
ms
16
0
24
24
20
f(BCLK)
tsu(PLL)
VCC = 3.0 to 5.5 V
PLL frequency synthesizer stabilization wait time
NOTES:
Main clock input oscillation frequency
(Mask ROM version / Flash memory
version: no wait)
1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless
otherwise specified.
16.0
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 3.3 0.3 V or
VCC = 5.0 0.5 V.
4. When using over 16 MHz, use PLL clock. PLL clock oscillation
frequency which can be used is 16 MHz, 20 MHz or 24 MHz.
0.0
3.0
5.5
VCC [V] (main clock: no division)
Rev.2.40 Aug 25, 2006 page 50 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Table 5.29 A/D Conversion Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
Bit
–
Resolution
VREF = VCC
10
3
LSB
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
INL
Integral
nonlinearity
error
10 bits
VREF
= VCC
= 5 V
LSB
LSB
7
5
VREF
= VCC
= 3.3 V
LSB
LSB
LSB
7
2
3
8 bits
VREF = AVCC = VCC = 5.0 V, 3.3 V
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
–
Absolute
accuracy
10 bits
VREF
= VCC
= 5 V
LSB
LSB
7
5
VREF
= VCC
= 3.3 V
LSB
LSB
LSB
LSB
LSB
kΩ
7
2
8 bits
VREF = AVCC = VCC = 5.0 V, 3.3 V
DNL
–
Differential nonlinearity error
Offset error
1
3
–
Gain error
3
10
RLADDER
tCONV
Resistor ladder
VREF = VCC
40
µs
3.3
10-bit conversion time,
sample & hold available
8-bit conversion time,
sample & hold available
Sampling time
VREF = VCC = 5 V, φAD = 10 MHz
µs
2.8
VREF = VCC = 5 V, φAD = 10 MHz
µs
V
tSAMP
VREF
0.3
2.0
0
Reference voltage
Analog input voltage
VCC
VIA
VREF
V
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2.
When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2.
Table 5.30 D/A conversion Characteristics (1)
Standard
Symbol
Parameter
Measuring Condition
Unit
Min.
Max.
8
Typ.
–
Resolution
Bits
%
–
Absolute accuracy
1.0
3
tsu
µs
Setup time
RO
IVREF
4
10
20
1.5
kΩ
mA
Output resistance
(NOTE 2)
Reference power supply input current
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.
The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF
may have been set to be unconnected by the ADCON1 register.
Rev.2.40 Aug 25, 2006 page 51 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Table 5.31 Power Supply Circuit Timing Characteristics
Standard
Typ.
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
2
td(P-R)
td(R-S)
td(W-S)
Time for internal power supply stabilization during powering-on VCC = 3.0 to 5.5 V
STOP release time
ms
µs
µs
150
150
Low power dissipation mode wait mode release time
td(P-R)
Time for internal power supply
stabilization during powering-on
VCC
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
td(R-S)
STOP release time
(b) Wait mode release
td(W-S)
Low power dissipation mode
wait mode release time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 5.11 Power Supply Circuit Timing Diagram
Rev.2.40 Aug 25, 2006 page 52 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Table 5.32 Electrical Characteristics (1) (1)
VCC = 5V
Standard
Symbol
VOH
Parameter
Measuring Condition
Unit
Min. Typ. Max.
HIGH output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5 mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
V
CC-2.0
VCC
V
P9_2 to P9_7, P10_0 to P10_7
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
P9_2 to P9_7, P10_0 to P10_7
VOH
HIGH output
voltage
IOH = –200 µA
V
CC-0.3
IOH = –1 mA
VCC
VCC
3.0
3.0
V
V
V
XOUT
HIGHPOWER
LOWPOWER
VOH
VOL
HIGH output
voltage
IOH = –0.5 mA
With no load applied
With no load applied
IOL = 5 mA
2.5
1.6
XCOUT HIGHPOWER
HIGH output
voltage
LOWPOWER
2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW output
voltage
V
IOL = 200 µA
0.45
VOL
VOL
LOW output
voltage
V
V
V
IOL = 1 mA
IOL = 0.5 mA
XOUT
HIGHPOWER
LOWPOWER
LOW output
voltage
2.0
2.0
0
0
With no load applied
With no load applied
XCOUT HIGHPOWER
LOW output
voltage
LOWPOWER
_________ _______
Hysteresis
0.2
0.2
VT+-VT-
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
1.0
I_N___T__0__ to _IN___T__5__, _N__M___I_, ADTRG, C___T__S___0_ to _C__T__S___2_,
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,
TA0OUT to TA4OUT, _K__I_0_ to _K__I_3_ ,
_____________
RXD0 to RXD2, SIN3
_____________
Hysteresis
HIGH input
current
V
2.5
5.0
VT+-VT-
IIH
RESET
µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 5 V
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
LOW input
current
µA
–5.0
IIL
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
VI = 0 V
VI = 0 V
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
Pull-up
resistance
30
50
170
kΩ
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7
RPULLUP
Feedback resistance
Feedback resistance
RAM retention voltage
MΩ
MΩ
V
1.5
15
XIN
XCIN
RfXIN
RfXCIN
VRAM
At stop mode
2.0
NOTES:
1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
Rev.2.40 Aug 25, 2006 page 53 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Standard
Table 5.33 Electrical Characteristics (2) (1)
Symbol
Parameter
Measuring Condition
Unit
mA
Min. Typ. Max.
ICC
Power supply
current
Mask ROM
f(BCLK) = 24 MHz,
PLL operation,
No division
16
32
In single-chip mode,
the output pins are
(VCC= 3.0 to 5.5 V) open and other pins
are VSS.
On-chip oscillation,
No division
1
mA
mA
Flash memory f(BCLK) = 24 MHz,
PLL operation,
20
34
No division
On-chip oscillation,
No division
1.8
15
25
25
mA
mA
mA
µA
Flash memory f(BCLK) = 10 MHz,
program
VCC = 5 V
Flash memory f(BCLK) = 10 MHz,
erase
VCC = 5 V
Mask ROM
f(BCLK) = 32 kHz,
Low power dissipation
(2)
mode, ROM
Flash memory f(BCLK) = 32 kHz,
Low power dissipation
25
µA
µA
(2)
mode, RAM
f(BCLK) = 32 kHz,
Low power dissipation
mode,
420
(2)
Flash memory
Mask ROM
Flash memory Wait mode
f(BCLK) = 32 kHz,
On-chip oscillation,
50
µA
µA
8.5
(3)
Wait mode
,
Oscillation capacity High
f(BCLK) = 32 kHz,
3.0
0.8
µA
µA
(3)
Wait mode
,
Oscillation capacity Low
Stop mode,
3.0
Topr = 25°C
NOTES:
1. Referenced to VCC = 3.0 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
Rev.2.40 Aug 25, 2006 page 54 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.34 External Clock Input (XIN Input)
Standard
Symbol
tC
Parameter
Unit
Min.
62.5
25
Max.
External clock input cycle time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 5.35 Memory Expansion Mode and Microprocessor Mode
Standard
Unit
Symbol
Parameter
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
(NOTE 1) ns
(NOTE 2) ns
(NOTE 3) ns
Data input access time (when accessing multiplexed bus area)
40
30
40
0
ns
ns
ns
ns
ns
ns
Data input setup time
________
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
th(BCLK-RDY)
th(BCLK-HOLD)
0
RDY input hold time
__________
0
HOLD input hold time
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 45 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 45 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 45 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
Rev.2.40 Aug 25, 2006 page 55 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.36 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
100
40
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
40
Table 5.37 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
400
200
200
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.38 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
200
100
100
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.39 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
tw(TAH)
Parameter
Unit
Min.
100
100
Max.
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
tw(TAL)
Table 5.40 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
tc(UP)
Parameter
Unit
Min.
2000
1000
1000
400
Max.
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
TAiOUT input hold time
Table 5.41 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
800
200
200
Max.
TAiIN input cycle rime
TAiOUT input setup time
TAiIN input setup time
ns
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Rev.2.40 Aug 25, 2006 page 56 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.42 Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.43 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.44 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.45 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
_____________
tC(AD)
ADTRG input cycle time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG input LOW pulse width
Table 5.46 Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
70
90
RXDi input setup time
RXDi input hold time
_______
Table 5.47 External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
_______
tw(INH)
tw(INL)
INTi input HIGH pulse width
ns
ns
_______
INTi input LOW pulse width
Rev.2.40 Aug 25, 2006 page 57 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.48 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.12
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
NOTES:
HLDA output delay time
40
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
C
by a circuit of the right figure.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
30 pF
Figure 5.12 Port P0 to P10 Measurement Circuit
Rev.2.40 Aug 25, 2006 page 58 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.49 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.12
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
HLDA output delay time
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
– 40 [ns]
f(BCLK)
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
C
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Rev.2.40 Aug 25, 2006 page 59 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.50 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.12
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
25
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
25
40
RD signal output hold time
0
0
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
HLDA output delay time
40
15
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
–4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdZ(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 40 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 25 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 15 [ns]
Rev.2.40 Aug 25, 2006 page 60 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
t
h(TIN—UP) su(UP—TIN)
t
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
CLKi
tc(CK)
tw(CKH)
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 5.13 Timing Diagram (1)
Rev.2.40 Aug 25, 2006 page 61 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 5 V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Measuring conditions :
VCC = 5 V
Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V
Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V
Figure 5.14 Timing Diagram (2)
Rev.2.40 Aug 25, 2006 page 62 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 5 V
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
t
h(RD-AD)
-4ns.min
25ns.max
0ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac1(RD-DB)
(0.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
t
h(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
25ns.max
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.15 Timing Diagram (3)
Rev.2.40 Aug 25, 2006 page 63 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
h(RD-AD)
t
h(BCLK-ALE)
t
d(BCLK-ALE)
0ns.min
-4ns.min
25ns.max
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
25ns.max
0ns.min
t
ac2(RD-DB)
(1.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
h(RD-DB)
tSU(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
-4ns.min
25ns.max
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.16 Timing Diagram (4)
Rev.2.40 Aug 25, 2006 page 64 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
t
ac2(RD-DB)
(2.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.17 Timing Diagram (5)
Rev.2.40 Aug 25, 2006 page 65 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
tac2(RD-DB)
(3.5 ✕ tcyc-45)ns.max
Hi-Z
DBi
t
SU(DB-RD)
40ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
d(BCLK-ALE)
25ns.max
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.18 Timing Diagram (6)
Rev.2.40 Aug 25, 2006 page 66 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplexed bus selection)
VCC = 5 V
Read timing
BCLK
t
h(BCLK-CS)
t
d(BCLK-CS)
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
4ns.min
tcyc
25ns.max
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Address
Address
Data input
t
dZ(RD-AD)
8ns.max
t
h(RD-DB)
t
ac3(RD-DB)
tSU(DB-RD)
0ns.min
(1.5 ✕ tcyc-45)ns.max
40ns.min
t
d(AD-RD)
0ns.min
t
h(BCLK-AD)
t
d(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
t
h(BCLK-ALE)
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
25ns.max
-4ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
0ns.min
25ns.max
Write timing
BCLK
t
h(BCLK-CS)
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
tcyc
t
d(BCLK-CS)
4ns.min
25ns.max
CSi
t
h(BCLK-DB)
t
d(BCLK-DB)
4ns.min
40ns.max
ADi
Address
Data output
Address
/DBi
t
d(DB-WR)
t
h(WR-DB)
t
d(AD-ALE)
(1.5 ✕ tcyc-40)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-25)ns.min
t
d(BCLK-AD)
t
h(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-WR)
t
h(WR-AD)
25ns.max
-4ns.min
0ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
t
d(BCLK-WR)
t
h(BCLK-WR)
25ns.max
0ns.min
WR,WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.19 Timing Diagram (7)
Rev.2.40 Aug 25, 2006 page 67 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 5 V
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
Read timing
tcyc
BCLK
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-25)ns.min
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Data input
Address
t
h(RD-DB)
0ns.min
t
dZ(RD-AD)
t
ac3(RD-DB)
t
d(BCLK-AD)
8ns.max
t
SU(DB-RD)
40ns.min
td(AD-RD)
t
h(BCLK-AD)
4ns.min
25ns.max
(2.5 ✕ tcyc-45)ns.max
0ns.min
ADi
BHE
(no multiplex)
t
d(BCLK-ALE)
25ns.max
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
25ns.max
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-CS)
25ns.max
CSi
t
h(BCLK-DB)
4ns.min
t
d(BCLK-DB)
40ns.max
ADi
/DBi
Address
Data output
t
d(AD-ALE)
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-25)ns.min
(2.5 ✕ tcyc-40)ns.min
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex) td(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-4ns.min
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
25ns.max
WR, WRL
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 5 V
Input timing voltage : VIL = 0.8 V, VIH = 2.0 V
Output timing voltage : VOL = 0.4 V, VOH = 2.4 V
Figure 5.20 Timing Diagram (8)
Rev.2.40 Aug 25, 2006 page 68 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Table 5.51 Electrical Characteristics (1)
VCC = 3.3 V
Standard
Symbol
VOH
Parameter
Measuring Condition
Unit
Min. Typ. Max.
HIGH output
voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –1 mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0,
V
CC-0.5
VCC
V
P9_2 to P9_7, P10_0 to P10_7
VCC
VCC
V
V
V
XOUT
HIGHPOWER
LOWPOWER
VOH
VOL
HIGH output
voltage
IOH = –0.1 mA
IOH = –50 µA
V
V
CC-0.5
CC-0.5
2.5
1.6
XCOUT HIGHPOWER
HIGH output
voltage
With no load applied
With no load applied
IOL = 1 mA
LOWPOWER
0.5
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
LOW output
voltage
0.5
0.5
V
V
V
XOUT
HIGHPOWER
LOWPOWER
VOL
LOW output
voltage
IOL = 0.1 mA
IOL = 50 µA
0
0
XCOUT HIGHPOWER
LOW output
voltage
With no load applied
With no load applied
LOWPOWER
_________
HOLD, _R__D__Y__, TA0IN to TA4IN, TB0IN to TB5IN,
Hysteresis
VT+-VT-
0.2
0.2
0.8
I_N___T__0__ to INT5, NMI, ADTRG, C___T__S__0__ to CTS2,
________ _______ _____________
_________
SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,
TA0OUT to TA4OUT, _K__I_0_ to KI3,
_____
RXD0 to RXD2, SIN3
_____________
Hysteresis
VT+-VT-
IIH
RESET
1.8
4.0
V
HIGH input
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
µA
VI = 3.3 V
VI = 0 V
VI = 0 V
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
LOW input
current
IIL
µA
–4.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
____________
XIN, RESET, CNVSS, BYTE
RPULLUP Pull-up
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to
P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7
100
kΩ
50
500
resistance
RfXIN
Feedback resistance
XIN
MΩ
MΩ
V
3.0
25
RfXCIN
VRAM
Feedback resistance
RAM retention voltage
XCIN
At stop mode
2.0
NOTES:
1. Referenced to VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.
Rev.2.40 Aug 25, 2006 page 69 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.52 External Clock Input (XIN Input)
Standard
Symbol
tC
Parameter
Unit
Min.
62.5
25
Max.
External clock input cycle time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 5.53 Memory Expansion Mode and Microprocessor Mode
Standard
Unit
Symbol
Parameter
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
(NOTE 1) ns
(NOTE 2) ns
(NOTE 3) ns
Data input access time (when accessing multiplexed bus area)
50
40
50
0
ns
ns
ns
ns
ns
ns
Data input setup time
________
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
RDY input setup time
__________
HOLD input setup time
Data input hold time
________
th(BCLK-RDY)
th(BCLK-HOLD)
0
RDY input hold time
__________
0
HOLD input hold time
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 60 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 60 [ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 60 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
Rev.2.40 Aug 25, 2006 page 70 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.54 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
150
60
Max.
tc(TA)
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
60
Table 5.55 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
600
300
300
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.56 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
300
150
150
Max.
TAiIN input cycle time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 5.57 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
tw(TAH)
Parameter
Unit
Min.
150
150
Max.
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
tw(TAL)
Table 5.58 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
tc(UP)
Parameter
Unit
Min.
3000
1500
1500
600
Max.
TAiOUT input cycle time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
600
TAiOUT input hold time
Table 5.59 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
tc(TA)
Parameter
Unit
Min.
2
Max.
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
µs
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
500
500
Rev.2.40 Aug 25, 2006 page 71 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Timing Requirements
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.60 Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.61 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.62 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
tc(TB)
TBiIN input cycle time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 5.63 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
_____________
tC(AD)
ADTRG input cycle time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG input LOW pulse width
Table 5.64 Serial Interface
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TXDi output delay time
TXDi hold time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
160
0
100
90
RXDi input setup time
RXDi input hold time
_______
Table 5.65 External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
_______
tw(INH)
tw(INL)
INTi input HIGH pulse width
ns
ns
_______
INTi input LOW pulse width
Rev.2.40 Aug 25, 2006 page 72 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.66 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.21
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
30
25
30
30
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
NOTES:
HLDA output delay time
40
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
C
by a circuit of the right figure.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
30 pF
Figure 5.21 Port P0 to P10 Measurement Circuit
Rev.2.40 Aug 25, 2006 page 73 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.67 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.21
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
0
th(WR-AD)
(NOTE 1)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
30
25
30
30
40
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
4
–4
0
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
Data output delay time (in relation to BCLK)
(3)
Data output hold time (in relation to BCLK)
4
Data output delay time (in relation to WR)
(NOTE 2)
(NOTE 1)
(3)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
HLDA output delay time
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 109
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
– 40 [ns]
f(BCLK)
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
R
C
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
DBi
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.
Rev.2.40 Aug 25, 2006 page 74 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3 V
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.68 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Standard
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address output delay time
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5.21
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
50
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
40
40
50
RD signal output hold time
0
0
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
Data output hold time (in relation to WR)
__________
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
HLDA output delay time
40
25
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
–4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdZ(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 10 [ns]
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 109
– 50 [ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
f(BCLK)
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 40 [ns]
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 109
f(BCLK)
– 15 [ns]
Rev.2.40 Aug 25, 2006 page 75 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
t
h(TIN—UP) su(UP—TIN)
t
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
CLKi
tc(CK)
tw(CKH)
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 5.22 Timing Diagram (1)
Rev.2.40 Aug 25, 2006 page 76 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 3.3 V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
t
su(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
NOTE:
1. The above pins are set to high-impedance regardless of the input level of the BYTE pin,
the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.
Measuring conditions :
VCC = 3.3 V
Input timing voltage : Determined with VIL = 0.6 V, VIH = 2.7 V
Output timing voltage: Determined with VOL = 1.65 V, VOH = 1.65 V
Figure 5.23 Timing Diagram (2)
Rev.2.40 Aug 25, 2006 page 77 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 3.3 V
(For setting with no wait)
Read timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
t
h(RD-AD)
-4ns.min
30ns.max
0ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
30ns.max
0ns.min
t
ac1(RD-DB)
(0.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
t
h(RD-DB)
50ns.min
0ns.min
Write timing
BCLK
t
d(BCLK-CS)
t
h(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
h(WR-AD)
30ns.max
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
30ns.max
0ns.min
WR,WRL,
WRH
t
d(BCLK-DB)
t
h(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
t
d(DB-WR)
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.24 Timing Diagram (3)
Rev.2.40 Aug 25, 2006 page 78 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
VCC = 3.3 V
Memory Expansion Mode and Microprocessor Mode
(For 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
th(RD-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
td(BCLK-ALE)
30ns.max
ALE
RD
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
tac2(RD-DB)
(1.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
th(RD-DB)
0ns.min
tSU(DB-RD)
50ns.min
Write timing
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
(0.5 ✕ tcyc-40)ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.25 Timing Diagram (4)
Rev.2.40 Aug 25, 2006 page 79 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 3.3 V
(For 2-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
30ns.max
t
ac2(RD-DB)
(2.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
d(BCLK-ALE)
30ns.max
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
30ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(1.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.26 Timing Diagram (5)
Rev.2.40 Aug 25, 2006 page 80 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
VCC = 3.3 V
(For 3-wait setting and external area access)
Read timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(RD-AD)
0ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
RD
t
h(BCLK-RD)
0ns.min
t
d(BCLK-RD)
30ns.max
tac2(RD-DB)
(3.5 ✕ tcyc-60)ns.max
Hi-Z
DBi
t
SU(DB-RD)
50ns.min
t
h(RD-DB)
0ns.min
Write timing
tcyc
BCLK
t
h(BCLK-CS)
4ns.min
t
d(BCLK-CS)
30ns.max
CSi
t
h(BCLK-AD)
4ns.min
t
d(BCLK-AD)
30ns.max
ADi
BHE
t
d(BCLK-ALE)
30ns.max
t
h(WR-AD)
(0.5 ✕ tcyc-10)ns.min
t
h(BCLK-ALE)
-4ns.min
ALE
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
30ns.max
WR, WRL
WRH
t
d(BCLK-DB)
40ns.max
t
h(BCLK-DB)
4ns.min
Hi-Z
DBi
t
d(DB-WR)
(2.5 ✕ tcyc-40)ns.min
t
h(WR-DB)
(0.5 ✕ tcyc-10)ns.min
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.27 Timing Diagram (6)
Rev.2.40 Aug 25, 2006 page 81 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 2-wait setting, external area access and multiplexed bus selection)
VCC = 3.3 V
Read timing
BCLK
t
h(BCLK-CS)
t
d(BCLK-CS)
t
h(RD-CS)
(0.5 ✕ tcyc-10)ns.min
4ns.min
tcyc
40ns.max
CSi
t
d(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
t
h(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Address
Address
Data input
t
dZ(RD-AD)
8ns.max
t
h(RD-DB)
t
ac3(RD-DB)
tSU(DB-RD)
0ns.min
(1.5 ✕ tcyc-60)ns.max
50ns.min
t
d(AD-RD)
0ns.min
t
h(BCLK-AD)
t
d(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
t
h(BCLK-ALE)
t
h(RD-AD)
(0.5 ✕ tcyc-10)ns.min
40ns.max
-4ns.min
ALE
RD
t
d(BCLK-RD)
t
h(BCLK-RD)
0ns.min
40ns.max
Write timing
BCLK
t
h(BCLK-CS)
t
h(WR-CS)
(0.5 ✕ tcyc-10)ns.min
tcyc
t
d(BCLK-CS)
4ns.min
40ns.max
CSi
t
h(BCLK-DB)
t
d(BCLK-DB)
4ns.min
50ns.max
ADi
Address
Data output
Address
/DBi
t
d(DB-WR)
t
h(WR-DB)
t
d(AD-ALE)
(1.5 ✕ tcyc-50)ns.min
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-40)ns.min
t
d(BCLK-AD)
t
h(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-WR)
t
h(WR-AD)
40ns.max
-4ns.min
0ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
t
d(BCLK-WR)
t
h(BCLK-WR)
40ns.max
0ns.min
WR,WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.28 Timing Diagram (7)
Rev.2.40 Aug 25, 2006 page 82 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
5. Electric Characteristics (Normal-ver.)
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
VCC = 3.3 V
Read timing
tcyc
BCLK
th(RD-CS)
th(BCLK-CS)
6ns.min
(0.5 ✕ tcyc-10)ns.min
td(BCLK-CS)
40ns.max
CSi
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
th(ALE-AD)
(0.5 ✕ tcyc-15)ns.min
ADi
/DBi
Data input
Address
th(RD-DB)
tdZ(RD-AD)
8ns.max
0ns.min
tac3(RD-DB)
(2.5 ✕ tcyc-60)ns.max
td(BCLK-AD)
40ns.max
tSU(DB-RD)
50ns.min
td(AD-RD)
0ns.min
th(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
-4ns.min
(0.5 ✕ tcyc-10)ns.min
ALE
RD
th(BCLK-RD)
0ns.min
td(BCLK-RD)
40ns.max
Write timing
tcyc
BCLK
th(BCLK-CS)
th(WR-CS)
td(BCLK-CS)
40ns.max
4ns.min
(0.5 ✕ tcyc-10)ns.min
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5 ✕ tcyc-40)ns.min
td(DB-WR)
(2.5 ✕ tcyc-50)ns.min
th(WR-DB)
(0.5 ✕ tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex) td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
40ns.max
WR, WRL
WRH
1
tcyc =
f(BCLK)
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.29 Timing Diagram (8)
Rev.2.40 Aug 25, 2006 page 83 of 84
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N5)
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JB-A
Previous Code
100P6S-A
MASS[Typ.]
1.6g
HD
*1
D
80
51
81
50
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
19.8 20.0 20.2
13.8 14.0 14.2
2.8
100
31
A2
HD
HE
A
22.5 22.8 23.1
16.5 16.8 17.1
3.05
1
30
ZD
Index mark
F
A1
bp
c
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
L
0°
10°
*3
e
bp
y
e
y
0.5 0.65 0.8
0.10
0.575
Detail F
ZD
ZE
L
0.825
0.4 0.6 0.8
JEITA Package Code
RENESAS Code
PLQP0100KB-A
Previous Code
MASS[Typ.]
0.6g
P-LQFP100-14x14-0.50
100P6Q-A / FP-100U / FP-100UV
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
76
50
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
13.9 14.0 14.1
13.9 14.0 14.1
1.4
Terminal cross section
A2
HD
HE
A
15.8 16.0 16.2
15.8 16.0 16.2
1.7
100
26
A1
bp
b1
c
0.1
0.05
0.15
1
25
Index mark
0.15 0.20 0.25
0.18
ZD
F
0.145
0.125
0.09
0.20
c1
0°
8°
e
0.5
y
*3
x
L
0.08
0.08
bp
e
x
y
L1
ZD
ZE
L
1.0
1.0
0.5
1.0
Detail F
0.35
0.65
L1
Rev.2.40 Aug 25, 2006 page 84 of 84
REJ03B0004-0240
REVISION HISTORY
M16C/6N Group (M16C/6N5) Data Sheet
Description
Summary
Rev.
Date
Page
1.00 Jun. 30, 2003
2.00 Nov. 10, 2004
–
–
First edition issued
Revised edition issued
* Words standardizes (on-chip oscillator)
* 100P6Q-A (100-pin version) is added.
* Revised parts and revised contents are as follows (except for change of a layout
and an expressional change).
1
2
1. Overview 3rd line: "and LQFP" is added.
Table 1.1 Performance outline of M16C/6N Group (M16C/6N5)
• Operation Mode is added.
• Address Space is added.
• Power Consumption is revised.
• "LQFP" is added to Package.
4
Table 1.2 Product List is revised.
Figure 1.2 Type No., Memory Size, and Package:
• "GP: Package 100P6Q-A" is added to Package type.
Figure 1.3 Pin Configuration (Top View) (1): "ZP" is added.
Figure 1.4 Pin Configuration (Top View) (2) is added. (100P6Q-A)
Table 1.4 Pin Description (2): "ZP" is added to Timer A.
3. Memory
5
6
8
12
• 5th to 6th lines: The description about the flash memory version (block A) is added.
Figure 3.1 Memory Map
• Interenal ROM (data area) is added.
• NOTES 3, 4 are added and NOTE 5 is revised.
Table 4.1 SFR Information (1)
13
• The value of After Reset in PM1 register is revised.
• The value of After Reset in CM2 register is revised.
Table 4.7 SFR Information (7)
19
23
• The value of After Reset in FMR0 register is revised.
Table 4.11 SFR Information (11)
• The value of After Reset in U0C1 register is revised.
• The value of After Reset in U1C1 register is revised.
• NOTE 1 is added.
24
25
27
Table 4.12 SFR Information (12)
• The value of After Reset in DA0, DA1 registers are revised.
Table 5.1 Absolute Maximum Ratings
• "Flash Program Erase" in Operating Ambient Temperature is added.
Table 5.3 Recommended Operating Conditions (2)
• Parameters of Power Supply Ripple are added.
• NOTE 4 is revised.
Figure 5.1 Timing of Voltage Fluctuation is added.
Table 5.4 Electrical Characteristics (1): Hysteresis
28
• "CLK4" is revised to "CLK3", and "TA2OUT" is revised to "TA0OUT".
____________
• Max. of Standard in RESET is revised from "2.2" to "2.5".
• XIN is added.
A-1
REVISION HISTORY
M16C/6N Group (M16C/6N5) Data Sheet
Description
Summary
Rev.
Date
Page
2.00 Nov. 10, 2004
30
31
Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added.
Table 5.8 Power Supply Circuit Timing Characteristics: "td(M-L)" is deleted.
Figure 5.2 Power Supply Circuit Timing Diagram is added.
Table 5.10 Memory Expansion Mode and Microprocessor Mode: "td(BCLK-HLDA)" is deleted.
Table 5.21 Serial I/O: Min. of standard in tsu(D-C) is revised from "30" to "70".
Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
• td(BCLK-HLDA) is added.
32
34
35
36
37
38
Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting
and external area access)
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
• td(BCLK-HLDA) is added.
Table 5.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting,
external area access and multiplexed bus selection)
• td(BCLK-HLDA) is added.
• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".
Figure 5.4 Timing Diagram (1): "XIN input" is added.
40, 41 Figures 5.6 and 5.7 Timing Diagram (3) (4): "DB" in Read timing is revised to "DBi".
42, 43 Figures 5.8 and 5.9 Timing Diagram (5) (6): "DB" in Write timing is revised to "DBi".
45
Figure 5.11 Timing Diagram (8)
• "ADi/DB" in Read/Write timing is revised to "ADi/DBi".
Appendix 1. Package Dimensions: 100P6Q-A is added.
Revised edition issued
46
–
2.10 Jun. 24, 2005
* The contents of product are revised. (Normal-ver. is added.)
* Revised parts and revised contents are as follows (except for expressional change).
Table 1.1 Performance outline of M16C/6N Group (M16C/6N5)
• Performance outline of Normal-ver. is added.
2
4
Table 1.2 Product List is revised. (Normal-ver. is added.)
Figure 1.2 Type No., Memory Size, and Package:
• "(no): Normal-ver." is added to Characteristics.
19
28
Figure 4.7 SFR Information (7): NOTE 1 is revised.
Table 5.4 Electrical Characteristics (1)
• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.
Table 5.5 Electrical Characteristics (2): Mask ROM (5th item)
• “f(XCIN)” is changed to “(f(BCLK)).
29
30
–
Table 5.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
Revised edition issued
2.40 Aug. 25, 2006
* Electric Characteristics of Normal-ver. is added.
* Revised parts and revised contents are as follows (except for expressional change).
1.1 Applications: Comment of Normal-ver. is added.
Table 1.2 Product Information
1
4
• Status of development is revised and NOTES 1 and 2 are added.
A-2
REVISION HISTORY
M16C/6N Group (M16C/6N5) Data Sheet
Description
Summary
Rev.
Date
Page
2.40 Aug. 25, 2006
7, 8
9
Tables 1.3 and 1.4 List of Pin Names (1)(2) are added.
Table 1.5 Pin Functions (1)
• 3.0 to 5.5 V (Normal-ver.) is added to Description of Power supply input.
Table 4.8 SFR Information (8)
22
29
30
• The value of After Reset in IDB0 register is revised.
• The value of After Reset in IDB1 register is revised.
Table 5.3 Recommended Operating Conditions (2)
• Power supply ripple is deleted. (three items)
Figure 5.1 Voltage Fluctuation Timing is deleted.
Table 5.4 Electrical Characteristics (1): Hysteresis XIN is deleted.
48 to 83 5.2 Electrical Characteristics (Normal-ver.) is added.
A-3
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0
相关型号：
M306NAFGTFP
16-BIT, FLASH, 16MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
RENESAS
M306NAMCT-XXXFP
Microcontroller, 16-Bit, MROM, M16C CPU, 16MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
MITSUBISHI
M306NAMCV-XXXFP
Microcontroller, 16-Bit, MROM, M16C CPU, 16MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
MITSUBISHI
M306NAMCV-XXXFP
16-BIT, MROM, 16MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
RENESAS
M306NAMGT-XXXFP
Microcontroller, 16-Bit, MROM, M16C CPU, 16MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
MITSUBISHI
M306NAMGT-XXXFP
16-BIT, MROM, 16MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
RENESAS
M306NBFCTFP
Microcontroller, 16-Bit, FLASH, M16C CPU, 16MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
MITSUBISHI
M306NBMCT-XXXFP
16-BIT, MROM, 16MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
RENESAS
M306NBMCV-XXXFP
Microcontroller, 16-Bit, MROM, M16C CPU, 16MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
MITSUBISHI
©2020 ICPDF网 联系我们和版权申明