MC-22222361F9-E85X-CD5 [RENESAS]
MC-22222361F9-E85X-CD5;
| 型号： | MC-22222361F9-E85X-CD5 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | MC-22222361F9-E85X-CD5 CD |
| 文件： | 总28页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-22222361-X
MCP (MULTI-CHIP PACKAGE) FLASH MEMORY AND SRAM
64M-BIT PAGE MODE FLASH MEMORY AND 8M-BIT SRAM
Description
The MC-22222361-X is a stacked type MCP (Multi-Chip Package) of 67,108,864 bits (4,194,304 words by 16 bits)
flash memory and 8,388,608 bits (524,288 words by 16 bits) static RAM.
The MC-22222361-X is packaged in a 85-pin TAPE FBGA .
Features
General Features
• Fast access time : tACC = 80 ns (MAX.) (VCCf = 1.8 V), 85 ns (MAX.) (VCCf = 1.65 V) (Flash Memory),
tAA = 55 ns (MAX.) (SRAM)
• Supply voltage : -D80X : 1.8 to 2.1 V (Chip) / 2.7 to 3.1 V (I/O) (Flash Memory), 2.7 to 3.1 V (SRAM)
-E85X : 1.65 to 1.95 V (Chip) / 2.7 to 3.1 V (I/O) (Flash Memory), 2.7 to 3.1 V (SRAM)
• Output Enable input for easy application
• Wide operating temperature : TA = −25 to +85°C
Flash Memory Features
• Four bank organization enabling simultaneous execution of program / erase and read
• High-speed read with page mode
• Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
• Memory organization : 4,194,304 words × 16 bits
• Sector organization : 142 sectors (4K words × 16 sectors, 32K words × 126 sectors)
Boot sector allocated to the highest address (sector) and the lowest address (sector)
• 3-state output
• Automatic program
• Program suspend / resume
• Unlock bypass program
• Automatic erase
• Chip erase
• Sector erase (sectors can be combined freely)
• Erase suspend / resume
• Program / Erase completion detection
• Detection through data polling and toggle bits
• Detection through RY (/BY) pin
• Sector group protection
• Any sector group can be protected
• Any protected sector group can be temporary unprotected
• Any sector group can be unprotected
• Sectors can be used for boot application
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
Document No. M15854EJ4V0DS00 (4th edition)
Date Published November 2002 NS CP (K)
Printed in Japan
The mark # shows major revised points.
2002
MC-22222361-X
• Hardware reset and standby using /RESET pin
• Automatic sleep mode
• Boot block sector protect by /WP (ACC) pin
• Extra One Time Protect Sector provided
• Program / erase time
• Program : 11.0 µs / word (TYP.)
• Sector erase :
Program / erase cycle : 100,000 cycles
0.15 s (TYP.) (4K words sector), 0.5 s (TYP.) (32K words sector)
Program / erase cycle : 300,000 cycles
0.5 s (TYP.) (4K words sector), 0.7 s (TYP.) (32K words sector)
• Program / erase cycle : 300,000 cycles (MIN.)
SRAM Features
• Memory organization : 524,288 words × 16 bits
• Supply current : At operating : 30 mA (MAX.)
At standby : 15 µA (MAX.)
• Two Chip Enable inputs : /CE1s, CE2s
• Byte data control : /LB, /UB
• Low VCC data retention : 1.5 V (MIN.)
Ordering Information
Part number
Flash Memory
SRAM
Operating supply voltage
V
Package
Mounted
Access time Access time
Flash Memory
ns (MAX.)
80
ns (MAX.)
55
Chip
I/O
MC-22222361F9-D80X-CD5
1.8 to 2.1
(Flash
2.7 to 3.1
(Flash
85-pin
µPD29F064115-X
TAPE FBGA
(11 × 8)
Memory)
2.7 to 3.1
(SRAM)
1.65 to 1.95
(Flash
Memory)
MC-22222361F9-E85X-CD5
85
Memory)
2.7 to 3.1
(SRAM)
Bus Operations, COMMANDS, HARDWARE SEQUENCE FLAGS, HARD WARE DATA PROTECTION, READ
MODE REGISTER SETTINGS, TIMING CHARTS and FLOW CHARTS for Flash Memory, refer to PAGE MODE
FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
TIMING CHARTS OF SRAM FOR MCP, refer to SRAM AND MOBILE SPECIFIED RAM TIMING CHARTS FOR
MCP Information (M15819E).
Preliminary Data Sheet M15854EJ4V0DS
2
MC-22222361-X
Pin Configuration
/xxx indicates active low signal.
85-pin TAPE FBGA (11 × 8)
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
M
L K J H G F E D C B A
A
B
B
C
D
E
C
F G H J K L M
Top View
A
D
E
F
G
H
J
K
L
M
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
A16
IC
NC
NC
NC
NC
A15
A12
A21
A13
A9
V
CC
s
Vss
I/O7
NC
NC
A11
A8
A14
A10
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
I/O14
I/O5
A19
I/O6
I/O12
NC
NC
/WE
CE2s
A20
V
CCs
V
CCQf
NC
NC
/WP(ACC) /RESET RY(/BY)
VCC
f
I/O11
I/O2
I/O8
/LB
A7
/UB
A6
A18
A5
A17
A4
I/O1
Vss
A0
I/O10
I/O0
NC
NC
A3
A2
A1
/CEf
/CE1s
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Common Pins
A0 to A18 : Address Inputs
I/O0 to I/O15: Data Inputs / Outputs
Flash Memory Pins
A19 to A21 : Address Inputs
/CEf
: Chip Enable Input
/OE
: Output Enable Input
: Write Enable Input
: Ground
RY (/BY)
/RESET
: Ready (Busy) output
: Hardware reset Input
/WE
VSS
/WP(ACC) : Hardware Write Protect (Acceleration) Input
NC Note1
IC Note2
: No Connection
: Internal Connection
VCCf
: Supply Voltage
VCCQf
: Input / Output Supply Voltage
SRAM Pins
/CE1s
: Chip Enable 1 Input
: Chip Enable 2 Input
: Byte data select Input
: Supply Voltage
CE2s
/LB, /UB
VCCs
Notes 1. Some signals can be applied because this pin is not internally connected.
2. Any level (Vss, Vccf, Open) can be applied. Do not change the state during operation.
Remark Refer to Package Drawing for the index mark.
Preliminary Data Sheet M15854EJ4V0DS
3
MC-22222361-X
Block Diagram
V
CCf
V
SS
VCCQf
A0 to A21
A0 to A21
/RESET
/CEf
RY (/BY)
64 M-bit Flash Memory
(4,194,304 words by 16 bits)
/WP(ACC)
V
CCs
V
SS
I/O0 to I/O15
A0 to A18
8 M-bit SRAM
/WE
/OE
(524,288 words by 16 bits)
/CE1s
CE2s
/LB
/UB
Preliminary Data Sheet M15854EJ4V0DS
4
MC-22222361-X
Bus Operations
Operation
Flash Memory
SRAM
Common
/RESET /CEf /WP(ACC) /CE1S CE2S /LB /UB /OE /WE I/O0 to I/O7 I/O8 to I/O15
Full Standby
H
H
×
H
×
×
L
×
L
×
×
×
×
High-Z
High-Z
×
H
H
Output Disable
Flash Memory
Word Read Note 1
Word Write
H
L
×
H
×
×
H
H
High-Z
High-Z
H
H
L
L
×
×
Note 2
Note 2
L
H
L
Data Out
Data Out
H
Data In
Data In
High-Z or
Data In/Out Data In/Out
High-Z or
Temporary Sector Group Unprotect
VID
H
×
L
×
×
×
L
Note 2
Note 2
×
×
L
×
×
H
×
Automatic Sleep Mode
Data Out
High-Z or
Data In/Out Data In/Out
High-Z or High-Z or
Data In/Out Data In/Out
Data Out
High-Z or
Boot Block Sector Protect
×
×
×
×
×
Accelerated Mode
H
L
×
×
VACC
Note 2
×
×
×
×
Hardware Reset
SRAM
×
×
×
×
High-Z
High-Z
Word Read
Note 3
Note 3
L
H
H
L
L
H
L
L
H
L
Data Out
Data Out
High-Z
Lower byte read
Upper byte read
Word Write
H
L
High-Z
Data In
Data Out
Data In
High-Z
L
L
×
Lower byte read
Upper byte read
H
L
H
High-Z
Data In
Caution Other operations except for indicated in this table are inhibited.
Notes 1. When /OE = VIL, VIL can be applied to /WE. When /OE = VIH, a write operation is started. When /WE = VIL
and /OE = VIL, a write operation is started.
2. SRAM should be Standby.
3. Flash Memory should be Standby or Hardware reset.
Remarks 1. × : VIH or VIL, H : VIH, L : VIL, VID : 9.0 to 11.0 V, VACC : 8.5 to 9.5 V
2. Sector group protection and read the product ID are using a command.
3. If an address is held longer than the minimum read cycle time (tRC) in the flash memory read mode, the
automatic sleep mode is set.
Preliminary Data Sheet M15854EJ4V0DS
5
MC-22222361-X
Sector Organization / Sector Address Table ( Flash Memory )
(1/4)
Bank
Sector
Organization
K words
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank D
4
3FFFFFH
3FF000H
SA141
SA140
SA139
SA138
SA137
SA136
SA135
SA134
SA133
SA132
SA131
SA130
SA129
SA128
SA127
SA126
SA125
SA124
SA123
SA122
SA121
SA120
SA119
SA118
SA117
SA116
SA115
SA114
SA113
SA112
SA111
SA110
SA109
SA108
SA107
SA106
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
3FEFFFH
3FE000H
4
3FDFFFH
3FD000H
4
3FCFFFH
3FC000H
4
3FBFFFH
3FB000H
4
3FAFFFH
3FA000H
4
3F9FFFH
3F9000H
4
3F8FFFH
3F8000H
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3F7FFFH
3F0000H
3EFFFFH
3E8000H
3E7FFFH
3E0000H
3DFFFFH
3D8000H
3D7FFFH
3D0000H
3CFFFFH
3C8000H
3C7FFFH
3C0000H
3B7FFFH
3B8000H
3B7FFFH
3B0000H
3AFFFFH
3A8000H
3A7FFFH
3A0000H
39FFFFH
398000H
397FFFH
390000H
38FFFFH
388000H
387FFFH
380000H
Bank C
37FFFFH
378000H
377FFFH
370000H
36FFFFH
368000H
367FFFH
360000H
35FFFFH
358000H
357FFFH
350000H
34FFFFH
348000H
347FFFH
340000H
33FFFFH
338000H
337FFFH
330000H
32FFFFH
328000H
327FFFH
320000H
31FFFFH
318000H
Preliminary Data Sheet M15854EJ4V0DS
6
MC-22222361-X
(2/4)
Bank
Sector
Organization
K words
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank C
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
317FFFH
310000H
SA105
SA104
SA103
SA102
SA101
SA100
SA99
SA98
SA97
SA96
SA95
SA94
SA93
SA92
SA91
SA90
SA89
SA88
SA87
SA86
SA85
SA84
SA83
SA82
SA81
SA80
SA79
SA78
SA77
SA76
SA75
SA74
SA73
SA72
SA71
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
30FFFFH
308000H
307FFFH
300000H
2FFFFFH
2F8000H
2F7FFFH
2F0000H
2EFFFFH
2E8000H
2E7FFFH
2E0000H
2DFFFFH
2D8000H
2D7FFFH
2D0000H
2CFFFFH
2C8000H
2C7FFFH
2C0000H
2BFFFFH
2B8000H
2B7FFFH
2B0000H
2AFFFFH
2A8000H
2A7FFFH
2A0000H
29FFFFH
298000H
297FFFH
290000H
28FFFFH
288000H
287FFFH
280000H
27FFFFH
278000H
277FFFH
270000H
26FFFFH
268000H
267FFFH
260000H
25FFFFH
258000H
257FFFH
250000H
24FFFFH
248000H
247FFFH
240000H
23FFFFH
238000H
237FFFH
230000H
22FFFFH
228000H
227FFFH
220000H
21FFFFH
218000H
217FFFH
210000H
20FFFFH
208000H
207FFFH
200000H
Preliminary Data Sheet M15854EJ4V0DS
7
MC-22222361-X
(3/4)
Bank
Sector
Organization
K words
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank B
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1FFFFFH
1F8000H
SA70
SA69
SA68
SA67
SA66
SA65
SA64
SA63
SA62
SA61
SA60
SA59
SA58
SA57
SA56
SA55
SA54
SA53
SA52
SA51
SA50
SA49
SA48
SA47
SA46
SA45
SA44
SA43
SA42
SA41
SA40
SA39
SA38
SA37
SA36
SA35
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1F7FFFH
1F0000H
1EFFFFH
1E8000H
1E7FFFH
1E0000H
1DFFFFH
1D8000H
1D7FFFH
1D0000H
1CFFFFH
1C8000H
1C7FFFH
1C0000H
1BFFFFH
1B8000H
1B7FFFH
1B0000H
1AFFFFH
1A8000H
1A7FFFH
1A0000H
19FFFFH
198000H
197FFFH
190000H
18FFFFH
188000H
187FFFH
180000H
17FFFFH
178000H
177FFFH
170000H
16FFFFH
168000H
167FFFH
160000H
15FFFFH
158000H
157FFFH
150000H
14FFFFH
148000H
147FFFH
140000H
13FFFFH
138000H
137FFFH
130000H
12FFFFH
128000H
127FFFH
120000H
11FFFFH
118000H
117FFFH
110000H
10FFFFH
108000H
107FFFH
100000H
0FFFFFH
0F8000H
0F7FFFH
0F0000H
0EFFFFH
0E8000H
0E7FFFH
0E0000H
Preliminary Data Sheet M15854EJ4V0DS
8
MC-22222361-X
(4/4)
Bank
Sector
Organization
K words
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank B
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0DFFFFH
0D8000H
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
0
0D7FFFH
0D0000H
0CFFFFH
0C8000H
0C7FFFH
0C0000H
0BFFFFH
0B8000H
0B7FFFH
0B0000H
0AFFFFH
0A8000H
0A7FFFH
0A0000H
09FFFFH
098000H
097FFFH
090000H
08FFFFH
088000H
087FFFH
080000H
Bank A
07FFFFH
078000H
077FFFH
070000H
06FFFFH
068000H
067FFFH
060000H
05FFFFH
058000H
057FFFH
050000H
04FFFFH
048000H
047FFFH
040000H
03FFFFH
038000H
037FFFH
030000H
02FFFFH
028000H
027FFFH
020000H
01FFFFH
018000H
017FFFH
010000H
00FFFFH
008000H
SA8
007FFFH
SA7
007000H
4
006FFFH
006000H
SA6
4
005FFFH
SA5
005000H
4
004FFFH
004000H
SA4
4
003FFFH
SA3
003000H
4
002FFFH
002000H
SA2
4
001FFFH
SA1
001000H
4
000FFFH
000000H
SA0
Preliminary Data Sheet M15854EJ4V0DS
9
MC-22222361-X
Sector Group Address Table ( Flash Memory )
(1/2)
Sector group A21 A20
A19 A18
A17 A16
A15
0
0
0
0
0
0
0
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A14 A13
A12
0
Size
Sector
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
1
1
1
1
×
0
0
1
1
0
0
1
1
×
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
96K words (3 Sectors)
SA0
1
SA1
0
SA2
1
SA3
0
SA4
1
SA5
0
SA6
1
SA7
×
SA8 to SA10
SGA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
128K words (4 Sectors) SA11 to SA14
128K words (4 Sectors) SA15 to SA18
128K words (4 Sectors) SA19 to SA22
128K words (4 Sectors) SA23 to SA26
128K words (4 Sectors) SA27 to SA30
128K words (4 Sectors) SA31 to SA34
128K words (4 Sectors) SA35 to SA38
128K words (4 Sectors) SA39 to SA42
128K words (4 Sectors) SA43 to SA46
128K words (4 Sectors) SA47 to SA50
128K words (4 Sectors) SA51 to SA54
128K words (4 Sectors) SA55 to SA58
128K words (4 Sectors) SA59 to SA62
128K words (4 Sectors) SA63 to SA66
128K words (4 Sectors) SA67 to SA70
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
Remark × : VIH or VIL
Preliminary Data Sheet M15854EJ4V0DS
10
MC-22222361-X
(2/2)
Sector group A21 A20
A19 A18
A17 A16
A15
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
0
1
1
1
1
1
1
1
1
A14 A13
A12
×
Size
Sector
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
SGA39
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
1
1
1
1
1
1
1
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
128K words (4 Sectors) SA71 to SA74
128K words (4 Sectors) SA75 to SA78
128K words (4 Sectors) SA79 to SA82
128K words (4 Sectors) SA83 to SA86
128K words (4 Sectors) SA87 to SA90
128K words (4 Sectors) SA91 to SA94
128K words (4 Sectors) SA95 to SA98
128K words (4 Sectors) SA99 to SA102
128K words (4 Sectors) SA103 to SA106
128K words (4 Sectors) SA107 to SA110
128K words (4 Sectors) SA111 to SA114
128K words (4 Sectors) SA115 to SA118
128K words (4 Sectors) SA119 to SA122
128K words (4 Sectors) SA123 to SA126
128K words (4 Sectors) SA127 to SA130
96K words (3 Sectors) SA131 to SA133
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Remark × : VIH or VIL
Product ID Code ( Flash Memory )
Product ID Code
Code output
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
HEX
0010H
Manufacturer code
Device code
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
1
221CH
Sector group protection
0001HNote
Note If 0001H is output, the sector group is protected. If 0000H is output, the sector group is unprotected.
Preliminary Data Sheet M15854EJ4V0DS
11
MC-22222361-X
Command Sequence ( Flash Memory )
Command sequence
Bus
1st bus Cycle
2nd bus Cycle
3rd bus Cycle
4th bus Cycle
5th bus Cycle
6th bus Cycle
Cycle Address Data Address Data Address Data Address Data Address Data Address Data
Read / Reset Note1
Read / Reset Note1
1
3
4
1
1
6
6
1
1
3
2
2
2
2
3
×××H
555H
555H
BA
F0H
AAH
AAH
B0H
30H
AAH
AAH
B0H
30H
AAH
A0H
80H
80H
90H
AAH
RA
2AAH
2AAH
–
RD
55H
55H
–
–
555H
555H
–
–
F0H
A0H
–
–
RA
PA
–
–
RD
PD
–
–
–
–
–
–
–
–
–
Program
–
–
–
–
Program Suspend Note 2
Program Resume Note 3
Chip Erase
–
–
–
–
BA
–
–
–
–
–
–
–
–
–
–
555H
555H
BA
2AAH
2AAH
–
55H
55H
–
555H
555H
–
80H
80H
–
555H
555H
–
AAH
AAH
–
2AAH
55H
55H
–
555H
SA
–
10H
30H
–
Sector Erase
2AAH
Sector Erase Suspend Note 4, 5
Sector Erase Resume Note 4, 6
Unlock Bypass Set
Unlock Bypass Program Note 7
Unlock Bypass Chip Erase Note 7
Unlock Bypass Sector Erase Note 7
Unlock Bypass Reset Note 7
–
–
–
–
–
–
–
–
BA
–
–
–
–
–
–
–
–
–
555H
×××H
×××H
×××H
×××H
555H
2AAH
PA
55H
PD
10H
30H
555H
–
20H
–
–
–
–
–
–
–
–
–
–
–
×××H
SA
×××H 00HNote11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Product ID / Sector Group Protection
Information / Read Mode Register
Information
2AAH
55H
(BA)
555H
90H
IA
ID
–
–
–
Sector Group Protection Note 8
4
4
3
4
×××H
×××H
555H
555H
60H
60H
AAH
AAH
SPA
SUA
60H
60H
55H
55H
SPA
SUA
555H
555H
40H
40H
88H
90H
SPA
SUA
–
SD
SD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Sector Group Unprotect Note 9
Extra One Time Protect Sector Entry
Extra One Time Protect
Sector Reset Note 10
2AAH
2AAH
xxxH
00H
Extra One Time Protect Sector
Program Note 10
4
6
4
3
555H
555H
×××H
555H
AAH
AAH
60H
AAH
2AAH
2AAH
55H
55H
60H
55H
555H
555H
A0H
80H
40H
C0H
PA
555H
EOTPSA
–
PD
AAH
SD
–
–
2AAH
–
–
55H
–
–
–
30H
–
Extra One Time Protect
Sector Erase Note 10
EOTPSA
Extra One Time Protect Sector
Protection Note 10
–
–
EOTPSA
EOTPSA
Read Mode Register Set
2AAH
REGD
–
–
–
Notes 1. Both these read / reset commands reset the device to the read mode.
2. Programming is suspended if B0H is input to the bank address being programmed to in a program
operation.
3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend
operation.
4. If automatic erase resume and suspend are repeated at intervals of less than 100 µs, since it will become
suspend operation, without starting automatic erase, the erase operation may not be correctly completed.
5. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.
6. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend
operation.
7. Valid only in the unlock bypass mode.
8. Valid only when /RESET = VID (except in the Extra One Time Protect Sector mode).
9. The command sequence that protects a sector group is excluded.
10. Valid only in the Extra One Time Protect Sector mode.
11. This command can be used even if this data is F0H.
Preliminary Data Sheet M15854EJ4V0DS
12
MC-22222361-X
Remarks 1.
2.
The system should generate the following address pattern:
555H or 2AAH (A10 to A0)
RA
RD
IA
: Read address
: Read data
: Address input as follows
Information
A21 to A12
Bank address
Bank address
A11 to A4
A3 to A0
Manufacturer code
Device code
Don’t care
Don’t care
0000
0001
0010
0100
Sector group protection information Sector group address Don’t care
Read mode register information Bank address Don’t care
ID
: Code output. For the manufacture code, device code and sector group protection
information, refer to the Product ID code (Flash Memory). For read mode register
information, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
PA
PD
SA
: Program address
: Program data
: Erase sector address. The sector to be erased is selected by the combination of A21 to
A12. Refer to the Sector Organization / Sector Address Table (Flash Memory).
Bank address. Refer to the Sector Organization / Sector Address Table (Flash
Memory).
BA
:
SPA
: Sector group address to be protected or protection-verified. Set the sector group address
(SGA) and (A6, A3, A2, A1, A0) = (VIL, VIL, VIL, VIH, VIL).
Sector group protection can be set for each sector group address. For details, refer to
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information
(M15451E).
Refer to the Sector Group Address Table (Flash Memory) for the sector group address.
: Sector group address to be unprotected or unprotection-verified. Set the sector group
address (SGA) and (A6, A3, A2, A1, A0) = (VIH, VIL, VIL, VIH, VIL).
SUA
Sector group unprotect is performed for all sector group using a single command,
however, unprotect verification must be performed for each sector group address. For
details, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
Refer to the Sector Group Address Table (Flash Memory) for the sector group address.
EOTPSA : Extra One Time Protect Sector area addresses. These addresses are 000000H to
007FFFH.
SD
: Data for verifying whether sector groups read from the address specified by SPA, SUA,
EOTPSA are protected or unprotected.
Read mode register information. Description for setting, refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
REGD
:
3.
The sector group address is don't care except when a program / erase address or read address are
selected.
4. For the operation of bus, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
5.
× of address bit indicates VIH or VIL.
Preliminary Data Sheet M15854EJ4V0DS
13
MC-22222361-X
Electrical Specifications
Before turning on power, input VSS 0.2 V to the /RESET pin until VCCf ≥ VCCf (MIN.) and keep that state for 200 µs.
Absolute Maximum Ratings
Parameter
Symbol
Condition
with respect to VSS
Rating
Unit
V
Supply voltage
VCCf
–0.5 to +2.4
–0.5 Note 1 to +3.3
–0.5 to +4.0
VCCs
Input / Output supply
voltage
VCCQf with respect to VSS
V
V
Input / Output voltage
VT
with respect /WP(ACC), /RESET
–0.5 Note 2 to +13.0
to VSS
except /WP(ACC), /RESET
–0.5Note 1 to VCCQf + 0.4 (3.3 V MAX.),
–0.5 Note 1 to VCCs + 0.4 (3.3 V MAX.)
Ambient operation
temperature
TA
–25 to +85
°C
°C
Storage temperature
Tstg
–55 to +125
–25 to +85
Tbias
at bias
Notes 1. –1.5 V (MIN.) (pulse width ≤ 30 ns)
2. –2.0 V (MIN.) (pulse width ≤ 20 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCCf
Test condition
MIN.
1.8
TYP.
MAX.
2.1
Unit
V
-D80X
-E85X
1.65
2.7
1.95
VCCs
VCCQf
VIH
3.1
2.7
3.1
V
V
Input / Output supply voltage
High level input voltage
2.4
VCCQf +0.4,
VCCs +0.4
11.0
VID
VIL
High voltage is applied (/RESET)
High voltage is applied
9.0
–0.3Note
8.5
V
V
Low level input voltage
+0.5
Accelerated programming voltage VACC
Ambient operating temperature TA
9.5
V
–25
+85
°C
Note –1.0 V (MIN.) (pulse width = 20 ns)
Preliminary Data Sheet M15854EJ4V0DS
14
MC-22222361-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Flash Memory
(1/2)
Parameter
Symbol
Test condition
-D80X
TYP.
Unit
MIN.
MAX.
High level output voltage
Low level output voltage
Input leakage current
VOH
VOL
ILI1
IOH = −0.1 mA
VCCQf−0.1
V
V
IOL = 0.1 mA
0.1
1.0
35
VIN = VSS to VCCQf, VCCQf = VCCQf (MAX.)
/RESET = 11.0 V
µA
High voltage is applied
ILI2
I/O leakage current
Power Read
ILO
VI/O = VSS to VCCQf, VCCQf = VCCQf (MAX.)
/CEf = VIL, /OE = VIH, Cycle = 5 MHz,
IOUT = 0 mA
1.0
20
µA
ICC1
10
15
mA
supply
current Program, Erase
ICC2
/CEf = VIL, /OE = VIH,
35
25
mA
Automatic programming / erase
VCCf = VCCf (MAX.), /OE = VIL, /CEf = /RESET =
/WP(ACC) = VCCQf 0.3 V
Standby
ICC3
µA
Standby / Reset
ICC4
ICC5
ICC6
VCCf = VCCf (MAX.), /RESET = VSS 0.2 V
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
15
15
25
25
55
µA
µA
Automatic sleep mode
Read during
mA
programming
Read during erasing
ICC7
ICC8
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
/CEf = VIL, /OE = VIH,
55
35
mA
mA
Programming
during suspend
Automatic programming during suspend
/WP (ACC) pin
Accelerated
IACC
5
10
35
mA
V
programming
Low VCCf lock-out voltageNote
VCCf
15
VLKO
1.0
Note When VCCf is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Remark VIN : Input voltage, VI/O : Input / Output voltage
Preliminary Data Sheet M15854EJ4V0DS
15
MC-22222361-X
Flash Memory
Parameter
(2/2)
Symbol
Test condition
-E85X
TYP.
Unit
MIN.
MAX.
High level output voltage
Low level output voltage
Input leakage current
VOH
VOL
ILI1
IOH = −0.1 mA
VCCQf−0.1
V
V
IOL = 0.1 mA
0.1
1.0
35
VIN = VSS to VCCQf, VCCQf = VCCQf (MAX.)
/RESET = 11.0 V
µA
High voltage is applied
ILI2
I/O leakage current
Power Read
ILO
VI/O = VSS to VCCQf, VCCQf = VCCQf (MAX.)
/CEf = VIL, /OE = VIH, Cycle = 5 MHz,
IOUT = 0 mA
1.0
15
µA
ICC1
8
mA
supply
current Program, Erase
ICC2
/CEf = VIL, /OE = VIH,
25
25
mA
Automatic programming / erase
VCCf = VCCf (MAX.), /OE = VIL, /CEf = /RESET =
/WP(ACC) = VCCQf 0.3 V
Standby
ICC3
15
µA
Standby / Reset
ICC4
ICC5
ICC6
VCCf = VCCf (MAX.), /RESET = VSS 0.2 V
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
15
15
25
25
40
µA
µA
Automatic sleep mode
Read during
mA
programming
Read during erasing
ICC7
ICC8
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
/CEf = VIL, /OE = VIH,
40
25
mA
mA
Programming
during suspend
Automatic programming during suspend
/WP (ACC) pin
Accelerated
IACC
5
10
25
mA
V
programming
Low VCCf lock-out voltageNote
VCCf
12
VLKO
1.0
Note When VCCf is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Remark VIN : Input voltage, VI/O : Input / Output voltage
SRAM
Parameter
High level output voltage
Low level output voltage
Input leakage current
I/O leakage current
Symbol
VOH
VOL
Test condition
MIN. TYP. MAX. Unit
IOH = −0.1 mA
IOL = 0.1 mA
V
V
VCCs−0.1
0.1
ILI
VIN = 0 V to VCCs
–1.0
–1.0
+1.0
+1.0
µA
µA
ILO
VI/O = 0 V to VCCs, /CE1s = VIH or CE2s = VIL or /WE = VIL or
/OE = VIH
Power supply current
ICCA1
ICCA2
ICCA3
/CE1s = VIL, CE2s = VIH, II/O = 0 mA, Minimum cycle time
/CE1s = VIL, CE2s = VIH, II/O = 0 mA, Cycle time = ∞
/CE1s ≤ 0.2 V, CE2s ≥ VCCs – 0.2 V, VIL ≤ 0.2 V,
VIH ≥ VCCs – 0.2 V, II/O = 0 mA, Cycle time = 1 µs
/CE1s = VIH or CE2s = VIL or /LB = /UB = VIH
/CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
CE2s ≤ 0.2 V
–
–
–
30
5
mA
6
Standby supply current
ISB
–
0.6
15
15
15
mA
ISB1
ISB2
ISB3
1.0
1.0
1.0
µA
/LB = /UB ≥ VCCs − 0.2 V, /CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
Remarks 1. VIN : Input voltage, VI/O : Input / Output voltage
2. This DC Characteristic is in common regardless of product classification.
Preliminary Data Sheet M15854EJ4V0DS
16
MC-22222361-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ Flash Memory ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
V
CCQf
V
CCQf / 2
VCCQf / 2
Test Points
0 V
Output Waveform
V
CCQf / 2
VCCQf / 2
Test Points
Output Load
1 TTL + 30 pF
[ SRAM ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
0.9 VCC
s
s
V
CCs / 2
VCCs / 2
Test Points
0.1 VCC
Output Waveform
V
CCs / 2
VCCs / 2
Test Points
Output Load
1 TTL + 30 pF
Preliminary Data Sheet M15854EJ4V0DS
17
MC-22222361-X
/CEf, /CE1s, CE2s Timing
Parameter
Symbol
tCCR
Test Condition
MIN.
0
TYP.
MAX.
Unit
ns
Note
/CEf, /CE1s, CE2s recover time
Read Cycle (Flash Memory)
Parameter
Symbol
-D80X
-E85X
Unit Note
ns
MIN.
80
MAX.
80
MIN.
MAX.
85
Read cycle time
tRC
tACC
tPRC
tPACC
tCEf
85
Address access time
Page read cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
1
30
30
Page address access time
/CEf access time
30
80
25
25
30
85
25
25
1
2
/OE access time
tOE
Output disable time
Output hold time
tDF
tOH
0
0
/RESET pulse width
/RESET hold time before read
tRP
500
50
500
50
tRH
/RESET low
to read mode
At automatic mode
Except automatic mode
tREADY
20
20
500
500
/OE low level time from /WE high level
tOEH
20
20
Notes 1. /CEf = /OE = VIL
2. /OE = VIL
Remark
t
DF is the time from inactivation of /CEf or /OE to high impedance state output.
Preliminary Data Sheet M15854EJ4V0DS
18
MC-22222361-X
Write Cycle (Program /Erase) (Flash Memory)
Parameter Symbol
(1/2)
-D80X
TYP.
-E85X
Unit Note
MIN.
80
0
MAX.
MIN.
85
0
TYP.
MAX.
Write cycle time
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (/WE to address)
Address setup time (/CEf to address)
Address hold time (/WE to address)
Address hold time (/CEf to address)
Input data setup time
tAS
0
0
tAH
tAH
tDS
tDH
tOEH
45
45
45
0
45
45
45
0
Input data hold time
/OE hold time
Read
0
0
Toggle bit, Data polling
10
0
10
0
Read recovery time before write (/OE to /CEf)
Read recovery time before write (/OE to /WE)
/WE setup time (/CEf to /WE)
/CEf setup time (/WE to /CEf)
/WE hold time (/CEf to /WE)
/CEf hold time (/WE to /CEf)
Write pulse width
tGHEL
tGHWL
tWS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
0
0
0
0
tCS
0
0
tWH
0
0
tCH
0
0
tWP
35
35
30
30
35
35
30
30
/CEf pulse width
tCP
Write pulse width high
tWPH
tCPH
tWPG
tCPG
tSER
/CEf pulse width high
Word programming operation time
Chip programming operation time
11
47
200
840
1.0
11
47
200
840
1.0
Sector erase operation time
4K words sector
32K words sector
4K words sector
32K words sector
0.15
0.5
0.5
0.7
65.4
96.2
7
0.15
0.5
0.5
0.7
65.4
96.2
7
s
1,2
1,3
1.5
1.5
3.0
3.0
5.0
5.0
Chip erase operation time
tCER
205
678
150
205
678
150
s
1,2
1,3
Accelerated programming time
Program / Erase cycle
VCCf setup time
tACCPG
µs
cycle
µs
300,000
200
0
300,000
200
0
tVCS
tRB
RY (/BY) recovery time
/RESET pulse width
ns
tRP
500
20
500
20
ns
/RESET high-voltage (VID) hold time
from high of RY(/BY) when sector group is
temporarily unprotect
tRRB
µs
/RESET hold time
tRH
50
50
ns
Notes 1. The preprogramming time prior to the erase operation is not included.
2. Program / erase cycle : 100,000 cycles
3. Program / erase cycle : 300,000 cycles
Preliminary Data Sheet M15854EJ4V0DS
19
MC-22222361-X
Write Cycle (Program / Erase) (Flash Memory)
(2/2)
Parameter
Symbol
-D80X
TYP.
-E85X
TYP.
Unit Note
MIN.
MAX.
80
MIN.
MAX.
85
From completion of automatic program / erase to
data output time
tEOE
ns
ns
RY (/BY) delay time from valid program or erase
operation
tBUSY
80
85
Address setup time to /OE low in toggle bit
Address hold time to /CEf or /OE high in toggle bit
/CEf pulse width high for toggle bit
/OE pulse width high for toggle bit
Voltage transition time
tASO
tAHT
15
0
15
0
ns
ns
ns
ns
tCEPH
tOEPH
tVLHT
tVIDR
tVACCR
tTOW
tSPD
20
20
4
20
20
4
µs
ns
ns
µs
µs
1
Rise time to VID (/RESET)
500
500
50
500
500
50
Rise time to VACC (/WP(ACC))
Erase timeout time
2
2
Erase suspend transition time
20
20
Notes 1. Sector group protection only.
2. Table only.
Write operation (Program / Erase) Performance (Flash Memory)
Parameter Description
Sector erase time
The preprogramming time
MIN.
TYP.
MAX.
1.0
Unit Note
4K words sector
32K words sector
4K words sector
32K words sector
0.15
0.5
0.5
0.7
65.4
96.2
11
s
1
prior to the erase
1.5
operation is not included.
3.0
2
5.0
Chip erase time
The preprogramming time prior to
the erase operation is not included.
Excludes system-level overhead
Excludes system-level overhead
205
678
200
840
150
s
1
2
Word programming time
Chip programming time
µs
s
47
Accelerated programming time Excludes system-level overhead
Program / Erase cycle
7
µs
300,000
cycle
Notes 1. Program / erase cycle : 100,000 cycles
2. Program / erase cycle : 300,000 cycles
Preliminary Data Sheet M15854EJ4V0DS
20
MC-22222361-X
Read Cycle (SRAM)
Parameter
Symbol
tRC
MIN.
55
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
Read cycle time
Address access time
tAA
55
55
55
30
55
/CE1s access time
tCO1
tCO2
tOE
CE2s access time
/OE to output valid
/LB, /UB to output valid
Output hold from address change
/CE1s to output in Low-Z
CE2s to output in Low-Z
/OE to output in Low-Z
/LB, /UB to output in Low-Z
/CE1s to output in High-Z
CE2s to output in High-Z
/OE to output in High-Z
/LB, /UB to output in High-Z
tBA
tOH
5
5
5
0
5
tLZ1
2
tLZ2
tOLZ
tBLZ
tHZ1
tHZ2
tOHZ
tBHZ
20
20
20
20
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Write Cycle (SRAM)
Parameter
Write cycle time
Symbol
tWC
MIN.
55
50
50
50
50
0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
/CE1s to end of write
CE2s to end of write
/LB, /UB to end of write
Address valid to end of write
Address setup time
tCW1
tCW2
tBW
tAW
tAS
Write pulse width
tWP
45
0
Write recovery time
tWR
Data valid to end of write
Data hold time
tDW
25
0
tDH
/WE to output in High-Z
Output active from end of write
tWHZ
tOW
20
1
5
Note 1. The output load is 1TTL + 5 pF.
Preliminary Data Sheet M15854EJ4V0DS
21
MC-22222361-X
Low VCC Data Retention Characteristics (TA = −25 to +85°C) (SRAM)
Parameter
Symbol
Test Condition
MIN.
1.5
TYP.
MAX.
3.1
Unit
V
Data retention supply voltage
VCCDR1 /CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
VCCDR2 CE2s ≤ 0.2 V
1.5
3.1
VCCDR3 /LB = /UB ≥ VCCs − 0.2 V,
/CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
1.5
3.1
Data retention supply current
ICCDR1
VCCs = 1.5 V, /CE1s ≥ VCCs − 0.2 V,
CE2s ≥ VCCs − 0.2 V
0.5
6.0
µA
ICCDR2
ICCDR3
VCCs = 1.5 V, CE2s ≤ 0.2 V
0.5
0.5
6.0
6.0
VCCs = 1.5 V, /LB = /UB ≥ VCCs − 0.2 V,
/CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
Chip deselection to data retention mode
Operation recovery time
tCDR
tR
0
ns
ns
Note
tRC
Note tRC : Read cycle time
Preliminary Data Sheet M15854EJ4V0DS
22
MC-22222361-X
Package Drawing
85-PIN TAPE FBGA (11x8)
ZD
w
S
B
ZE
B
E
10
9
8
7
6
5
4
3
2
1
A
INDEX MARK
w
S
A
M L K J H G F E D C B A
A
A2
S
y1
S
S
y
e
A1
S
M
φ
φ
x
b
A B
ITEM MILLIMETERS
D
E
8.00 0.10
11.00 0.10
0.20
w
e
0.80
A
1.11 0.10
0.27 0.05
0.84
A1
A2
b
0.45 0.05
0.08
x
y
0.10
y1
ZD
ZE
0.20
0.40
1.10
P85F9-80-CD5
Preliminary Data Sheet M15854EJ4V0DS
23
MC-22222361-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the MC-22222361-X.
Type of Surface Mount Device
MC-22222361F9-CD5 : 85-pin TAPE FBGA (11 × 8)
Related Documents
Document Name
Document Number
M15451E
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information
SRAM AND MOBILE SPECIFIED RAM TIMING CHARTS FOR MCP Information
M15819E
Preliminary Data Sheet M15854EJ4V0DS
24
MC-22222361-X
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
3rd edition/ p.2
Previous
edition
(Previous edition → This edition)
p.2
Modification Mounted Flash Memory
Addition Pin Configuration
µPD29F064115-Y → µPD29F064115-X
Sep. 2002
p.3
p.3
Figures of top view and bottom view
p.13
p.16
p.13
p.16
Modification Command Sequence (Flash Memory) Remark 2: SPA, SUA
Modification DC Characteristics (SRAM)
Addition
ISB1, ISB2, ISB3 (TYP.): TBD → 1.0 µA
Remark 2
TOEH
p.18
p.18
Addition Read Cycle (Flash Memory)
pp.19, 20 pp.19, 20 Modification Accelerated programming time (MAX.) TBD → 150 µs
p.23
p.23
Modification Package Drawing
Preliminary version
→ Standard version
4th edition/ pp.1, 2
Nov. 2002
pp.1, 2
p.21
Modification General Features,
Ordering Information
SRAM Access time (MAX.):
70 ns → 55 ns
p.21
Modification Read Cycle (SRAM)
tRC (MIN.): 70 ns → 55 ns
tAA, tCO1, tCO2, tBA (MAX.): 70 ns → 55 ns
tOE (MAX.): 35 ns → 30 ns
tHZ1, tHZ2, tOHZ, tBHZ (MAX.): 25 ns → 20 ns
tWC (MIN.): 70 ns → 55 ns
tCW1, tCW2, tBW, tAW (MIN.): 55 ns → 50 ns
tWP (MIN.): 50 ns → 45 ns
tDW (MIN.): 30 ns → 25 ns
tWHZ (MAX.): 25 ns → 20 ns
Write Cycle (SRAM)
Preliminary Data Sheet M15854EJ4V0DS
25
MC-22222361-X
[MEMO]
Preliminary Data Sheet M15854EJ4V0DS
26
MC-22222361-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M15854EJ4V0DS
27
MC-22222361-X
•
The information in this document is current as of November, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such NEC Electronics products. No license, express, implied or
otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or
others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers
or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to
determine NEC Electronics's willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11
相关型号：
©2020 ICPDF网 联系我们和版权申明