MC-222272F9-B85X-BT3 [RENESAS]
IC,MIXED MEMORY,FLASH+SRAM,HYBRID,BGA,77PIN,PLASTIC;型号: | MC-222272F9-B85X-BT3 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | IC,MIXED MEMORY,FLASH+SRAM,HYBRID,BGA,77PIN,PLASTIC 静态存储器 内存集成电路 |
文件: | 总40页 (文件大小:250K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-222272-X
MCP (MULTI-CHIP PACKAGE) FLASH MEMORY AND SRAM
32M-BIT FLASH MEMORY AND 8M-BIT SRAM
Description
The MC-222272-X is a stacked type MCP (Multi-Chip Package) of 33,554,432 bits (BYTE mode : 4,194,304 words by
8 bits, WORD mode : 2,097,152 words by 16 bits) Flash Memory and 8,388,608 bits (BYTE mode : 1,048,576 words
by 8 bits, WORD mode : 524,288 words by 16 bits) Static RAM.
The MC-222272-X is packaged in a 77-pin TAPE FBGA.
Features
General Features
• Fast access time : tACC = 85 ns (MAX.) (Flash Memory), tAA = 70 ns (MAX.) (SRAM)
• Supply voltage : VCCf / VCCs = 2.7 to 3.6 V
• Wide operating temperature : TA = −25 to +85°C
Flash Memory Features
• Two bank organization enabling simultaneous
execution of program / erase and read
• Bank organization : 2 banks (4M bits + 28M bits)
• Memory organization :
• Sectors can be used for boot application
• Hardware reset and standby using /RESET pin
• Automatic sleep mode
• Boot block sector protect by /WP (ACC) pin
• Conforms to common flash memory interface (CFI)
• Extra One Time Protect Sector provided
4,194,304 words × 8 bits (BYTE mode)
2,097,152 words × 16 bits (WORD mode)
• Sector organization :
SRAM Features
71 sectors (8K bytes / 4K words × 8 sectors,
64K bytes / 32K words × 63 sectors)
• Boot sector allocated to the lowest address (sector)
• 3-state output
• Memory organization :
1,048,576 words × 8 bits (BYTE mode)
524,288 words × 16 bits (WORD mode)
• Supply current : At operating : 50 mA (MAX.)
At standby : 15 µA (MAX.)
• Automatic program
• Program suspend / resume
• Unlock bypass program
• Two Chip Enable inputs : /CE1s, CE2s
• Byte data select : /LB, /UB
• Automatic erase
• Chip erase
• BYTE / WORD mode select : CIOs
• Low VCC data retention : 1.0 to 3.6 V
• Sector erase (sectors can be combined freely)
• Erase suspend / resume
• Program / Erase completion detection
• Detection through data polling and toggle bits
• Detection through RY (/BY) pin
• Sector group protection
• Any sector can be protected
• Any protected sector can be temporary
unprotected
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15341EJ2V0DS00 (2nd edition)
Date Published March 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2001
©
MC-222272-X
Ordering Information
Part number
Flash Memory
Boot sector
Flash Memory
Access time
ns (MAX.)
SRAM
Package
Access time
ns (MAX.)
MC-222272F9-B85X-BT3
Bottom address (sector)
(B type)
85
70
77-pin TAPE FBGA (12 × 7)
Data Sheet M15341EJ2V0DS
2
MC-222272-X
Pin Configuration
/xxx indicates active low signal.
77-pin TAPE FBGA (12 × 7)
Top View
Bottom View
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P
P N M L K J H G F E D C B A
Top View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
A15
A12
NC
A13
NC
A14
A16
CIOf
V
SS
NC
NC
NC
NC
NC
A11
A8
SA I/O15, A-1 I/O7
I/O14
I/O5
A19
A9
A10
I/O6
I/O13 I/O12
/WE CE2s
A20
I/O4
I/O3
V
CC
s
CIOs
I/O11
I/O2
/WP(ACC) /RESET RY(/BY)
VCCf
/LB
A7
/UB
A18
A17
I/O1
I/O9 I/O10
/OE
I/O0
/CEf /CE1s
NC
NC
NC
NC
A6
A3
A5
A2
A4
A1
V
SS
I/O8
NC
NC
NC
NC
NC
NC
A0
NC
Common Pins
A0 - A18 : Address inputs
I/O0 - I/O15 : Data inputs / outputs
Flash Memory Pins
A19, A20 : Address inputs
I/O15, A−1 : Data inputs / outputs 15 (WORD mode)
/OE
: Output Enable
: Write Enable
: Ground
LSB address input (BYTE mode)
/WE
VSS
NC Note
/CEf
: Chip Enable
RY (/BY)
/RESET
VCCf
: Ready (Busy) output
: Hardware reset input
: Supply Voltage
: No Connection
/WP(ACC) : Hardware Write Protect (Acceleration)
CIOf
: Selects 8-bit or 16-bit mode
SRAM Pins
SA
: Address input (A19 for SRAM)
: Chip Enable 1
/CE1s
CE2s
: Chip Enable 2
VCCs
: Supply Voltage
/LB, /UB
CIOs
: Byte data select
: Selects 8-bit or 16-bit mode
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to Package Drawing for the index mark.
Data Sheet M15341EJ2V0DS
3
MC-222272-X
Block Diagram
V
CCf
V
SS
A0 - A20
A0 - A20
RY (/BY)
32 M-bit Flash Memory
/RESET
/CEf
4,194,304 words by 8 bits
2,097,152 words by 16 bits
CIOf
/WP(ACC)
V
CCs
V
SS
I/O0 - I/O15, A-1
A0 - A18
SA
/WE
8 M-bit SRAM
/OE
1,048,576 words by 8 bits
524,288 words by 16 bits
/CE1s
CE2s
/LB
/UB
CIOs
Data Sheet M15341EJ2V0DS
4
MC-222272-X
Bus Operations Table
Operation
Flash Memory
SRAM
Common
/RESET /CEf CIOf /WP(ACC) /CE1S CE2S /LB
/UB CIOs /OE /WE I/O0 - I/O7 I/O8-I/O15
Full standby
H
H
×
×
H
×
×
L
×
L
×
×
×
×
×
Hi-Z
Hi-Z
×
H
×
H
Output disable
H
H
L
L
×
L
×
×
H
×
×
H
L
H
H
Hi-Z
Hi-Z
Hi-Z
Read (Flash
Memory Note 1
Write (Flash
Memory)
BYTE mode
Note 2
Data Out
Data Out
Data In
Data In
Hi-Z or
)
WORD mode
BYTE mode
WORD mode
H
L
Data Out
Hi-Z
H
L
×
×
Note 2
Note 2
×
H
×
×
L
×
×
H
×
Data In
Hi-Z or
Temporary sector group
unprotect
VID
×
Data In/Out Data In/Out
Hi-Z or Hi-Z or
Data In/Out Data In/Out
Boot block sector protect
×
×
×
×
L
×
×
×
×
Flash Memory hardware reset
Read (SRAM) BYTE mode
WORD mode
L
×
×
×
L
L
×
H
H
×
×
L
×
×
L
H
L
×
L
H
L
×
L
×
L
L
×
H
H
Hi-Z
Hi-Z
Hi-Z
Note 3
Note 3
Data Out
Data Out
H
Data Out
Hi-Z
H
×
L
Hi-Z
Data Out
Hi-Z
Write (SRAM) BYTE mode
WORD mode
Note 3
Note 3
L
L
H
H
L
×
×
L
L
Data In
Data In
H
Data In
Hi-Z
H
Hi-Z
Data In
Caution Other operations except for indicated in this table are inhibited.
Notes 1. When /OE = VIL, VIL can be applied to /WE. When /OE = VIH, a write operation is started.
2. SRAM should be Standby.
3. Flash Memory should be Standby or Hardware reset.
Remarks 1. × : VIH or VIL, H: VIH, L: VIL
2. Sector group protection and read the product ID are using a command.
!
3. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for Bus
Operations of Flash Memory.
Data Sheet M15341EJ2V0DS
5
MC-222272-X
Sector Organization / Sector Address Table (Flash Memory)
Flash Memory bottom boot
(1/2)
Bank
Sector
Organization
K bytes / K words
64/32
Address
Sectors
Address
Sector Address Table
Bank Address Table
A20 A19 A18 A17 A16 A15 A14 A13 A12
BYTE mode WORD mode
Bank 2
3FFFFFH
3F0000H
1FFFFFH
1F8000H
FSA70
FSA69
FSA68
FSA67
FSA66
FSA65
FSA64
FSA63
FSA62
FSA61
FSA60
FSA59
FSA58
FSA57
FSA56
FSA55
FSA54
FSA53
FSA52
FSA51
FSA50
FSA49
FSA48
FSA47
FSA46
FSA45
FSA44
FSA43
FSA42
FSA41
FSA40
FSA39
FSA38
FSA37
FSA36
FSA35
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
3EFFFFH
3E0000H
3DFFFFH
3D0000H
3CFFFFH
3C0000H
3BFFFFH
3B0000H
3AFFFFH
3A0000H
39FFFFH
390000H
38FFFFH
380000H
37FFFFH
370000H
36FFFFH
360000H
35FFFFH
350000H
34FFFFH
340000H
33FFFFH
330000H
32FFFFH
320000H
31FFFFH
310000H
30FFFFH
300000H
2FFFFFH
2F0000H
2EFFFFH
2E0000H
2DFFFFH
2D0000H
2CFFFFH
2C0000H
2BFFFFH
2B0000H
2AFFFFH
2A0000H
29FFFFH
290000H
28FFFFH
280000H
27FFFFH
270000H
26FFFFH
260000H
25FFFFH
250000H
24FFFFH
240000H
23FFFFH
230000H
22FFFFH
220000H
21FFFFH
210000H
20FFFFH
200000H
1FFFFFH
1F0000H
1F7FFFH
1F0000H
1EFFFFH
1E8000H
1E7FFFH
1E0000H
1DFFFFH
1D8000H
1D7FFFH
1D0000H
1CFFFFH
1C8000H
1C7FFFH
1C0000H
1BFFFFH
1B8000H
1B7FFFH
1B0000H
1AFFFFH
1A8000H
1A7FFFH
1A0000H
19FFFFH
198000H
197FFFH
190000H
18FFFFH
188000H
187FFFH
180000H
17FFFFH
178000H
177FFFH
170000H
16FFFFH
168000H
167FFFH
160000H
15FFFFH
158000H
157FFFH
150000H
14FFFFH
148000H
147FFFH
140000H
13FFFFH
138000H
137FFFH
130000H
12FFFFH
128000H
127FFFH
120000H
11FFFFH
118000H
117FFFH
110000H
10FFFFH
108000H
107FFFH
100000H
0FFFFFH
0F8000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
0F7FFFH
0F0000H
0EFFFFH
0E8000H
0E7FFFH
0E0000H
Data Sheet M15341EJ2V0DS
6
MC-222272-X
(2/2)
Bank
Sector
Organization
K bytes / K words
64/32
Address
Sectors
Address
Sector Address Table
Bank Address Table
A20 A19 A18 A17 A16 A15 A14 A13 A12
BYTE mode WORD mode
Bank 2
1BFFFFH
1B0000H
0DFFFFH
0D8000H
FSA34
FSA33
FSA32
FSA31
FSA30
FSA29
FSA28
FSA27
FSA26
FSA25
FSA24
FSA23
FSA22
FSA21
FSA20
FSA19
FSA18
FSA17
FSA16
FSA15
FSA14
FSA13
FSA12
FSA11
FSA10
FSA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
1AFFFFH
1A0000H
19FFFFH
190000H
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
00E000H
00DFFFH
00C000H
00BFFFH
00A000H
009FFFH
008000H
007FFFH
006000H
005FFFH
004000H
0D7FFFH
0D0000H
0CFFFFH
0C8000H
0C7FFFH
0C0000H
0BFFFFH
0B8000H
0B7FFFH
0B0000H
0AFFFFH
0A8000H
0A7FFFH
0A0000H
09FFFFH
098000H
097FFFH
090000H
08FFFFH
088000H
087FFFH
080000H
07FFFFH
078000H
077FFFH
070000H
06FFFFH
068000H
067FFFH
060000H
05FFFFH
058000H
057FFFH
050000H
04FFFFH
048000H
047FFFH
040000H
03FFFFH
038000H
037FFFH
030000H
02FFFFH
028000H
027FFFH
020000H
01FFFFH
018000H
017FFFH
010000H
00FFFFH
008000H
007FFFH
007000H
006FFFH
006000H
005FFFH
005000H
004FFFH
004000H
003FFFH
003000H
002FFFH
002000H
Bank 1
FSA8
FSA7
8/4
FSA6
8/4
FSA5
8/4
FSA4
8/4
FSA3
8/4
FSA2
8/4
003FFFH
002000H
001FFFH
000000H
001FFFH
001000H
000FFFH
000000H
FSA1
8/4
FSA0
0
0
0
0
0
0
0
0
0
Data Sheet M15341EJ2V0DS
7
MC-222272-X
Sector Group Address Table (Flash Memory)
!
Sector group
SGA0
A20
0
A19
0
A18
0
A17
0
A16
0
0
0
0
0
0
0
0
0
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
0
1
A14
0
A13
0
A12
0
Size
Sector
8K Bytes (1 Sector)
8K Bytes (1 Sector)
8K Bytes (1 Sector)
8K Bytes (1 Sector)
8K Bytes (1 Sector)
8K Bytes (1 Sector)
8K Bytes (1 Sector)
8K Bytes (1 Sector)
FSA0
FSA1
FSA2
FSA3
FSA4
FSA5
FSA6
FSA7
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
×
×
×
192K Bytes (3 Sectors) FSA8–FSA10
SGA9
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
256K Bytes (4 Sectors) FSA11–FSA14
256K Bytes (4 Sectors) FSA15–FSA18
256K Bytes (4 Sectors) FSA19–FSA22
256K Bytes (4 Sectors) FSA23–FSA26
256K Bytes (4 Sectors) FSA27–FSA30
256K Bytes (4 Sectors) FSA31–FSA34
256K Bytes (4 Sectors) FSA35–FSA38
256K Bytes (4 Sectors) FSA39–FSA42
256K Bytes (4 Sectors) FSA43–FSA46
256K Bytes (4 Sectors) FSA47–FSA50
256K Bytes (4 Sectors) FSA51–FSA54
256K Bytes (4 Sectors) FSA55–FSA58
256K Bytes (4 Sectors) FSA59–FSA62
256K Bytes (4 Sectors) FSA63–FSA66
192K Bytes (3 Sectors) FSA67–FSA69
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
1
1
1
1
×
×
×
64K Bytes (1 Sector)
FSA70
Remark × : VIH or VIL
Data Sheet M15341EJ2V0DS
8
MC-222272-X
Command Sequence (Flash Memory)
Command sequence
Bus
1st bus Cycle
2nd bus Cycle
3rd bus Cycle
4th bus Cycle
5th bus Cycle
6th bus Cycle
Cycle Address Data Address Data Address Data Address Data Address Data Address Data
Read / Reset Note1
1
3
×××H
AAAH
555H
AAAH
555H
BA
F0H
AAH
RA
555H
2AAH
555H
2AAH
–
RD
–
–
–
–
–
–
–
–
–
–
–
–
Read / Reset Note1
BYTE mode
WORD mode
BYTE mode
WORD mode
55H
AAAH
555H
AAAH
555H
–
F0H
RA
RD
Program
4
AAH
55H
A0H
PA
PD
–
–
–
–
Program Suspend Note 2
Program Resume Note 3
Chip Erase
1
1
6
B0H
30H
AAH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BA
–
–
–
BYTE mode
WORD mode
BYTE mode
WORD mode
AAAH
555H
AAAH
555H
BA
555H
2AAH
555H
2AAH
–
55H
AAAH
555H
AAAH
555H
–
80H
AAAH
555H
AAAH
555H
–
AAH
555H
2AAH
555H
2AAH
–
55H
AAAH
555H
FSA
10H
Sector Erase
6
AAH
55H
80H
AAH
55H
30H
Sector Erase Suspend Note 4
1
1
3
B0H
30H
AAH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Sector Erase Resume Note 5
Unlock Bypass Set BYTE mode
WORD mode
BA
–
–
–
–
AAAH
555H
×××H
BA
555H
2AAH
PA
55H
AAAH
555H
–
20H
–
–
Unlock Bypass Program Note 6
Unlock Bypass Reset Note 6
2
2
3
A0H
90H
AAH
PD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
×××H 00HNote11
–
Product ID
BYTE mode
AAAH
555H
55H
(BA)
AAAH
(BA)
555H
SPA
SUA
–
90H
IA
ID
WORD mode
555H
2AAH
Sector Group Protection Note 7
Sector Group Unprotect Note 8
4
4
1
×××H
×××H
AAH
60H
60H
98H
SPA
SUA
–
60H
60H
–
40H
40H
–
SPA
SUA
–
SD
SD
–
–
–
–
–
–
–
–
–
–
–
–
–
Query Note 9
BYTE mode
WORD mode
Extra One Time Protect BYTE mode
Sector Entry WORD mode
Extra One Time Protect BYTE mode
Sector Program Note 10
WORD mode
Extra One Time Protect BYTE mode
Sector Erase Note 10
WORD mode
Extra One Time Protect BYTE mode
Sector Reset Note 10
WORD mode
55H
3
4
6
4
4
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
×××H
AAH
AAH
AAH
AAH
60H
555H
2AAH
555H
55H
55H
55H
55H
60H
AAAH
555H
88H
A0H
80H
90H
40H
–
–
–
–
–
–
–
–
–
–
AAAH
555H
PA
PD
2AAH
555H
AAAH
555H
AAAH
555H
xxxH
AAH
00H
SD
555H
2AAH
–
55H EOTPSA 30H
2AAH
555H
AAAH
555H
–
–
–
–
–
–
2AAH
EOTPSA
Extra One Time Protect Sector
Protection Note 10
–
EOTPSA
EOTPSA
Data Sheet M15341EJ2V0DS
9
MC-222272-X
Notes 1. Both these read / reset commands reset the device to the read mode.
2. Programming is suspended if B0H is input to the bank address being programmed to in a program
operation.
3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend
operation.
4. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.
5. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend
operation.
6. Valid only in the unlock bypass mode.
7. Valid only when /RESET = VID (except in the Extra One Time Protect Sector mode).
8. The command sequence that protects a sector group is excluded.
9. Only A0 to A6 are valid as an address.
10. Valid only in the Extra One Time Protect Sector mode.
11. This command can be used even if this data is F0H.
Remarks 1. Specify address 555H or 2AAH (A10 to A0) in the WORD mode, and AAAH or 555H (A10 to A0, A-1) in
the BYTE mode.
2. RA : Read address
RD : Read data
IA : Address input
xx00H (to read the manufacturer code)
xx02H (to read the device code in the BYTE mode)
xx01H (to read the device code in the WORD mode)
ID : Code output. Refer to the Product ID code (Manufacturer code / Device code) (Flash Memory).
PA : Program address
PD : Program data
FSA: Erase sector address. The sector to be erased is selected by the combination of this address.
Refer to the Sector Organization / Sector Address Table (Flash Memory).
BA : Bank address. Refer to the Sector Organization / Sector Address Table (Flash Memory).
SPA : Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (VIL,
VIH, VIL). For the sector group address, refer to the Sector Group Address Table (Flash
Memory).
!
!
SUA : Unprotect sector group address. Set sector group address (SGA) and (A6, A1, A0) = (VIH, VIH,
VIL). For the sector group address, refer to the Sector Group Address Table (Flash Memory).
SD : Data for verifying whether sector groups read from the address specified by SPA, SUA, and
EOTPSA are protected.
EOTPSA : Extra One Time Protect Sector area addresses.
BYTE mode : 000000H to 00FFFFH, WORD mode : 000000H to 007FFFH
3. The sector group address is don't care except when a program / erase address or read address are
selected.
4. For the operation of the bus, refer to Bus Operations Table.
5. × of address bit indicates VIH or VIL.
!
6. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for
Commands of Flash Memory.
Data Sheet M15341EJ2V0DS
10
MC-222272-X
Product ID Code (Manufacturer Code / Device Code) (Flash Memory)
Product ID Code
Address inputs
Output
HEX
A6
L
A1
L
A0
L
Manufacturer Code
Device code
10H
L
L
H
56H (BYTE mode),
2256H (WORD mode)
Product ID Code
Code outputs
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
HEX
15 14 13 12 11 10
9
0
x
1
8
0
x
0
7
0
0
0
6
0
1
1
5
0
0
0
4
1
1
1
3
0
0
0
2
0
1
1
1
0
1
1
0
0
0
0
Manufacturer Code
Device code BYTE mode
WORD mode
0
A-1
0
0
x
0
0
x
1
0
x
0
0
x
0
0
x
0
10H
56H
2256H
Remark H : VIH, L : VIL, x : Hi-Z
!
Hardware Sequence Flags, Hardware Data Protection (Flash Memory)
Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E).
Data Sheet M15341EJ2V0DS
11
MC-222272-X
Electrical Specifications
Before turning on power, input VSS ± 0.2 V to the /RESET pin until VCCf ≥ VCCf (MIN.).
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Condition
Rating
Unit
V
VCCf, VCCs with respect to VSS
–0.5 to +4.0
Input / Output voltage
VT
TA
with respect /WP(ACC), /RESET
–0.5 Note 1 to +13.0
except /WP(ACC), /RESET –0.5Note 1 to VCCf, VCCs + 0.4 (4.0 V MAX.) Note 2
–25 to +85
V
to VSS
Ambient operation
temperature
°C
°C
Storage temperature
Tstg
–55 to +125
Notes 1. –2.0 V (MIN.) (pulse width ≤ 20 ns)
2. VCCf, VCCs + 0.5 V (MAX.) (pulse width ≤ 20 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCCf, VCCs
TA
Condition
MIN.
2.7
TYP.
MAX.
3.6
Unit
V
Supply voltage
Ambient operation temperature
–25
+85
°C
Data Sheet M15341EJ2V0DS
12
MC-222272-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Common
Parameter
Symbol
VIH
Test condition
MIN.
2.4
TYP.
MAX.
VCCf, VCCs + 0.3
+0.5
Unit
V
High level input voltage
Low level input voltage
High level output voltage
VIL
−0.3
2.4
V
VOH
IOH = −500 µA, VCCf = VCCf (MIN.),
VCCs = VCCs (MIN.)
V
Low level output voltage
VOL
IOL = +1.0 mA, VCCf = VCCf (MIN.),
VCCs = VCCs (MIN.)
0.4
V
Input leakage current
Output leakage current
ILI
−1.0
−1.0
+1.0
+1.0
µA
µA
ILO
Flash Memory
Parameter
Symbol
ICC1f
Test condition
MIN.
TYP. MAX. Unit
Power
supply
current
Read
BYTE mode
VCCf = VCCf (MAX.),
/CEf = VIL, /OE = VIH
tCYCLE = 5 MHz
tCYCLE = 1 MHz
tCYCLE = 5 MHz
tCYCLE = 1 MHz
10
2
16
4
mA
WORD mode
10
2
16
4
Program, Erase
Standby
ICC2f
ICC3f
VCCf = VCCf (MAX.), /CEf = VIL, /OE = VIH
VCCf = VCCf (MAX.), /CEf = /RESET =
/WP(ACC) = VCCf ± 0.3 V, /OE = VIL
VCCf = VCCf (MAX.), /RESET = VSS ± 0.2 V
VIH = VCCf ± 0.2 V, VIL = VSS ± 0.2 V
VIH = VCCf ± 0.2 V, VIL = VSS ± 0.2 V
VIH = VCCf ± 0.2 V, VIL = VSS ± 0.2 V
/CEf = VIL, /OE = VIH,
15
0.2
30
5
mA
µA
Standby / Reset
Automatic sleep mode
Read during programming
Read during erasing
Programming
ICC4f
ICC5f
ICC6f
ICC7f
ICC8f
0.2
0.2
21
5
µA
µA
5
45
45
35
mA
mA
mA
21
17
during suspend
Automatic programming during suspend
/WP (ACC) pin
Accelerated
IACC
5
10
30
mA
programming
VCCf
15
/RESET high level input voltage
Accelerated programming voltage
Low VCCf lock-out voltageNote
VID
High Voltage is applied
11.5
8.5
12.5
9.5
1.7
V
V
V
VACC
VLKO
High Voltage is applied
!
Note When VCCf is equal to or lower than VLKO, the device ignores all write cycles. Refer to DUAL OPERATION
FLASH MEMORY 32M BITS A SERIES Information (M14914E).
SRAM
Parameter
Symbol
ICC1S
Test condition
MIN.
TYP. MAX. Unit
Power supply current
/CE1s = VIL, CE2s = VIH, Minimum cycle time, II/O = 0 mA
/CE1s = VIL, CE2s = VIH, II/O = 0 mA, Cycle time = ∞
/CE1s ≤ 0.2 V, CE2s ≥ VCCs – 0.2 V, Cycle time = 1 µs,
II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCCs – 0.2 V
–
–
–
50
12
10
mA
ICC2S
Standby supply current
ISB1S
ISB2S
/CE1s = VIH or CE2s = VIL or /LB = /UB = VIH
/CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
CE2s ≤ 0.2 V
–
1
1
1
0.6
15
15
15
mA
µA
/LB = /UB ≥ VCCs − 0.2 V, /CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
Data Sheet M15341EJ2V0DS
13
MC-222272-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Flash Memory
!
Input Waveform (Rise and Fall Time ≤ 5 ns)
3.0 V
1.5 V
Test Points
1.5 V
V
SS
Output Waveform
1.5 V
Test Points
1.5 V
Output Load
1 TTL + 30 pF
SRAM
Input Waveform (Rise and Fall Time ≤ 5 ns)
V
CCs x 0.9 V
V
CCs / 2 V
Test points
VCCs / 2 V
V
CCs x 0.1 V
Output Waveform
V
CCs / 2 V
Test points
VCCs / 2 V
Output Load
1 TTL + 30 pF
/CEf, /CE1s, CE2s Timing
Parameter
Symbol
tCCR
Test Condition
MIN.
0
TYP.
MAX.
Unit
ns
Notes
/CEf, /CE1s, CE2s recover time
Data Sheet M15341EJ2V0DS
14
MC-222272-X
Read Cycle (Flash Memory)
Parameter
Read cycle time
Symbol
tRC
Test Condition
MIN.
85
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Notes
Address access time
/CEf access time
tACC
/CEf = /OE = VIL
85
85
40
30
tCEf
/OE = VIL
/OE access time
tOE
/CEf = VIL
Output disable time
tDF
/OE = VIL or /CEf = VIL
Output hold time
tOH
0
/RESET pulse width
/RESET hold time before read
/RESET low to read mode
/CEf low to CIOf low, high
CIOf low output disable time
CIOf high access time
tRP
500
50
tRH
tREADY
tELFL/tELFH
tFLQZ
tFHQV
20
5
30
85
Remark
t
DF is the time from inactivation of /CEf or /OE to Hi-Z state output.
Data Sheet M15341EJ2V0DS
15
MC-222272-X
Write Cycle (Program / Erase) (Flash Memory)
Parameter
Write cycle time
Symbol
tWC
tAS
MIN.
85
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Address setup time (/WE to address)
Address setup time (/CEf to address)
Address hold time (/WE to address)
Address hold time (/CEf to address)
Input data setup time
tAS
0
tAH
45
45
35
0
tAH
tDS
Input data hold time
tDH
/OE hold time
Read
tOEH
0
Toggle bit, Data polling
10
0
Read recovery time before write (/OE to /CEf)
Read recovery time before write (/OE to /WE)
/WE setup time (/CEf to /WE)
/CEf setup time (/WE to /CEf)
/WE hold time (/CEf to /WE)
tGHEL
tGHWL
tWS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
s
0
0
tCS
0
tWH
0
/CEf hold time (/WE to /CEf)
tCH
0
Write pulse width
tWP
35
35
30
30
/CEf pulse width
tCP
Write pulse width high
tWPH
tCPH
tBPG
tWPG
tSER
tVCS
tRB
/CEf pulse width high
Byte programming operation time
Word programming operation time
Sector erase operation time
9
200
200
5
11
0.7
1
VCCf setup time
50
0
µs
ns
ns
µs
RY (/BY) recovery time
/RESET pulse width
tRP
500
20
/RESET high-voltage (VID) hold time from high of RY(/BY)
when sector group is temporarily unprotect
/RESET hold time
tRRB
tRH
50
ns
ns
From completion of automatic program / erase to data
output time
tEOE
85
90
RY (/BY) delay time from valid program or erase operation
Address setup time to /OE low in toggle bit
Address hold time to /CEf or /OE high in toggle bit
/CEf pulse width high for toggle bit
/OE pulse width high for toggle bit
Voltage transition time
tBUSY
tASO
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
15
0
tAHT
tCEPH
tOEPH
tVLHT
tVIDR
tVACCR
tTOW
tSPD
20
20
4
2
3
2
4
4
Rise time to VID (/RESET)
500
500
50
Rise time to VACC (/WP(ACC))
Erase timeout time
Erase suspend transition time
20
Notes 1. The preprogramming time prior to the erase operation is not included.
2. Sector group protection and accelerated mode only
3. Sector group protection only.
4. Table only.
Data Sheet M15341EJ2V0DS
16
MC-222272-X
Write Operation (Program / Erase) Performance (Flash Memory)
Parameter
Sector erase time
Description
Excludes programming time prior to erasure
Excludes programming time prior to erasure
Excludes system-level overhead
Excludes system-level overhead
Excludes system-level overhead BYTE mode
WORD mode
MIN.
TYP.
0.7
50
9
MAX.
5
Unit
s
Chip erase time
s
Byte programming time
Word programming time
Chip programming time
200
200
µs
µs
s
11
40
25
7
Accelerated programming time
Erase / Program cycle
Excludes system-level overhead
150
µs
100,000
cycles
Data Sheet M15341EJ2V0DS
17
MC-222272-X
Read Cycle (SRAM)
Parameter
Symbol
tRC
MIN.
70
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
/CE1s access time
tAA
70
70
70
35
70
tCO1
tCO2
tOE
CE2s access time
/OE to output valid
/LB, /UB to output valid
Output hold from address change
/CE1s to output in Low-Z
CE2s to output in Low-Z
/OE to output in Low-Z
/LB, /UB to output in Low-Z
/CE1s to output in Hi-Z
CE2s to output in Hi-Z
/OE to output in Hi-Z
/LB, /UB to output in Hi-Z
tBA
tOH
10
10
10
0
tLZ1
tLZ2
tOLZ
tBLZ
tHZ1
tHZ2
tOHZ
tBHZ
10
25
25
25
25
Write Cycle (SRAM)
Parameter
Write cycle time
Symbol
tWC
MIN.
70
55
55
55
55
0
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
/CE1s to end of write
CE2s to end of write
/LB, /UB to end of write
Address valid to end of write
Address setup time
tCW1
tCW2
tBW
tAW
tAS
Write pulse width
tWP
50
0
Write recovery time
tWR
Data valid to end of write
Data hold time
tDW
30
0
tDH
/WE to output in Hi-Z
Output active from end of write
tWHZ
tOW
25
5
Data Sheet M15341EJ2V0DS
18
MC-222272-X
Low VCC Data Retention Characteristics (SRAM)
Parameter
Symbol
Test Condition
MIN.
1.0
TYP.
MAX.
3.6
Unit
V
Data retention supply voltage
VCCDR1 /CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
VCCDR2 CE2s ≤ 0.2 V
1.0
3.6
VCCDR3 /LB = /UB ≥ VCCs − 0.2 V,
/CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
1.0
3.6
Data retention supply current
ICCDR1
VCCs = 1.5 V, /CE1s ≥ VCCs − 0.2 V,
CE2s ≥ VCCs − 0.2 V
0.5
6
µA
ICCDR2
ICCDR3
VCCs = 1.5 V, CE2s ≤ 0.2 V
0.5
0.5
6
6
VCCs = 1.5 V, /LB = /UB ≥ VCCs − 0.2 V,
/CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
Chip deselection to data retention mode
Operation recovery time
tCDR
tR
0
ns
ns
Note
tRC
Note tRC : Read cycle time
Data Sheet M15341EJ2V0DS
19
MC-222272-X
Figure 1. Alternating SRAM to Flash Memory Timing Chart
/CEf (Input)
tCCR
tCCR
/CE1s (Input)
tCCR
tCCR
CE2s (Input)
Figure 2. Read Cycle Timing Chart 1 (Flash Memory)
t
RC
Address (Input)
/CEf (Input)
/OE (Input)
t
ACC
t
CEf
t
DF
t
OEH
t
OE
t
OH
/WE (Input)
I/O (Output)
Hi-Z
Hi-Z
Data out
Figure 3. Read Cycle Timing Chart 2 (Flash Memory)
t
RC
Address (Input)
/RESET (Input)
/CEf (Input)
t
RP
t
RH
t
ACC
t
READY
t
CEf
t
OH
Hi-Z
Hi-Z
I/O (Output)
Data out
Data Sheet M15341EJ2V0DS
20
MC-222272-X
Figure 4. Sector Group Protection Timing Chart (Flash Memory)
VCCf
t
VCS
V
V
ID
IH
t
VIDR
VLHT
WC
/RESET (Input)
t
t
t
WC
Address (Input)
SGAx
SGAx
SGAy
A0 (Input)
A1 (Input)
A6 (Input)
/CEf (Input)
/OE (Input)
t
WP
TIMEOUT
/WE (Input)
t
OE
01HNote
60H
I/O (Input/Output)
60H
60H
40H
Note The sector group protection verification result is output.
01H : The sector group is protected.
00H : The sector group is not protected.
Figure 5. Temporary Sector Group Unprotect Timing Chart (Flash Memory)
VCCf
t
VCS
t
VLHT
t
VIDR
V
V
ID
IH
/RESET (Input)
t
RRB
(Program or erase command sequence)
/WE (Input)
/CEf (Input)
t
VLHT
t
VLHT
RY (/BY) (Output)
Period during which
protection is canceled
Data Sheet M15341EJ2V0DS
21
MC-222272-X
Figure 6. Accelerated Mode Timing Chart (Flash Memory)
VCCf
t
VCS
t
VLHT
t
VACCR
V
ACC
IH
V
/WP (ACC) (Input)
(Program or erase command sequence)
/WE (Input)
/CEf (Input)
t
VLHT
t
VLHT
RY (/BY) (Output)
Accelerated mode period
Figure 7. Dual Operation Timing Chart (Flash Memory)
t
RC
t
WC
t
RC
t
WC
t
RC
t
WC
Address (Input)
/CEf (Input)
BA1
BA2
BA1
BA2
BA1
BA2
t
AH
t
AS
t
ACC
t
AS
t
AHT
t
CEPH
t
CEf
/OE (Input)
/WE (Input)
t
GHWL
t
WP
t
OEH
t
OE
t
DF
t
DF
t
DS
t
DH
I/O (Input / Output)
Output
Input
Output
Input
Output
Status
Data Sheet M15341EJ2V0DS
22
MC-222272-X
Figure 8. Write Cycle Timing Chart (/WE Controlled) (Flash Memory)
(3rd and 4th write cycle)
(Data polling)
t
WC
t
AS
Address (Input)
/CEf (Input)
555H
PA
PA
t
AH
t
RC
t
CH
t
CEf
t
GHWL
/OE (Input)
/WE (Input)
t
BPG or tWPG
t
WP
t
WPH
t
CS
t
OE
t
DH
I/O (Input / Output)
A0H
PD
/I/O7
D
OUT
DOUT
t
DS
t
OH
Remarks 1. This timing chart shows the last two write cycles among the program command sequence's four write
cycles, and data polling.
2. This timing chart shows the WORD mode’s case. In the BYTE mode, address to be input
are different from the WORD mode. See Command Sequence (Flash Memory).
3. PA : Program address
PD : Program data
/I/O7 : The output of the complement of the data written to the device.
DOUT : The output of the data written to the device.
Figure 9. Write Cycle Timing Chart (/CEf Controlled) (Flash Memory)
(3rd and 4th write cycle)
(Data polling)
t
WC
t
AS
Address (Input)
/CEf (Input)
555H
PA
PA
t
AH
t
RC
t
CP
t
CPH
t
CEf
t
GHEL
/OE (Input)
/WE (Input)
t
BPG or tWPG
t
WH
t
WS
t
DS
DH
t
OE
t
I/O (Input / Output)
A0H
PD
/I/O7
D
OUT
DOUT
t
OH
Remarks 1. This timing chart shows the last two write cycles among the program command sequence's four write
cycles, and data polling.
2. This timing chart shows the WORD mode’s case. In the BYTE mode, address to be input
are different from the WORD mode. See Command Sequence (Flash Memory).
3. PA : Program address
PD : Program data
/I/O7 : The output of the complement of the data written to the device.
DOUT : The output of the data written to the device.
Data Sheet M15341EJ2V0DS
23
MC-222272-X
Figure 10. Sector / Chip Erase Timing Chart (Flash Memory)
t
WC
t
AS
FSANote
Address (Input)
/CEf (Input)
555H
2AAH
555H
555H
2AAH
t
AH
t
CS
t
CH
/OE (Input)
/WE (Input)
I/O (Input)
t
WP
t
GHWL
t
WPH
t
DS
(10H for chip erase)
30H
t
DH
AAH
55H
80H
AAH
55H
t
VCS
VCCf
Note FSA is the sector address to be erased. In the case of chip erase, input 555H (WORD mode), AAAH (BYTE
mode).
Remark This timing chart shows the WORD mode’s case. In the BYTE mode, address to be input are different from
the WORD mode. See Command Sequence (Flash Memory)..
Figure 11. Data Polling Timing Chart (Flash Memory)
/CEf (Input)
t
OE
t
CH
t
DF
/OE (Input)
/WE (Input)
t
OEH
t
CEf
t
BPG,
t
WPG,
t
SER
Hi-Z
Hi-Z
Note
I/O7 (Output)
/I/O7
D
OUT
Status data
Valid data
I/O0 - I/O6 (Output)
RY (/BY) (Output)
t
BUSY
t
EOE
Note I/O7 = DOUT : True value of program data (indicates completion of automatic program / erase)
Data Sheet M15341EJ2V0DS
24
MC-222272-X
Figure 12. Toggle Bit Timing Chart (Flash Memory)
Address (Input)
/CEf (Input)
t
AHT
t
AS
t
AHT
t
ASO
t
CEPH
/WE (Input)
/OE (Input)
t
OEH
t
OEPH
t
OEH
t
DH
t
OE
t
CEf
Valid
data out
Stop
togglingNote
I/O6, I/O2 (Input / Output)
RY (/BY) (Output)
Input data
Toggle
Toggle
Toggle
t
BUSY
Note I/O6 stops the toggle (indicates automatic program / erase completion).
Figure 13. I/O2 vs. I/O6 Timing Chart (Flash Memory)
Erase
suspended
Erase suspended input
of program command
Input of automatic
erase command
Erasure resumed
Erase suspended
Erase suspended
read
Completion of
Erasure
/WE (Input)
Erasure
erasure
read
Erase suspended input
of program command
I/O6 (Output)
I/O2 (Output)
Toggle
I/O2 and I/O6 (/CEf or /OE is used for toggle)
Figure 14. RY (/BY) (Ready / Busy) Timing Chart (Flash Memory)
/CEf (Input)
Rising edge of the last write pulse
Automatic program or erase
/WE (Input)
RY (/BY) (Output)
t
BUSY
Figure 15. /RESET and RY (/BY) Timing Chart (Flash Memory)
/WE (Input)
/RESET (Input)
t
RB
t
RP
RY (/BY) (Output)
t
READY
Data Sheet M15341EJ2V0DS
25
MC-222272-X
Figure 16. Write CIOf Timing Chart (Flash Memory)
Falling edge of last write pulse
/CEf, /WE (Input)
CIOf (Input)
Input determined
t
AH
t
AS
Figure 17. BYTE mode Switching Timing Chart (Flash Memory)
!
/CEf (Input)
CIOf (Input)
I/O0 - I/O14 (Output)
t
ELFL
Hi-Z
Hi-Z
Hi-Z
Data Output
I/O0-I/O14
Data Output
I/O0-I/O7
t
ACC
Data Output
I/O15
Address Input
I/O15 (Output), A−1 (Input)
A−1
t
FLQZ
Figure 18. WORD mode Switching Timing Chart (Flash Memory)
!
/CEf (Input)
CIOf (Input)
t
CEf
t
ELFH
Hi-Z
Hi-Z
Data Output
I/O0-I/O7
Data Output
I/O0-I/O14
I/O0 - I/O14 (Output)
I/O15 (Output), A−1 (Input)
Hi-Z
Address Input
Data Output
I/O15
A−1
t
FHQV
Data Sheet M15341EJ2V0DS
26
MC-222272-X
Figure 19. Read Cycle Timing Chart (SRAM)
t
RC
Address (Input)
/CE1s (Input)
t
AA
t
OH
t
CO1
CO2
t
t
HZ1
t
t
LZ1
CE2s (Input)
/OE (Input)
t
HZ2
LZ2
t
OE
t
OHZ
t
OLZ
/LB, /UB (Input)
I/O (Output)
t
BA
t
BHZ
t
BLZ
Hi-Z
Data out
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M15341EJ2V0DS
27
MC-222272-X
Figure 20. Write Cycle Timing Chart 1 (/WE Controlled) (SRAM)
t
WC
Address (Input)
t
CW1
CW2
/CE1s (Input)
CE2s (Input)
t
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
BW
/LB, /UB (Input)
t
OW
t
WHZ
t
DW
t
DH
Hi-Z
Hi-Z
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a
high level CE2s.
2. If /CE1s changes to low level at the same time or after the change of /WE to low level, or if
CE2s changes to high level at the same time or after the change of /WE to low level, the I/O
pins will remain Hi-Z state.
3. When /WE is at low level, the I/O pins are always Hi-Z. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins Hi-Z.
Data Sheet M15341EJ2V0DS
28
MC-222272-X
Figure 21. Write Cycle Timing Chart 2 (/CE1s Controlled) (SRAM)
t
WC
Address (Input)
t
AS
t
CW1
/CE1s (Input)
CE2s (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
Hi-Z
Hi-Z
Data in
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a high level
CE2s.
Data Sheet M15341EJ2V0DS
29
MC-222272-X
Figure 22. Write Cycle Timing Chart 3 (CE2s Controlled) (SRAM)
tWC
Address (Input)
/CE1s (Input)
CE2s (Input)
tCW1
tAS
tCW2
tAW
tWP
tBW
tWR
/WE (Input)
/LB, /UB (Input)
tDW
tDH
Hi-Z
Hi-Z
Data in
I/O (Input)
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a high level
CE2s.
Data Sheet M15341EJ2V0DS
30
MC-222272-X
Figure 23. Write Cycle Timing Chart 4 (/LB, /UB Controlled) (SRAM)
t
WC
Address (Input)
t
t
CW1
CW2
/CE1s (Input)
CE2s (Input)
t
AW
t
WP
t
WR
/WE (Input)
t
AS
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
Hi-Z
Hi-Z
Data in
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a high level
CE2s.
Data Sheet M15341EJ2V0DS
31
MC-222272-X
Figure 24. Data Retention Timing Chart 1 (/CE1s Controlled) (SRAM)
t
CDR
Data retention mode
t
R
VCCs
VCCs(MIN.)
/CE1s
VIH (MIN.)
V
CCDR (MIN.)
/CE1s ≥ VCCs – 0.2 V
VIL (MAX.)
VSS
Remark On the data retention mode by controlling /CE1s, the input level of CE2s must be ≥ VCCs − 0.2 V or
≤ 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in Hi-Z state.
Figure 25. Data Retention Timing Chart 2 (CE2s Controlled) (SRAM)
t
CDR
Data retention mode
t
R
VCCs
V
CCs(MIN.)
V
IH (MIN.)
V
CCDR (MIN.)
CE2s
VIL (MAX.)
CE2s ≤ 0.2 V
V
SS
Remark On the data retention mode by controlling CE2s, the other pins (/CE1s, Address, I/O, /WE, /OE, /LB, /UB)
can be in Hi-Z state.
Data Sheet M15341EJ2V0DS
32
MC-222272-X
Figure 26. Data Retention Timing Chart 3 (/LB, /UB Controlled) (SRAM)
t
CDR
Data retention mode
t
R
VCCs
V
CCs(MIN.)
/LB, /UB
VIH (MIN.)
V
CCDR (MIN.)
/LB, /UB ≥ VCCs – 0.2 V
VIL (MAX.)
VSS
Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1s and CE2s must be
≥ VCCs − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in Hi-Z state.
Flow Charts (Flash Memory)
!
Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E).
Data Sheet M15341EJ2V0DS
33
MC-222272-X
CFI Code List
(1/2)
Address A6 to A0
Data I/O15 to I/O0
Description
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
0051H
0052H
0059H
0002H
0000H
0040H
0000H
0000H
0000H
0000H
0000H
0027H
"QRY" (ASCII code)
Main command set
2 : AMD/FJ standard type
Start address of PRIMARY table
Auxiliary command set
00H : Not supported
Start address of auxiliary algorithm table
Minimum VCCf voltage (program / erase)
I/O7 to I/O4 : 1 V/bit
I/O3 to I/O0 : 100 mV/bit
1CH
0036H
Maximum VCCf voltage (program / erase)
I/O7 to I/O4 : 1 V/bit
I/O3 to I/O0 : 100 mV/bit
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
0000H
0000H
0004H
0000H
000AH
0000H
0005H
0000H
0004H
0000H
0016H
0002H
0000H
0000H
0000H
0002H
0007H
0000H
0020H
0000H
Minimum VPP voltage
Maximum VPP voltage
Typical word program time (2 N µs)
Typical buffer program time (2 N µs)
Typical sector erase time (2 N ms)
Typical chip erase time (2 N ms)
Maximum word program time (typical time × 2 N)
Maximum buffer program time (typical time × 2 N)
Maximum sector erasing time (typical time × 2 N)
Maximum chip erasing time (typical time × 2 N)
Capacity (2 N Bytes)
I/O information
2 : ×8/×16-bit organization
Maximum number of bytes when two banks are programmed (2 N)
Type of erase block
Information about erase block 1
Bit0 to 15 : y = number of sectors
Bit16 to 31 : z = size
(Z × 256 Bytes)
Data Sheet M15341EJ2V0DS
34
MC-222272-X
(2/2)
Address A6 to A0
Data I/O15 to I/O0
003EH
Description
31H
32H
33H
34H
40H
41H
42H
43H
44H
45H
Information about erase block 2
0000H
bit0 to 15 : y = number of sectors
bit16 to 31 : z = size
(z × 256 Bytes)
0000H
0001H
0050H
"PRI" (ASCII code)
0052H
0049H
0031H
Main version (ASCII code)
Minor version (ASCII code)
Address during command input
00H : Necessary
0032H
0000H
01H : Unnecessary
46H
0002H
Temporary erase suspend function
00H : Not supported
01H : Read only
02H : Read / Program
Sector group protection
00H : Not supported
47H
48H
0001H
0001H
01H : Supported
Temporary sector group protection
00H : Not supported
01H : Supported
49H
4AH
0004H
00xxH
Sector group protection algorithm
Number of sectors of bank 2
00H : Not supported
38H : MC-222272-X
4BH
4CH
4DH
0000H
0000H
0085H
Burst mode
00H : Not supported
Page mode
00H : Not supported
Minimum VACC voltage
I/O7 to I/O4 : 1 V/bit
I/O3 to I/O0 : 100 mV/bit
Maximum VACC voltage
I/O7 to I/O4 : 1 V/bit
4EH
0095H
I/O3 to I/O0 : 100 mV/bit
Boot organization
4FH
50H
00xxH
0001H
02H : Bottom boot
Temporary program suspend function
00H : Not supported
01H : Supported
Data Sheet M15341EJ2V0DS
35
MC-222272-X
Package Drawing
77-PIN TAPE FBGA (12x7)
E
ZD
ZE
B
w
S B
8
7
6
5
4
3
2
1
A
D
P N M L K J H G F E D C B A
INDEX MARK
w
S A
A
A2
y1
S
S
e
A1
y
S
φ
b
φ x M S AB
ITEM MILLIMETERS
7.0±0.1
D
E
12.0±0.1
0.2
w
1.1±0.1
A
A1
A2
e
0.26±0.05
0.84
0.8
b
0.45±0.05
0.08
x
y
0.1
y1
ZD
ZE
0.1
0.7
0.8
P77F9-80-BT3
Data Sheet M15341EJ2V0DS
36
MC-222272-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the MC-222272-X.
Type of Surface Mount Device
MC-222272F9-BT3 : 77-pin TAPE FBGA (12 × 7)
Data Sheet M15341EJ2V0DS
37
MC-222272-X
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
Previous
edition
(Previous edition → This edition)
2nd edition/ Throughout Throughout Modification
Preliminary Data Sheet → Data Sheet
CONTENTS
March 2002
−
p.5
−
p.5, 6
p.7
Deletion
Addition
Deletion
Bus Operations Table
1. Bus Operations,
Remark 3
p.7 to 9
p.12 to 19
p.20 to 22
p.23
Explanation
3. Commands,
4. Hardware Sequence Flags,
5. Hardware Data Protection
p.8
−
Addition
Sector Group Address Table
Remark 2: SPA, SUA
Remark 6
p.10
p.13
Modification Command Sequence
Addition
Addition
p.11
p.12
p.13
p.14
p.26
−
Reference comment of information
Capacitance
p.24
p.25
p.26
p.38
Deletion
Electrical Specifications
Modification DC Characteristics (Flash Memory) Note: Reference comment of information
Modification AC Test Conditions
Modification Figure 17
Figure 18
Divided Flash Memory and SRAM
Range of tACC
Range of tCEf and tFHQV
8. Flow Chart
−
p.46 to 50 Deletion
Addition
p.33
−
Reference comment of information
Data Sheet M15341EJ2V0DS
38
MC-222272-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M15341EJ2V0DS
39
MC-222272-X
Related Documents
Document Name
DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information
Document Number
M14914E
•
The information in this document is current as of March, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
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NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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