R2J20653ANPG3 [RENESAS]
Integrated Driver - MOS FET (DrMOS); 集成的驱动程序 - MOS场效应管（的DrMOS ）
| 型号： | R2J20653ANPG3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Integrated Driver - MOS FET (DrMOS) |
| 文件： | 总13页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
R2J20653ANP
Integrated Driver – MOS FET (DrMOS)
REJ03G1849-0100
Rev.1.00
Dec 07, 2009
Description
The R2J20653ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver
in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compliant with Intel 6 × 6 DrMOS specification
Built-in power MOS FET suitable for Notebook, Desktop, Server application
Low-side MOS FET with built-in SBD for lower loss and reduced ringing
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
High-frequency operation (above 1 MHz) possible
VIN operating-voltage range: 27 V max
Large average output current (Max. 35 A)
Achieve low power dissipation
Controllable driver: Remote on/off
Low-side MOS FET disabled function for DCM operation
Double thermal protection: Thermal warning & Thermal shutdown
Built-in bootstrapping switch
Small package: QFN40 (6 mm × 6 mm × 0.95 mm)
Terminal Pb-free/Halogen-free
Outline
Integrated Driver-MOS FET (DrMOS)
QFN40 package 6 mm × 6 mm
VCIN BOOT
MOS FET Driver
CGND VDRV
GH
VIN
1
10
40
11
THWN
DISBL#
LSDBL#
PWM
Driver
Pad
High-side
MOS Pad
VSWH
Low-side MOS Pad
31
20
30
21
GL PGND
(Bottom view)
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 1 of 12
R2J20653ANP
Preliminary
Block Diagram
Driver Chip
VCIN
VDRV
BOOT
GH
THWN
THDN
THWN
Boot
SW
VIN
DISBL#
High Side
MOS FET
2 μA
UVL
CGND
VCIN
Level Shifter
25 k
CGND
150 k
LSDBL#
PWM
VCIN
VSWH
Overlap
Protection.
& Logic
Input Logic
(TTL Level)
(3 state in)
Low Side
MOS FET
VDRV
20 μA
PGND
CGND
GL
Notes: 1. Truth table for the DISBL# pin.
2. Truth table for the LSDBL# pin.
DISBL# Input
"L"
Driver Chip Status
Shutdown (GL, GH = "L")
LSDBL# Input
GL Status
"L"
"L"
"Open"
"H"
Shutdown (GL, GH = "L")
Enable (GL, GH = "Active")
"Open"
"H"
"Active"
"Active"
3. Output signal from the UVL block
4. Output signal from the THWN block
For active
"H"
"H"
Thermal
Warning
UVL output
Logic Level
Normal
operating
For shutdown
Thermal Warning
Logic Level
"L"
VCIN
"L"
TIC(°C)
VL
VH
TwarnL TwarnH
5. Truth table for the THDN block
Driver IC Temp.
Driver Chip Status
< 150°C
(< 135°C on cancellation)
Enable (GL, GH = "Active")
Shutdown (GL, GH = "L")
> 150°C
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 2 of 12
R2J20653ANP
Preliminary
Pin Arrangement
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
VIN
VIN
PWM
DISBL#
THWN
CGND
GL
VIN
CGND
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
21 22 23 24 25 26 27 28 29 30
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
LSDBL#
VCIN
Pin No.
Description
Remarks
When asserted "L" signal, Low-side gate disable
1
2
3
4
Low-side gate disable
Control input voltage (+5 V input) Driver Vcc input
Gate supply voltage (+5 V input) 5 V gate drive
VDRV
BOOT
CGND
GH
Bootstrap voltage pin
Control signal ground
High-side gate signal
Input voltage
To be supplied +5 V through internal switch
5, 37, Pad
6
Should be connected to PGND externally
Pin for monitor
VIN
8 to 14, Pad
VSWH
PGND
GL
7, 15, 29 to 35, Pad Phase output/Switch output
16 to 28
36
Power ground
Low-side gate signal
Thermal warning
Signal disable
Pin for monitor
THWN
DISBL#
38
Thermal warning when over 115°C
39
Disabled when DISBL# is "L"
This pin is pulled low when internal IC over the
thermal shutdown level, 150°C.
PWM
40
PWM drive logic input
5 V logic input
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 3 of 12
R2J20653ANP
Preliminary
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Pt(25)
Rating
Units
Note
Power dissipation
25
W
1
Pt(110)
8
Average output current
Input voltage
Iout
35
A
V
VIN (DC)
–0.3 to +27
2
2, 4
2
VIN (AC)
30
Supply voltage & Drive voltage
Switch node voltage
VCIN & VDRV
VSWH (DC)
VSWH (AC)
VBOOT (DC)
VBOOT (AC)
–0.3 to +6
V
V
27
2
30
2, 4
2
BOOT voltage
I/O voltage
32
36
V
V
2, 4
2, 5
Vpwm, Vdisble,
Vlsdbl, Vthwn
–0.3 to VCIN + 0.3
THWN current
Ithwn
Tj-opr
Tstg
0 to 1.0
mA
°C
Operating junction temperature
Storage temperature
–40 to +150
–55 to +150
°C
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110°C.
2. Rated voltages are relative to voltages on the CGND and PGND pins.
3. For rated current, (+) indicates inflow.
4. The specification values indicated "AC" are limited within 100 ns.
5. VCIN + 0.3 V < 6 V
Safe Operating Area
45
40
35
30
25
Condition
20
15
VOUT = 1.3 V
VIN = 12 V
VCIN = 5 V
10 VDRV = 5 V
L = 0.45 μH
Fsw = 1 MHz
5
0
0
25
50
75
100
125
150
175
PCB Temperature (°C)
Recommended Operating Condition
Item
Symbol
Rating
Units
Note
Input voltage
Supply voltage & Drive voltage
VIN
4.5 to 22
4.5 to 5.5
V
V
VCIN & VDRV
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 4 of 12
R2J20653ANP
Preliminary
Electrical Characteristics
(Ta = 25°C, VCIN = 5 V, VDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Item
Symbol
VH
Min
4.1
3.6
—
Typ
4.3
3.8
0.5
33
Max
4.5
4.0
—
Units
V
Test Conditions
Supply
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VL
V
dUVL
ICIN
V
VH – VL
PWM = 1 MHz,
VCIN operating current
—
—
mA
f
Ton_pwm = 120 ns
VCIN disable current
ICIN-DISBL
—
—
2
mA
DISBL# = 0 V, PWM = 0 V,
LSDBL# = Open
PWM
input
PWM rising threshold
PWM falling threshold
PWM input resistance
Tri-state shutdown window
Shutdown hold-off time
Disable threshold
VH-PWM
VL-PWM
RIN-PWM
VIN-SD
3.0
0.9
10
3.4
1.2
20
3.8
1.5
40
V
V
kΩ
V
PWM = 1 V
VL-PWM
—
—
VH-PWM
—
1
tHOLD-OFF
VDISBL
*
100
1.2
2.4
2.0
0.5
2.4
1.2
–27
115
15
ns
V
DISBL#
input
0.9
1.9
—
1.5
2.9
5.0
1.0
2.9
1.5
–14
135
—
Enable threshold
VENBL
V
Input current
IDISBL
μA
kΩ
V
DISBL# = 1 V
THDN = 0.2 V
1
THDN on resistance
Low-side activation threshold
Low-side disable threshold
Input current
RTHDN
*
0.2
1.9
0.9
–56
95
LSDBL#
input
VLSDBLH
VLSDBLL
ILSDBL
V
μA
°C
°C
kΩ
μA
°C
°C
LSDBL# = 1 V
1
Thermal
warning
Warning temperature
Temperature hysteresis
THWN on resistance
THWN leakage current
Shutdown temperature
Temperature hysteresis
TTHWN
*
1
Driver IC temperature
THYS
*
—
1
RTHWN
*
0.2
—
0.5
0.001
150
15
1.0
1.0
—
THWN = 0.2 V
ILEAK
Tstdn *1
THWN = 5 V
Thermal
130
—
Driver IC temperature
1
shutdown
TDHYS
*
—
Note: 1. Reference values for design. Not 100% tested in production.
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 5 of 12
R2J20653ANP
Preliminary
Typical Application
4.5 to 22 V
+5 V
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20653A
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20653A
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
PWM1
+1.3 V
PWM2
PWM
Control
PWM3
Circuit
VCIN VDRV BOOT GH
PWM4
THWN
VIN
DISBL# R2J20653A
VSWH
NP
Power GND Signal GND
LSDBL#
PGND
GL
PWM
CGND
VCIN VDRV BOOT GH
THWN
VIN
DISBL# R2J20653A
VSWH
NP
LSDBL#
PGND
GL
PWM
CGND
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 6 of 12
R2J20653ANP
Preliminary
Pin Connection
+5 V
0.1 μF
1.0 μF
CGND
Low Side Disable Signal INPUT
VIN
(4.5 V~22 V)
0~10 Ω
CGND
10
9
8
7
6
5
4
3
2
1
PWM
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
PWM INPUT
10 μF × 4
DISBL#
THWN
VIN
CGND
PAD
PAD
PGND
10 kΩ
VIN
CGND
GL
+5 V
VSWH
PGND
10 kΩ
R2J20653ANP
VSWH
+5 V
VSWH
PAD
Thermal Shutdown
Thermal Warning
21 22 23 24 25 26 27 28 29 30
0.45 μH
Vout
PGND
PGND
Power GND Signal GND
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 7 of 12
R2J20653ANP
Preliminary
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
VCIN & DISBL#
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN
is 4.3 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 3.8 V or less. The
signal on pin DISBL# also enables or disables the circuit.
Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,
etc., to pull the DISBL# line up to VCIN are both possible.
VCIN
DISBL#
Driver State
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
L
∗
L
H
H
H
H
Open
Disable (GL, GH = L)
The pulled-down MOS FET, which is turned on when internal IC temperature becomes over thermal shutdown level, is
connected to the DISBL# pin. The detailed function is described in THDN section.
PWM & LSDBL#
The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (VCIN + 0.3 V). When the
PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is
low.
PWM
GH
L
GL
H
L
H
H
L
The LSDBL# pin is the low-side gate disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low.
Figure 1 shows the typical high-side and low-side gate switching and inductor current (IL) during Continuous
Conduction Mode (CCM) and low-side gate disabled when asserting low-side disable signal.
This pin is internally pulled up to VCIN with 150 kΩ resistor.
When low-side disable function is not used, keep this pin open or pulled up to VCIN.
CCM Operation (LSDBL# = "H" or Open mode)
IL
GH
GL
Figure 1.1 Typical Signals during CCM
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 8 of 12
R2J20653ANP
Preliminary
DCM Operation (LSDBL# = "L")
IL
0 A
GH
GL
Figure 1.2 Typical Signals during Low-Side Disable Operation
The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri-
state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in
the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become
low, a PWM input voltage of 3.4 V or more is required to make the circuit return to normal operation.
100 ns (tHOLD-OFF
)
100 ns (tHOLD-OFF)
3.4 V
1.2 V
PWM
GH
GL
100 ns (tHOLD-OFF
)
100 ns (tHOLD-OFF)
3.4 V
1.2 V
PWM
GH
GL
Figure 2
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 9 of 12
R2J20653ANP
Preliminary
The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal
operation; after the PWM input signal has stayed in the hysteresis window for 100 ns (typ.) and the tri-state detection
signal has been driven high, the transistor M1 is turned off.
When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is
asserted high signal, M1 becomes ON and shifts to normal operation.
VCIN
DISBL#
M1
20 k
Tri-state
PWM Pin
detection signal
Input
Logic
To internal control
20 k
Figure 3 Equivalent Circuit for the PWM-pin Input
THWN & THDN
This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function.
This thermal warning feature is the indication of the high temperature status.
THWN is an open drain logic output signal and need to connect a pull-up resistor (ex. 51 kΩ) to THWN for systems
with the thermal warning implementation.
When the chip temperature of the internal driver IC becomes over 115°C, thermal warning function operates.
This signal is only indication for the system controller and does not disable DrMOS operation.
When thermal warning function is not used, keep this pin open.
Thermal
warning
"H"
Normal
THWN output
Logic Level
operating
"L"
TIC (°C)
100 115
Figure 4 THWN Trigger Temperature
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 10 of 12
R2J20653ANP
Preliminary
THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.
This function makes high-side MOS FET and low-side MOS FET turn off for the device protection from abnormal high
temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system controller.
Figure 5 shows the example of two types of DISBL# connection with the system controller signal.
Driver IC Temp.
< 150°C
Driver Chip Status
Enable (GL, GH = "Active")
(< 135°C on cancellation)
> 150°C
Shutdown (GL, GH = "L")
5 V
10 k
To Internal
Logic
To Internal
Logic
DISBL#
DISBL#
10 k
2 μA
2 μA
To shutdown signal
ON/OFF signal
Thermal
Shutdown
Detection
Thermal
Shutdown
Detection
Figure 5.1 THDN Signal to the System Controller
Figure 5.2 ON/OFF Signal from the System Controller
MOS FETs
The MOS FETs incorporated in R2J20653ANP are highly suitable for synchronous-rectification buck conversion. For
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 11 of 12
R2J20653ANP
Preliminary
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
—
MASS[Typ.]
—
P-HVQFN40-p-0606-0.50
PVQN0040KC-A
HD
D
HD/2
D /2
4-C0.50
B
B
1pin
1pin
INDEX
40
40
2.2
C0.3
A
0.7
0.2
1.95
Dimension in Millimeters
Min Nom Max
5.95 6.00 6.05
5.95 6.00 6.05
Reference
Symbol
2-A section
CAV No.
Die No.
D
E
2.05
1.95
A2 0.87 0.89 0.91
f
—
—
0.20
ZD
A
0.865 0.91 0.95
X 4
e
X 4
t
S AB
A1 0.005 0.02 0.04
0.17 0.22 0.27
b1 0.16 0.20 0.24
0.50
Lp 0.40 0.50 0.60
f
S AB
b
b
x
S AB
y1
S
e
—
—
L1
x
y
y1
t
—
—
—
—
—
—
—
—
0.05
0.05
0.20
0.20
S
HD 6.15 6.20 6.25
HE 6.15 6.20 6.25
y
S
Lp
ZD
ZE
—
—
0.75
0.75
—
—
L1 0.06 0.10 0.14
c1 0.17 0.20 0.23
c2 0.17 0.22 0.27
Ordering Information
Part Name
Quantity
Shipping Container
Taping Reel
R2J20653ANP#G3
2500 pcs
REJ03G1849-0100 Rev.1.00 Dec 07, 2009
Page 12 of 12
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
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