RMLV0414E [RENESAS]
4Mb Advanced LPSRAM; 4MB先进LPSRAM
| 型号： | RMLV0414E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4Mb Advanced LPSRAM |
| 文件： | 总12页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RMLV0408E Series
4Mb Advanced LPSRAM (512k word × 8bit)
R10DS0217EJ0001
Rev.0.01
2013.09.10
Description
The RMLV0408E Series is a family of 4-Mbit static RAMs organized 524,288-word × 8-bit, fabricated by Renesas’s
high-performance Advanced LPSRAM technologies. The RMLV0408E Series has realized higher density, higher
performance and low power consumption. The RMLV0408E Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP, 32-pin TSOP II or 32-pin STSOP.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 45/55ns (max.)
Current consumption:
── Standby: 0.4µA (typ.)
Equal access and cycle times
Common data input and output
── Three state output
Directly TTL compatible
── All inputs and outputs
Battery backup operation
Part Name Information
Access
time
Temperature
Range
Part Name
Package
RMLV0408EGSP-4S2
RMLV0408EGSP-5S2
RMLV0408EGSB-4S2
RMLV0408EGSB-5S2
RMLV0408EGSA-4S2
RMLV0408EGSA-5S2
45 ns
55 ns
45 ns
55 ns
45 ns
55 ns
525-mil 32-pin plastic SOP
-40 ~ +85°C
400-mil 32-pin plastic TSOP II
8mm x 13.4mm STSOP
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10
RMLV0408E Series
Preliminary
Pin Arrangement
32-pin SOP
32-pin TSOP II
32-pin STSOP
A11
A9
A18
A16
A14
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
1
2
1
2
A8
3
3
A13
WE#
A18
A15
Vcc
A17
A16
A14
A12
A7
4
4
5
5
A6
6
6
A5
A9
7
7
A4
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
8
8
A3
9
9
A2
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
Vss
A6
A1
A5
A2
A4
A3
(Top view)
(Top view)
Pin Description
Pin name
VCC
Function
Power supply
Ground
VSS
A0 to A18
I/O0 to I/O7
CS#
Address input
Data input/output
Chip select
WE#
Write enable
Output enable
OE#
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2013.09.10
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RMLV0408E Series
Preliminary
Block Diagram
VCC
VSS
A0
A4
A5
A6
・
・
・
・
・
A7
A8
A9
Memory Matrix
2,048 x 2,048
Row
Decoder
A10
A11
A12
A13
I/O0
・
・
・
Column I/O
・
Column Decoder
Input
Data
Control
I/O7
A17
A1 A2 A3 A14 A15 A16
A18
・
・
CS#
Timing Pulse Generator
Read/Write Control
WE#
OE#
Operation Table
CS#
H
WE#
X
OE#
X
I/O0 to I/O7
High-Z
Dout
Operation
Standby
Read
L
H
L
L
L
X
Din
Write
L
H
H
High-Z
Output disable
Note 1. H: VIH L:VIL
X: VIH or VIL
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2013.09.10
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RMLV0408E Series
Preliminary
Absolute Maximum Ratings
Parameter
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
Symbol
VCC
Value
-0.5 to +4.6
-0.5*2 to VCC+0.3*3
0.7
unit
V
VT
V
PT
W
°C
°C
°C
Operation temperature
Topr
Tstg
Tbias
-40 to +85
-65 to +150
-40 to +85
Storage temperature range
Storage temperature range under bias
Note 2. -3.0V for pulse ≤ 30ns (full width at half maximum)
3. Maximum voltage is +4.6V.
DC Operating Conditions
Parameter
Symbol
VCC
VSS
VIH
Min.
2.7
0
Typ.
3.0
0
Max.
Unit
V
Note
Supply voltage
3.6
0
V
Input high voltage
Input low voltage
2.2
-0.3
-40
─
VCC+0.3
0.6
V
VIL
─
V
4
Ambient temperature range
Ta
─
+85
°C
Note 4. -3.0V for pulse ≤ 30ns (full width at half maximum)
DC Characteristics
Parameter
Symbol
| ILI |
Min.
Typ.
Max.
1
Unit
Test conditions
Input leakage current
─
─
A Vin = VSS to VCC
Output leakage current
CS# =VIH or OE# =VIH or WE#= VIL,
| ILO
ICC
|
─
─
─
─
─
─
1
A
mA
mA
VI/O = VSS to VCC
CS# =VIL,
Operating current
10
20
Others = VIH/VIL, II/O = 0mA
Average operating current
Min. cycle, duty =100%, II/O = 0mA
CS# =VIL, Others = VIH/VIL
ICC1
Cycle =1s, duty =100%, II/O = 0mA
ICC2
─
─
─
2.5
0.3
mA CS# ≤ 0.2V,
VIH ≥ Vcc-0.2V, VIL ≤ 0.2V
Standby current
Standby current
CS# =VIH,
ISB
0.1*5
mA
Others = VSS to VCC
─
─
─
─
0.4*5
─
2
3
5
7
A
A
A
A
~+25°C
~+40°C
Vin = VSS to VCC
,
ISB1
CS# ≥ VCC-0.2V
─
~+70°C
─
~+85°C
Output high voltage
Output low voltage
VOH
2.4
VCC-0.2
─
─
─
─
─
─
─
V
V
V
V
IOH = -1mA
VOH2
VOL
IOH = -0.1mA
IOL = 2.1mA
IOL = 0.1mA
0.4
0.2
VOL2
─
Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
Capacitance
(Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C*2)
Parameter
Input capacitance
Input / output capacitance
Symbol
C in
Min.
─
Typ.
─
Max.
8
Unit
pF
Test conditions
Vin =0V
Note
6
6
C I/O
─
─
10
pF
VI/O =0V
Note 6. This parameter is sampled and not 100% tested.
R10DS0217EJ0001 Rev.0.01
2013.09.10
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RMLV0408E Series
Preliminary
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)
1.4V
Input pulse levels: VIL = 0.4V, VIH = 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
RL = 500 ohm
I/O
CL = 30 pF (-4S2)
CL = 50 pF (-5S2)
Read Cycle
RMLV0408EG**-4S2
RMLV0408EG**-5S2
Parameter
Symbol
Unit
Note
Min.
45
─
Max.
─
Min.
55
─
Max.
─
Read cycle time
tRC
tAA
tACS
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
45
45
22
─
55
55
30
─
Chip select access time
─
─
Output enable to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
─
─
tOH
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
─
─
7,8
7,8
─
─
0
18
18
0
20
20
7,8,9
7,8,9
0
0
Write Cycle
RMLV0408EG**-4S2
RMLV0408EG**-5S2
Parameter
Symbol
Unit
Note
10
Min.
45
35
35
35
0
Max.
─
Min.
55
50
50
40
0
Max.
─
Write cycle time
tWC
tAW
tCW
tWP
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to write end
Chip select to write end
─
─
─
─
Write pulse width
─
─
Address setup time to write start
Write recovery time from write end
Data to write time overlap
Data hold from write end
Output enable from write end
Output disable to output in high-Z
Write to output in high-Z
─
─
tWR
tDW
tDH
0
─
0
─
25
0
─
25
0
─
─
─
tOW
tOHZ
tWHZ
5
─
5
─
7
0
18
18
0
20
20
7,9
7,9
0
0
Note 7. This parameter is sampled and not 100% tested.
8. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, and tOHZ max is less than tOLZ
min, for any device.
9. tCHZ, tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not
referred to the I/O levels.
10. tWP is the interval between write start and write end.
A write starts when both of CS# and WE# become active
A write is performed during the overlap of a low CS#, a low WE#
A write ends when any of CS#, WE# becomes inactive.
R10DS0217EJ0001 Rev.0.01
2013.09.10
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RMLV0408E Series
Preliminary
Timing Waveforms
Read Cycle
tRC
Valid address
A0~18
tAA
tACS
CS#
*11,12,13
*12,13
tCLZ
tCHZ
VIH
WE#
WE# = “H” level
*11,12,13
tOHZ
tOE
OE#
*12,13
tOLZ
tOH
High impedance
I/O0~7
Valid Data
Note 11. tCHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to
the I/O levels.
12. This parameter is sampled and not 100% tested.
13. At any given temperature and voltage condition, tCHZ max is less than tCLZ min, and tOHZ max is less than tOLZ
min, for any device.
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RMLV0408E Series
Preliminary
Write Cycle (1) (WE# CLOCK, OE#=”H” while writing)
tWC
Valid address
A0~18
tCW
CS#
tAW
tWR
*14
tWP
WE#
OE#
I/O0~7
tAS
*15,16
tWHZ
*15,16
tOHZ
tDH
Valid Data
tDW
*17
Note 14. tWP is the interval between write start and write end.
A write starts when both of CS# and WE# become active.
A write is performed during the overlap of a low CS# and a low WE#.
A write ends when any of CS# or WE# becomes inactive.
15. tOHZ and tWHZ are defined as the time when the I/O pins enter a high-impedance state and are not referred to
the I/O levels.
16. This parameter is sampled and not 100% tested.
17. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
R10DS0217EJ0001 Rev.0.01
2013.09.10
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RMLV0408E Series
Preliminary
Write Cycle (2) (WE# CLOCK, OE# Low Fixed)
tWC
Valid address
A0~18
tCW
CS#
tAW
tWR
*18,
tWP
WE#
tAS
OE#
VIL
OE# = “L” level
*19,20
tWHZ
tOW
I/O0~7
Valid Data
tDH
*21
*21
tDW
Note 18. tWP is the interval between write start and write end.
A write starts when both of CS# and WE# become active.
A write is performed during the overlap of a low CS# and a low WE#.
A write ends when any of CS# or WE# becomes inactive.
19. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O
levels.
20. This parameter is sampled and not 100% tested.
21. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
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RMLV0408E Series
Preliminary
Write Cycle (3) (CS# CLOCK)
tWC
Valid address
A0~18
tAW
tAS
tWR
tCW
CS#
*22
tWP
WE#
OE#
OE# = “H” level
VIH
tDW
Valid Data
tDH
I/O0~7
Note 22. tWP is the interval between write start and write end.
A write starts when both of CS# and WE# become active.
A write is performed during the overlap of a low CS# and a low WE#.
A write ends when any of CS# or WE# becomes inactive.
R10DS0217EJ0001 Rev.0.01
2013.09.10
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RMLV0408E Series
Preliminary
Low VCC Data Retention Characteristics
Parameter
Symbol
Min.
1.5
Typ. Max.
Unit
V
Test conditions*24
Vin ≥ 0V,
VCC for data retention
VDR
─
0.4*23
─
─
2
3
5
7
CS# ≥ VCC-0.2V
─
─
─
─
A
A
A
A
~+25°C
~+40°C
VCC=3.0V, Vin ≥ 0V,
CS# ≥ Vcc-0.2V
Data retention current
ICCDR
─
~+70°C
~+85°C
─
Chip deselect time to data retention
Operation recovery time
tCDR
tR
0
5
─
─
─
─
ns
See retention waveform.
ms
Note 23. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
24. CS# controls address buffer, WE# buffer, OE# buffer, and I/O buffer. If CS# controls data retention mode, Vin
levels (address, WE#, OE#, I/O) can be in the high-impedance state.
Low Vcc Data Retention Timing Waveforms (CS# controlled)
CS# Controlled
VCC
2.7V
2.7V
tCDR
tR
VDR
2.2V
2.2V
CS# ≥ VCC - 0.2V
CS#
R10DS0217EJ0001 Rev.0.01
2013.09.10
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Revision History
RMLV0408E Series Data Sheet
Description
Summary
Rev.
0.01
Date
Page
2013.09.10
─
Preliminary First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2013 Renesas Electronics Corporation. All rights reserved.
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